FI20001654A - Multichip-moduli - Google Patents
Multichip-moduli Download PDFInfo
- Publication number
- FI20001654A FI20001654A FI20001654A FI20001654A FI20001654A FI 20001654 A FI20001654 A FI 20001654A FI 20001654 A FI20001654 A FI 20001654A FI 20001654 A FI20001654 A FI 20001654A FI 20001654 A FI20001654 A FI 20001654A
- Authority
- FI
- Finland
- Prior art keywords
- multichip module
- multichip
- module
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20001654A FI111197B (fi) | 2000-07-12 | 2000-07-12 | Multichip-moduli |
AU2001284066A AU2001284066A1 (en) | 2000-07-12 | 2001-07-10 | Multichip module connected to flexible, film-like substrate |
PCT/FI2001/000657 WO2002005603A1 (en) | 2000-07-12 | 2001-07-10 | Multichip module connected to flexible, film-like substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20001654 | 2000-07-12 | ||
FI20001654A FI111197B (fi) | 2000-07-12 | 2000-07-12 | Multichip-moduli |
Publications (3)
Publication Number | Publication Date |
---|---|
FI20001654A0 FI20001654A0 (fi) | 2000-07-12 |
FI20001654A true FI20001654A (fi) | 2002-01-13 |
FI111197B FI111197B (fi) | 2003-06-13 |
Family
ID=8558772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI20001654A FI111197B (fi) | 2000-07-12 | 2000-07-12 | Multichip-moduli |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU2001284066A1 (fi) |
FI (1) | FI111197B (fi) |
WO (1) | WO2002005603A1 (fi) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7610310B2 (en) | 2006-06-30 | 2009-10-27 | Intel Corporation | Method and system for the protected storage of downloaded media content via a virtualized platform |
EP2291858B1 (en) * | 2008-06-26 | 2012-03-28 | Nxp B.V. | Packaged semiconductor product and method for manufacture thereof |
GB2475563A (en) | 2009-11-24 | 2011-05-25 | Concepts For Success | Pants style garment formed with a centre strip and associated side panels |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5031027A (en) * | 1990-07-13 | 1991-07-09 | Motorola, Inc. | Shielded electrical circuit |
DE4035526A1 (de) * | 1990-11-08 | 1992-05-14 | Bosch Gmbh Robert | Elektrisches geraet, insbesondere schalt- und steuergeraet fuer kraftfahrzeuge, und verfahren zur herstellung |
DE19626126C2 (de) * | 1996-06-28 | 1998-04-16 | Fraunhofer Ges Forschung | Verfahren zur Ausbildung einer räumlichen Chipanordnung und räumliche Chipanordung |
-
2000
- 2000-07-12 FI FI20001654A patent/FI111197B/fi active
-
2001
- 2001-07-10 WO PCT/FI2001/000657 patent/WO2002005603A1/en active Application Filing
- 2001-07-10 AU AU2001284066A patent/AU2001284066A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
FI20001654A0 (fi) | 2000-07-12 |
AU2001284066A1 (en) | 2002-01-21 |
WO2002005603A1 (en) | 2002-01-17 |
FI111197B (fi) | 2003-06-13 |
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