FI118654B - Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite - Google Patents

Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite Download PDF

Info

Publication number
FI118654B
FI118654B FI20021983A FI20021983A FI118654B FI 118654 B FI118654 B FI 118654B FI 20021983 A FI20021983 A FI 20021983A FI 20021983 A FI20021983 A FI 20021983A FI 118654 B FI118654 B FI 118654B
Authority
FI
Finland
Prior art keywords
data
output
input
multiplier
multiplication
Prior art date
Application number
FI20021983A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI20021983A (fi
FI20021983A0 (fi
Inventor
Petri Liuha
David Guevorkian
Aki Launiainen
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Publication of FI20021983A0 publication Critical patent/FI20021983A0/fi
Priority to FI20021983A priority Critical patent/FI118654B/fi
Priority to CNB2003801083374A priority patent/CN100530168C/zh
Priority to EP03810471A priority patent/EP1576493B1/en
Priority to AT03810471T priority patent/ATE382901T1/de
Priority to DE60318494T priority patent/DE60318494T2/de
Priority to PCT/FI2003/000819 priority patent/WO2004042599A1/en
Priority to AU2003276291A priority patent/AU2003276291A1/en
Priority to KR1020057007985A priority patent/KR100715770B1/ko
Priority to TW092130872A priority patent/TWI266233B/zh
Priority to US10/703,162 priority patent/US7774400B2/en
Publication of FI20021983A publication Critical patent/FI20021983A/fi
Application granted granted Critical
Publication of FI118654B publication Critical patent/FI118654B/fi

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/16Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3868Bypass control, i.e. possibility to transfer an operand unchanged to the output

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
  • Hardware Redundancy (AREA)
  • Advance Control (AREA)
  • Fishing Rods (AREA)
  • Forklifts And Lifting Vehicles (AREA)
  • Preliminary Treatment Of Fibers (AREA)
  • Multi Processors (AREA)
FI20021983A 2002-11-06 2002-11-06 Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite FI118654B (fi)

Priority Applications (10)

Application Number Priority Date Filing Date Title
FI20021983A FI118654B (fi) 2002-11-06 2002-11-06 Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite
DE60318494T DE60318494T2 (de) 2002-11-06 2003-11-05 Verfahren, einrichtung und system zur durchführung von kalkulationsoperationen
EP03810471A EP1576493B1 (en) 2002-11-06 2003-11-05 Method, device and system for performing calculation operations
AT03810471T ATE382901T1 (de) 2002-11-06 2003-11-05 Verfahren, einrichtung und system zur durchführung von kalkulationsoperationen
CNB2003801083374A CN100530168C (zh) 2002-11-06 2003-11-05 用于执行计算操作的系统、方法及设备
PCT/FI2003/000819 WO2004042599A1 (en) 2002-11-06 2003-11-05 Method and a system for performing calculation operations and a device
AU2003276291A AU2003276291A1 (en) 2002-11-06 2003-11-05 Method and a system for performing calculation operations and a device
KR1020057007985A KR100715770B1 (ko) 2002-11-06 2003-11-05 연산을 수행하는 방법 및 시스템 및 장치
TW092130872A TWI266233B (en) 2002-11-06 2003-11-05 Method and system for performing a calculation operation and a device
US10/703,162 US7774400B2 (en) 2002-11-06 2003-11-06 Method and system for performing calculation operations and a device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20021983A FI118654B (fi) 2002-11-06 2002-11-06 Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite
FI20021983 2002-11-06

Publications (3)

Publication Number Publication Date
FI20021983A0 FI20021983A0 (fi) 2002-11-06
FI20021983A FI20021983A (fi) 2004-07-16
FI118654B true FI118654B (fi) 2008-01-31

Family

ID=8564892

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20021983A FI118654B (fi) 2002-11-06 2002-11-06 Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite

Country Status (10)

Country Link
US (1) US7774400B2 (zh)
EP (1) EP1576493B1 (zh)
KR (1) KR100715770B1 (zh)
CN (1) CN100530168C (zh)
AT (1) ATE382901T1 (zh)
AU (1) AU2003276291A1 (zh)
DE (1) DE60318494T2 (zh)
FI (1) FI118654B (zh)
TW (1) TWI266233B (zh)
WO (1) WO2004042599A1 (zh)

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8856201B1 (en) 2004-11-10 2014-10-07 Altera Corporation Mixed-mode multiplier using hard and soft logic circuitry
DE102005011374B3 (de) * 2005-03-11 2006-07-13 Infineon Technologies Ag Sicheres und schnelles Rechenwerk für Addiereschaltungen von Kryptographieprozessoren
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
US8266199B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
US8266198B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8041759B1 (en) 2006-02-09 2011-10-18 Altera Corporation Specialized processing block for programmable logic device
US7836117B1 (en) 2006-04-07 2010-11-16 Altera Corporation Specialized processing block for programmable logic device
US7822799B1 (en) 2006-06-26 2010-10-26 Altera Corporation Adder-rounder circuitry for specialized processing block in programmable logic device
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US7814137B1 (en) 2007-01-09 2010-10-12 Altera Corporation Combined interpolation and decimation filter for programmable logic device
US8650231B1 (en) 2007-01-22 2014-02-11 Altera Corporation Configuring floating point operations in a programmable device
US7865541B1 (en) 2007-01-22 2011-01-04 Altera Corporation Configuring floating point operations in a programmable logic device
US8645450B1 (en) 2007-03-02 2014-02-04 Altera Corporation Multiplier-accumulator circuitry and methods
US20080225939A1 (en) * 2007-03-15 2008-09-18 Jiun-In Guo Multifunctional video encoding circuit system
KR20080085423A (ko) * 2007-03-20 2008-09-24 엘지전자 주식회사 Bma 연산기 및 이를 이용한 인코더
US20090063609A1 (en) * 2007-06-08 2009-03-05 Honkai Tam Static 4:2 Compressor with Fast Sum and Carryout
US7958180B2 (en) * 2007-07-05 2011-06-07 International Business Machines Corporation Multiplier engine
US7949699B1 (en) 2007-08-30 2011-05-24 Altera Corporation Implementation of decimation filter in integrated circuit device using ram-based data storage
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8307023B1 (en) 2008-10-10 2012-11-06 Altera Corporation DSP block for implementing large multiplier on a programmable integrated circuit device
US8468192B1 (en) 2009-03-03 2013-06-18 Altera Corporation Implementing multipliers in a programmable integrated circuit device
US8706790B1 (en) 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US8645449B1 (en) 2009-03-03 2014-02-04 Altera Corporation Combined floating point adder and subtractor
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8396914B1 (en) 2009-09-11 2013-03-12 Altera Corporation Matrix decomposition in an integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
WO2011044398A2 (en) * 2009-10-07 2011-04-14 Qsigma, Inc. Computer for amdahl-compliant algorithms like matrix inversion
US7948267B1 (en) 2010-02-09 2011-05-24 Altera Corporation Efficient rounding circuits and methods in configurable integrated circuit devices
US8539016B1 (en) 2010-02-09 2013-09-17 Altera Corporation QR decomposition in an integrated circuit device
US8601044B2 (en) 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8484265B1 (en) 2010-03-04 2013-07-09 Altera Corporation Angular range reduction in an integrated circuit device
US8510354B1 (en) 2010-03-12 2013-08-13 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en) 2010-03-25 2013-09-17 Altera Corporation Solving linear matrices in an integrated circuit device
US8589463B2 (en) 2010-06-25 2013-11-19 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en) 2010-08-19 2013-11-05 Altera Corporation Matrix operations in an integrated circuit device
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8812576B1 (en) 2011-09-12 2014-08-19 Altera Corporation QR decomposition in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8762443B1 (en) 2011-11-15 2014-06-24 Altera Corporation Matrix operations in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9588765B2 (en) * 2014-09-26 2017-03-07 Intel Corporation Instruction and logic for multiplier selectors for merging math functions
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US9846623B2 (en) 2015-08-20 2017-12-19 Qsigma, Inc. Simultaneous multi-processor apparatus applicable to acheiving exascale performance for algorithms and program systems
CN111651205B (zh) * 2016-04-26 2023-11-17 中科寒武纪科技股份有限公司 一种用于执行向量内积运算的装置和方法
CN111857822B (zh) * 2016-08-05 2024-04-05 中科寒武纪科技股份有限公司 一种运算装置及其操作方法
US20180113840A1 (en) * 2016-10-25 2018-04-26 Wisconsin Alumni Research Foundation Matrix Processor with Localized Memory
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
US11893393B2 (en) 2017-07-24 2024-02-06 Tesla, Inc. Computational array microprocessor system with hardware arbiter managing memory requests
US10671349B2 (en) * 2017-07-24 2020-06-02 Tesla, Inc. Accelerated mathematical engine
EP3480710A1 (en) * 2017-11-03 2019-05-08 Nokia Technologies Oy Computer architectures and instructions for multiplication
US11561791B2 (en) 2018-02-01 2023-01-24 Tesla, Inc. Vector computational unit receiving data elements in parallel from a last row of a computational array
WO2021102382A1 (en) * 2019-11-20 2021-05-27 Mentium Technologies Inc. Data processing system configured for separated computations for positive and negative data
US11914447B1 (en) 2019-11-20 2024-02-27 Mentium Technologies Inc. Approximate computation in digital systems using bit partitioning
CN113395551A (zh) * 2021-07-20 2021-09-14 珠海极海半导体有限公司 处理器、npu芯片和电子设备
CN115138208B (zh) * 2022-09-06 2022-11-25 山东超华环保智能装备有限公司 数据处理器及包含该处理器的一种废气智能处理系统

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8718488D0 (en) * 1987-08-05 1987-09-09 British Petroleum Co Plc Chemical process
US5204828A (en) * 1989-02-10 1993-04-20 Intel Corporation Bus apparatus having hold registers for parallel processing in a microprocessor
US4965762A (en) * 1989-09-15 1990-10-23 Motorola Inc. Mixed size radix recoded multiplier
US5299320A (en) * 1990-09-03 1994-03-29 Matsushita Electric Industrial Co., Ltd. Program control type vector processor for executing a vector pipeline operation for a series of vector data which is in accordance with a vector pipeline
US5420815A (en) * 1991-10-29 1995-05-30 Advanced Micro Devices, Inc. Digital multiplication and accumulation system
US5220525A (en) * 1991-11-04 1993-06-15 Motorola, Inc. Recoded iterative multiplier
JP3140187B2 (ja) * 1992-07-23 2001-03-05 アイシン・エィ・ダブリュ株式会社 車両用経路誘導装置
JP3546437B2 (ja) * 1993-03-31 2004-07-28 ソニー株式会社 適応形ビデオ信号演算処理装置
US6058473A (en) * 1993-11-30 2000-05-02 Texas Instruments Incorporated Memory store from a register pair conditional upon a selected status bit
US5646877A (en) * 1995-05-25 1997-07-08 Texas Instruments Incorporated High radix multiplier architecture
JPH09305401A (ja) * 1996-05-13 1997-11-28 Mitsubishi Electric Corp コンピュータ及びコンパイラ
US5825680A (en) * 1996-06-21 1998-10-20 Digital Equipment Corporation Method and apparatus for performing fast division
JP3678512B2 (ja) * 1996-08-29 2005-08-03 富士通株式会社 乗算回路、該乗算回路を構成する加算回路、該乗算回路の部分積ビット圧縮方法、および、該乗算回路を適用した大規模半導体集積回路
KR100291383B1 (ko) * 1996-11-18 2001-09-17 윤종용 디지털신호처리를위한명령을지원하는모듈계산장치및방법
US5875125A (en) * 1997-07-07 1999-02-23 International Business Machines Corporation X+2X adder with multi-bit generate/propagate circuit
US6175911B1 (en) * 1998-08-21 2001-01-16 Advanced Micro Devices, Inc. Method and apparatus for concurrently executing multiplication and iterative operations
CN1109992C (zh) * 1998-11-26 2003-05-28 松下电器产业株式会社 运算装置和使用运算装置的图象处理装置
JP2000322235A (ja) * 1999-05-07 2000-11-24 Sony Corp 情報処理装置

Also Published As

Publication number Publication date
US20040148321A1 (en) 2004-07-29
FI20021983A (fi) 2004-07-16
WO2004042599A1 (en) 2004-05-21
TW200414023A (en) 2004-08-01
FI20021983A0 (fi) 2002-11-06
DE60318494T2 (de) 2009-01-15
US7774400B2 (en) 2010-08-10
CN100530168C (zh) 2009-08-19
AU2003276291A1 (en) 2004-06-07
KR20050065672A (ko) 2005-06-29
KR100715770B1 (ko) 2007-05-08
TWI266233B (en) 2006-11-11
CN1735880A (zh) 2006-02-15
EP1576493B1 (en) 2008-01-02
DE60318494D1 (de) 2008-02-14
ATE382901T1 (de) 2008-01-15
EP1576493A1 (en) 2005-09-21

Similar Documents

Publication Publication Date Title
FI118654B (fi) Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite
FI118612B (fi) Menetelmä ja järjestelmä laskuoperaatioiden suorittamiseksi ja laite
KR101173405B1 (ko) 부스 곱셈 방법들 및 시스템들을 위한 전력-효율적인 부호 확장
US7107305B2 (en) Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
US6473529B1 (en) Sum-of-absolute-difference calculator for motion estimation using inversion and carry compensation with full and half-adders
US6601077B1 (en) DSP unit for multi-level global accumulation
Olivieri Design of synchronous and asynchronous variable-latency pipelined multipliers
WO2008073917A2 (en) Programmable video signal processor for video compression and decompression
US6675286B1 (en) Multimedia instruction set for wide data paths
Tyler et al. AltiVec/sup TM: bringing vector technology to the PowerPC/sup TM/processor family
Olivares et al. SAD computation based on online arithmetic for motion estimation
FI115862B (fi) Menetelmä ja järjestelmä kertolaskuoperaation suorittamiseksi ja laite
KR20080094812A (ko) 개선된 감소 트리 회로를 갖는 부스 곱셈기
WO2002073395A2 (en) A method and apparatus for multiplication and/or modular reduction processing
Furht Processor architectures for multimedia: a survey
Chen et al. Design methodology of a hardware-efficiency VLIW architecture with highly adaptable data path
Atitallah et al. HW/SW FPGA architecture for a flexible motion estimation
KR100434391B1 (ko) 디에스피 프로세서 및 마이크로프로세서의 실시간영상데이터 처리를 위한 연산회로 및 그 연산방법
Chen et al. An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder
CN100370834C (zh) 多模图像编解码芯片中的系数缩放计算模块
Liu et al. A SIMD video signal processor with efficient data organization
Chen et al. Application-specific data path for highly efficient computation of multistandard video codecs
Guevorkian et al. A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
Furht Processor architectures for multimedia
Matutino et al. RNS-Based Embedded Processor Design

Legal Events

Date Code Title Description
FG Patent granted

Ref document number: 118654

Country of ref document: FI

MM Patent lapsed