FI115417B - Menetelmä, laite ja järjestelmä informaation lähettämiseksi langoitetulla-TAI-väylällä - Google Patents

Menetelmä, laite ja järjestelmä informaation lähettämiseksi langoitetulla-TAI-väylällä Download PDF

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Publication number
FI115417B
FI115417B FI950949A FI950949A FI115417B FI 115417 B FI115417 B FI 115417B FI 950949 A FI950949 A FI 950949A FI 950949 A FI950949 A FI 950949A FI 115417 B FI115417 B FI 115417B
Authority
FI
Finland
Prior art keywords
driver
bus
low
signal
line
Prior art date
Application number
FI950949A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI950949A0 (fi
FI950949A7 (fi
Inventor
Nitin Sarangdhar
Samuel E Calvin
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22764947&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=FI115417(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Intel Corp filed Critical Intel Corp
Publication of FI950949A0 publication Critical patent/FI950949A0/fi
Publication of FI950949A7 publication Critical patent/FI950949A7/fi
Application granted granted Critical
Publication of FI115417B publication Critical patent/FI115417B/fi

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
FI950949A 1994-03-01 1995-03-01 Menetelmä, laite ja järjestelmä informaation lähettämiseksi langoitetulla-TAI-väylällä FI115417B (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/206,091 US5659689A (en) 1994-03-01 1994-03-01 Method and apparatus for transmitting information on a wired-or bus
US20609194 1994-03-01

Publications (3)

Publication Number Publication Date
FI950949A0 FI950949A0 (fi) 1995-03-01
FI950949A7 FI950949A7 (fi) 1995-09-02
FI115417B true FI115417B (fi) 2005-04-29

Family

ID=22764947

Family Applications (1)

Application Number Title Priority Date Filing Date
FI950949A FI115417B (fi) 1994-03-01 1995-03-01 Menetelmä, laite ja järjestelmä informaation lähettämiseksi langoitetulla-TAI-väylällä

Country Status (6)

Country Link
US (1) US5659689A (en, 2012)
FI (1) FI115417B (en, 2012)
GB (1) GB2287162B (en, 2012)
NL (1) NL195000C (en, 2012)
SG (1) SG47008A1 (en, 2012)
TW (1) TW262545B (en, 2012)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6092212A (en) * 1997-12-22 2000-07-18 Intel Corporation Method and apparatus for driving a strobe signal
US6411802B1 (en) * 1999-03-15 2002-06-25 Bellsouth Intellectual Property Management Corporation Wireless backup telephone device
US6704830B1 (en) * 2000-01-05 2004-03-09 Tektronix, Inc. Apparatus for wire-or bus expansion between two instrument chassis
US20020091855A1 (en) * 2000-02-02 2002-07-11 Yechiam Yemini Method and apparatus for dynamically addressing and routing in a data network
US20040148441A1 (en) * 2003-01-20 2004-07-29 Fanuc Ltd. Device and method for transmitting wired or signal between two systems
DE10347301B4 (de) * 2003-10-08 2007-12-13 Infineon Technologies Ag Schaltung mit einem Bus mit mehreren Empfängern
WO2018022126A1 (en) * 2016-07-27 2018-02-01 Hubbell Incorporated Systems, apparatuses and methods for dual line inbound detection on a data communication bus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4120029A (en) * 1976-12-27 1978-10-10 Honeywell Information Systems, Inc. Method and apparatus for recovering a signal transferred over a common bus in a data processing system
US4500988A (en) * 1982-03-08 1985-02-19 Sperry Corporation VLSI Wired-OR driver/receiver circuit
DE3374238D1 (en) * 1983-07-08 1987-12-03 Ibm A synchronisation mechanism for a multiprocessing system
US5029076A (en) * 1986-01-29 1991-07-02 Digital Equipment Corporation Apparatus and method for providing a settling time cycle for a system bus in a data processing system
US5448591A (en) * 1990-06-24 1995-09-05 Next, Inc. Method and apparatus for clock and data delivery on a bus

Also Published As

Publication number Publication date
FI950949A0 (fi) 1995-03-01
NL195000C (nl) 2003-05-08
NL9500385A (nl) 1995-10-02
SG47008A1 (en) 1998-03-20
GB9500966D0 (en) 1995-03-08
TW262545B (en, 2012) 1995-11-11
GB2287162B (en) 1998-09-16
FI950949A7 (fi) 1995-09-02
US5659689A (en) 1997-08-19
GB2287162A (en) 1995-09-06

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