FI113113B - Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi - Google Patents

Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi Download PDF

Info

Publication number
FI113113B
FI113113B FI20012257A FI20012257A FI113113B FI 113113 B FI113113 B FI 113113B FI 20012257 A FI20012257 A FI 20012257A FI 20012257 A FI20012257 A FI 20012257A FI 113113 B FI113113 B FI 113113B
Authority
FI
Finland
Prior art keywords
den
integrated circuit
att
integrerade
integrerad
Prior art date
Application number
FI20012257A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI20012257A (fi
FI20012257A0 (fi
Inventor
Janne Takala
Sami Maekelae
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Priority to FI20012257A priority Critical patent/FI113113B/fi
Publication of FI20012257A0 publication Critical patent/FI20012257A0/fi
Priority to US10/298,307 priority patent/US7127632B2/en
Priority to AU2002342943A priority patent/AU2002342943A1/en
Priority to EP02779595A priority patent/EP1449051A1/de
Priority to CNA028230264A priority patent/CN1602459A/zh
Priority to CNA2008100992213A priority patent/CN101311871A/zh
Priority to PCT/FI2002/000918 priority patent/WO2003044644A1/en
Publication of FI20012257A publication Critical patent/FI20012257A/fi
Application granted granted Critical
Publication of FI113113B publication Critical patent/FI113113B/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
FI20012257A 2001-11-20 2001-11-20 Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi FI113113B (fi)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FI20012257A FI113113B (fi) 2001-11-20 2001-11-20 Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi
US10/298,307 US7127632B2 (en) 2001-11-20 2002-11-18 Method and device for synchronizing integrated circuits
AU2002342943A AU2002342943A1 (en) 2001-11-20 2002-11-19 Method and device for synchronising integrated circuits
EP02779595A EP1449051A1 (de) 2001-11-20 2002-11-19 Verfahren und einrichtung zum synchronisieren integrierter schaltungen
CNA028230264A CN1602459A (zh) 2001-11-20 2002-11-19 用于同步集成电路的方法和设备
CNA2008100992213A CN101311871A (zh) 2001-11-20 2002-11-19 用于同步集成电路的方法和设备
PCT/FI2002/000918 WO2003044644A1 (en) 2001-11-20 2002-11-19 Method and device for synchronising integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20012257A FI113113B (fi) 2001-11-20 2001-11-20 Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi
FI20012257 2001-11-20

Publications (3)

Publication Number Publication Date
FI20012257A0 FI20012257A0 (fi) 2001-11-20
FI20012257A FI20012257A (fi) 2003-05-21
FI113113B true FI113113B (fi) 2004-02-27

Family

ID=8562295

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20012257A FI113113B (fi) 2001-11-20 2001-11-20 Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi

Country Status (6)

Country Link
US (1) US7127632B2 (de)
EP (1) EP1449051A1 (de)
CN (2) CN101311871A (de)
AU (1) AU2002342943A1 (de)
FI (1) FI113113B (de)
WO (1) WO2003044644A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI116439B (fi) * 2004-06-04 2005-11-15 Nokia Corp Videon ja audion synkronointi
US8938628B2 (en) * 2011-03-03 2015-01-20 Acacia Communications, Inc. Staggered power-up and synchronized reset for a large ASIC or FPGA
CN103312427B (zh) * 2012-03-06 2017-07-28 马维尔国际有限公司 同步至少两套时间驱动引擎的系统和方法
CN104145514B (zh) * 2012-08-01 2018-03-13 华为技术有限公司 用于同步的方法、装置及系统
CN103684728B (zh) * 2012-09-04 2016-11-02 中国航空工业集团公司第六三一研究所 Fc网络时钟同步误差补偿方法
DE102016222618A1 (de) * 2016-11-17 2018-05-17 Robert Bosch Gmbh Verfahren zum Überwachen eines Zeitgebers einer integrierten Schaltung

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1305029A (de) 1969-11-13 1973-01-31
US4426637A (en) * 1979-02-26 1984-01-17 Multi-Elmac Company Combination encoder-decoder integrated circuit device
JPS6227813A (ja) 1985-07-29 1987-02-05 Hitachi Ltd 位相同期方式
JPS63238714A (ja) 1986-11-26 1988-10-04 Hitachi Ltd クロック供給システム
US4750010A (en) * 1987-01-02 1988-06-07 Eastman Kodak Company Circuit for generating center pulse width modulated waveforms and non-impact printer using same
GB8705022D0 (en) 1987-03-04 1987-04-08 Lucas Elect Electron Syst Multiplex control system
US4833695A (en) 1987-09-08 1989-05-23 Tektronix, Inc. Apparatus for skew compensating signals
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
CA2091962A1 (en) * 1992-03-31 1993-10-01 Mark L. Witsaman Clock synchronization system
US5394114A (en) 1992-04-30 1995-02-28 National Semiconductor Corporation One nanosecond resolution programmable waveform generator
JP3395210B2 (ja) * 1992-06-30 2003-04-07 ソニー株式会社 同期信号検出器及び同期信号検出方法
JP2996328B2 (ja) * 1992-12-17 1999-12-27 三菱電機株式会社 半導体集積回路、およびそれを用いた半導体集積回路組合回路
FI101833B (fi) 1994-07-13 1998-08-31 Nokia Telecommunications Oy Menetelmä ja järjestelmä kaapelointiviiveen automaattiseksi kompensoim iseksi kellosignaalin jakelujärjestelmässä
US5652627A (en) * 1994-09-27 1997-07-29 Lucent Technologies Inc. System and method for reducing jitter in a packet-based transmission network
JP2771464B2 (ja) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路
US5486783A (en) * 1994-10-31 1996-01-23 At&T Corp. Method and apparatus for providing clock de-skewing on an integrated circuit board
US5852728A (en) * 1995-01-12 1998-12-22 Hitachi, Ltd. Uninterruptible clock supply apparatus for fault tolerant computer system
US5715438A (en) * 1995-07-19 1998-02-03 International Business Machines Corporation System and method for providing time base adjustment
GB2347287B (en) 1995-09-19 2000-10-25 Fujitsu Ltd Digital phase control circuit and pll circuit
US5699392A (en) * 1995-11-06 1997-12-16 Stellar One Corporation Method and system for the recovery of an encoder clock from an MPEG-2 transport stream
DE19625195A1 (de) * 1996-06-24 1998-01-02 Siemens Ag Synchronisationsverfahren
US5905869A (en) * 1996-09-27 1999-05-18 Hewlett-Packard, Co. Time of century counter synchronization using a SCI interconnect
US5896524A (en) * 1997-02-06 1999-04-20 Digital Equipment Corporation Off-line clock synchronization for multiprocessor event traces
US5875320A (en) * 1997-03-24 1999-02-23 International Business Machines Corporation System and method for synchronizing plural processor clocks in a multiprocessor system
US6055644A (en) 1997-05-30 2000-04-25 Hewlett-Packard Company Multi-channel architecture with channel independent clock signals
JPH11194850A (ja) 1997-09-19 1999-07-21 Lsi Logic Corp 集積回路用クロック分配ネットワークおよびクロック分配方法
US6108389A (en) * 1997-12-11 2000-08-22 Motorola, Inc. Synchronization of internal coder-decoders of multiple microprocessors
US5958060A (en) * 1998-01-02 1999-09-28 General Electric Company Method and apparatus for clock control and synchronization
EP1064589B1 (de) * 1998-03-27 2003-05-14 Siemens Aktiengesellschaft Verfahren zur synchronisation einer lokalen auf eine zentrale zeitbasis, und vorrichtung zur durchführung des verfahrens mit bevorzugen verwendungen
DE19929337C2 (de) * 1999-06-26 2002-04-25 Alcatel Sa Verfahren zum Generieren eines Taktes für den Rückkanal eines bidirektionalen Punkt-zu-Mehrpunkt Netzwerkes
US6587694B1 (en) * 1999-09-24 2003-07-01 Agere Systems Inc. Clock synchronization between wireless devices during cradled time
US7856543B2 (en) 2001-02-14 2010-12-21 Rambus Inc. Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream
JP3932452B2 (ja) * 2001-09-27 2007-06-20 ソニー株式会社 通信装置および方法、並びにプログラム

Also Published As

Publication number Publication date
US20030094983A1 (en) 2003-05-22
AU2002342943A1 (en) 2003-06-10
US7127632B2 (en) 2006-10-24
EP1449051A1 (de) 2004-08-25
CN101311871A (zh) 2008-11-26
FI20012257A (fi) 2003-05-21
WO2003044644A1 (en) 2003-05-30
FI20012257A0 (fi) 2001-11-20
CN1602459A (zh) 2005-03-30

Similar Documents

Publication Publication Date Title
CN1543604B (zh) 带有片上后台调试系统的数据处理系统和相关方法
EP3254203B1 (de) Empfangstaktkalibrierung für einen seriellen bus
CN107003958A (zh) 带内中断时间戳
US20110013650A1 (en) Pseudo-synchronous time division multiplexing
US20150199287A1 (en) Camera control interface extension with in-band interrupt
US20150199295A1 (en) Receive clock calibration for a serial bus
US8386828B1 (en) Circuit for estimating latency through a FIFO buffer
CA2266029A1 (en) Low power serial protocol translator for use in multi-circuit board electronic systems
US7260734B2 (en) Method and circuit for transmitting data between systems having different clock speeds
CN100466507C (zh) 传感器或执行元件连接到总线系统上的方法和装置
FI113113B (fi) Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi
US11178055B2 (en) Methods and apparatus for providing deterministic latency for communications interfaces
US7831853B2 (en) Circuit comprising mutually asynchronous circuit modules
US9479310B2 (en) Method, apparatus and system to communicate with a device
KR100826496B1 (ko) 반도체 집적 회로 장치 및 그 동작 방법
US20030174655A1 (en) Apparatus & method for caching counter values in network packet traffic sampling
CN1848713B (zh) 时分复用系统子节点帧同步实现方法及实现装置
FR2678122B1 (fr) Dispositif de mesure de debit de circuits virtuels empruntant une voie de communication a multiplexage temporel asynchrone.
KR19990029006A (ko) 확장 칩 선택 리셋 장치 및 방법
Liljeberg et al. Asynchronous interface for locally clocked modules in ULSI systems
US20230125743A1 (en) Providing frames at a network port
US6311235B1 (en) UART support for address bit on seven bit frames
JP2003016026A (ja) シリアル通信回路
KR100855430B1 (ko) 시스템의 대기시간 설정 장치
JPS62133841A (ja) 非同期直列方式デ−タ通信システム

Legal Events

Date Code Title Description
MM Patent lapsed