ES8308109A1 - "un subsistema de almacenamiento para una instalacion de tratamiento de datos". - Google Patents
"un subsistema de almacenamiento para una instalacion de tratamiento de datos".Info
- Publication number
- ES8308109A1 ES8308109A1 ES516477A ES516477A ES8308109A1 ES 8308109 A1 ES8308109 A1 ES 8308109A1 ES 516477 A ES516477 A ES 516477A ES 516477 A ES516477 A ES 516477A ES 8308109 A1 ES8308109 A1 ES 8308109A1
- Authority
- ES
- Spain
- Prior art keywords
- series
- storage
- backing store
- data
- caching buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
Abstract
SUBSISTEMA DE MEMORIA PARA INSTALACION DE TRATAMIENTO DE DATOS. SE TRATA DE UNA JERARQUIA DE SUBSISTEMA DE MEMORIA QUE TIENE UN COMPENSADOR DE OCULTACION (15) Y UNA MEMORIA AUXILIAR (14). UN REPERTORIO INDICA LOS DATOS ALMACENADOS EN EL COMPENSADOR DE OCULTACION. AL PRODUCIRSE UN ACCESO A LA MEMORIA DE DATOS, DENTRO DE UNA SERIE DE TALES ACCESOS, QUE DE POR RESULTADO UNA INDICACION DE FALTA EN OCULTACION, TODOS LOS ACCESOS SUCESIVOS DE LA SERIE SE EFECTUAN A LA MEMORIA AUXILIAR, EXCLUYENDOSE EL COMPENSADOR DE OCULTACION, AUN CUANDO ESTE DISPONGA DE UN ESPACIO DE ALMACENAMIENTO ASIGNADO PARA DICHA TRANSFERENCIA DE DATOS. EN LA SERIE SE PONEN A LA MEMORIA AUXILIAR UNOS LIMITES SELECCIONADOS, TALES COMO LOS DE RECIBIR UNA INDICACION DE FINAL DE CADENA DE ORDENES DESDE UNA UNIDAD USUARIA, CRUZAR UNOS LIMITES DE CILINDRO, RECIBIR UNA DIRECCION DE ACCESO FUERA DE LIMITES, O RECIBIR CIERTAS ORDENES DE DISPOSITIVO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/311,570 US4500954A (en) | 1981-10-15 | 1981-10-15 | Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass |
Publications (2)
Publication Number | Publication Date |
---|---|
ES516477A0 ES516477A0 (es) | 1983-07-01 |
ES8308109A1 true ES8308109A1 (es) | 1983-07-01 |
Family
ID=23207489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES516477A Expired ES8308109A1 (es) | 1981-10-15 | 1982-10-14 | "un subsistema de almacenamiento para una instalacion de tratamiento de datos". |
Country Status (7)
Country | Link |
---|---|
US (1) | US4500954A (es) |
EP (1) | EP0077451B1 (es) |
JP (1) | JPS5876956A (es) |
AU (1) | AU548748B2 (es) |
CA (1) | CA1187199A (es) |
DE (1) | DE3278651D1 (es) |
ES (1) | ES8308109A1 (es) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58133696A (ja) * | 1982-02-03 | 1983-08-09 | Hitachi Ltd | 記憶制御方式 |
US4635194A (en) * | 1983-05-02 | 1987-01-06 | International Business Machines Corporation | Instruction buffer bypass apparatus |
US4603380A (en) * | 1983-07-01 | 1986-07-29 | International Business Machines Corporation | DASD cache block staging |
JPH0630075B2 (ja) * | 1984-08-31 | 1994-04-20 | 株式会社日立製作所 | キャッシュメモリを有するデータ処理装置 |
JPS62102344A (ja) * | 1985-10-29 | 1987-05-12 | Fujitsu Ltd | バツフア・メモリ制御方式 |
US4958351A (en) * | 1986-02-03 | 1990-09-18 | Unisys Corp. | High capacity multiple-disk storage method and apparatus having unusually high fault tolerance level and high bandpass |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US4802125A (en) * | 1986-11-21 | 1989-01-31 | Nec Corporation | Memory access control apparatus |
US4851993A (en) * | 1987-04-20 | 1989-07-25 | Amdahl Corporation | Cache move-in bypass |
KR910000590B1 (ko) * | 1988-03-14 | 1991-01-26 | 배만희 | 컴퓨터의 미러(Mirror) 디스크램 시스템 |
US4992978A (en) * | 1988-03-31 | 1991-02-12 | Wiltron Company | Cross-path optimization in multi-task processing |
US4974156A (en) * | 1988-05-05 | 1990-11-27 | International Business Machines | Multi-level peripheral data storage hierarchy with independent access to all levels of the hierarchy |
JP2567922B2 (ja) * | 1988-08-30 | 1996-12-25 | 株式会社日立製作所 | パス制御方式 |
US4905141A (en) * | 1988-10-25 | 1990-02-27 | International Business Machines Corporation | Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification |
US5359713A (en) * | 1989-06-01 | 1994-10-25 | Legato Systems, Inc. | Method and apparatus for enhancing synchronous I/O in a computer system with a non-volatile memory and using an acceleration device driver in a computer operating system |
US4998221A (en) * | 1989-10-31 | 1991-03-05 | International Business Machines Corporation | Memory by-pass for write through read operations |
JP2826857B2 (ja) * | 1989-12-13 | 1998-11-18 | 株式会社日立製作所 | キャッシュ制御方法および制御装置 |
EP0435475B1 (en) * | 1989-12-22 | 1996-02-07 | Digital Equipment Corporation | High-performance frame buffer and cache memory system |
EP0449369B1 (en) * | 1990-03-27 | 1998-07-29 | Koninklijke Philips Electronics N.V. | A data processing system provided with a performance enhancing instruction cache |
US5255371A (en) * | 1990-04-02 | 1993-10-19 | Unisys Corporation | Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands |
US5206939A (en) * | 1990-09-24 | 1993-04-27 | Emc Corporation | System and method for disk mapping and data retrieval |
US5544347A (en) * | 1990-09-24 | 1996-08-06 | Emc Corporation | Data storage system controlled remote data mirroring with respectively maintained data indices |
US5625793A (en) * | 1991-04-15 | 1997-04-29 | International Business Machines Corporation | Automatic cache bypass for instructions exhibiting poor cache hit ratio |
JP3194201B2 (ja) * | 1992-02-24 | 2001-07-30 | 株式会社日立製作所 | キャッシュモード選択方法 |
JPH07504527A (ja) * | 1992-03-09 | 1995-05-18 | オースペックス システムズ インコーポレイテッド | 高性能の不揮発性ram保護式の書き込みキャッシュアクセラレータシステム |
US5608890A (en) * | 1992-07-02 | 1997-03-04 | International Business Machines Corporation | Data set level cache optimization |
US5694570A (en) * | 1992-09-23 | 1997-12-02 | International Business Machines Corporation | Method and system of buffering data written to direct access storage devices in data processing systems |
DE4323929A1 (de) * | 1992-10-13 | 1994-04-14 | Hewlett Packard Co | Software-geführtes Mehrebenen-Cache-Speichersystem |
US5604882A (en) * | 1993-08-27 | 1997-02-18 | International Business Machines Corporation | System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system |
US5729713A (en) * | 1995-03-27 | 1998-03-17 | Texas Instruments Incorporated | Data processing with first level cache bypassing after a data transfer becomes excessively long |
US6098155A (en) * | 1996-10-28 | 2000-08-01 | Sun Microsystems, Inc. | Apparatus and method for streamlining data transfer with existing interconnect bandwidth |
US5978379A (en) | 1997-01-23 | 1999-11-02 | Gadzoox Networks, Inc. | Fiber channel learning bridge, learning half bridge, and protocol |
US7430171B2 (en) | 1998-11-19 | 2008-09-30 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US6370614B1 (en) | 1999-01-26 | 2002-04-09 | Motive Power, Inc. | I/O cache with user configurable preload |
US6463509B1 (en) * | 1999-01-26 | 2002-10-08 | Motive Power, Inc. | Preloading data in a cache memory according to user-specified preload criteria |
EP1277316A2 (en) * | 2000-04-28 | 2003-01-22 | Broadcom Corporation | Methods and systems for adaptive receiver equalization |
US7222170B2 (en) * | 2002-03-14 | 2007-05-22 | Hewlett-Packard Development Company, L.P. | Tracking hits for network files using transmitted counter instructions |
US7051159B2 (en) * | 2003-06-30 | 2006-05-23 | International Business Machines Corporation | Method and system for cache data fetch operations |
US8140110B2 (en) * | 2005-08-08 | 2012-03-20 | Freescale Semiconductor, Inc. | Controlling input and output in a multi-mode wireless processing system |
US7653675B2 (en) * | 2005-08-08 | 2010-01-26 | Freescale Semiconductor, Inc. | Convolution operation in a multi-mode wireless processing system |
US7802259B2 (en) * | 2005-08-08 | 2010-09-21 | Freescale Semiconductor, Inc. | System and method for wireless broadband context switching |
US7734674B2 (en) * | 2005-08-08 | 2010-06-08 | Freescale Semiconductor, Inc. | Fast fourier transform (FFT) architecture in a multi-mode wireless processing system |
US20070030801A1 (en) * | 2005-08-08 | 2007-02-08 | Freescale Semiconductor, Inc. | Dynamically controlling rate connections to sample buffers in a mult-mode wireless processing system |
US20070033349A1 (en) * | 2005-08-08 | 2007-02-08 | Freescale Semiconductor, Inc. | Multi-mode wireless processor interface |
US7707176B2 (en) * | 2006-12-22 | 2010-04-27 | Sap Ag | Content management system with improved performance |
US8621154B1 (en) | 2008-04-18 | 2013-12-31 | Netapp, Inc. | Flow based reply cache |
US8161236B1 (en) | 2008-04-23 | 2012-04-17 | Netapp, Inc. | Persistent reply cache integrated with file system |
US8171227B1 (en) | 2009-03-11 | 2012-05-01 | Netapp, Inc. | System and method for managing a flow based reply cache |
USRE49818E1 (en) * | 2010-05-13 | 2024-01-30 | Kioxia Corporation | Information processing method in a multi-level hierarchical memory system |
US8972645B2 (en) * | 2012-09-19 | 2015-03-03 | Hewlett-Packard Development Company, L.P. | Request sent to storage device based on moving average |
JP6155723B2 (ja) * | 2013-03-18 | 2017-07-05 | 富士通株式会社 | レーダ装置及びプログラム |
US9779044B2 (en) | 2014-11-25 | 2017-10-03 | Nxp Usa, Inc. | Access extent monitoring for data transfer reduction |
US11941151B2 (en) * | 2021-07-16 | 2024-03-26 | International Business Machines Corporation | Dynamic data masking for immutable datastores |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4075686A (en) * | 1976-12-30 | 1978-02-21 | Honeywell Information Systems Inc. | Input/output cache system including bypass capability |
US4084234A (en) * | 1977-02-17 | 1978-04-11 | Honeywell Information Systems Inc. | Cache write capacity |
GB2052118A (en) * | 1979-06-04 | 1981-01-21 | Memorex Corp | Disc Cache Subsystem |
US4445176A (en) * | 1979-12-28 | 1984-04-24 | International Business Machines Corporation | Block transfers of information in data processing networks |
US4398243A (en) * | 1980-04-25 | 1983-08-09 | Data General Corporation | Data processing system having a unique instruction processor system |
US4394733A (en) * | 1980-11-14 | 1983-07-19 | Sperry Corporation | Cache/disk subsystem |
US4407016A (en) * | 1981-02-18 | 1983-09-27 | Intel Corporation | Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor |
US4445177A (en) * | 1981-05-22 | 1984-04-24 | Data General Corporation | Digital data processing system utilizing a unique arithmetic logic unit for handling uniquely identifiable addresses for operands and instructions |
US4430701A (en) * | 1981-08-03 | 1984-02-07 | International Business Machines Corporation | Method and apparatus for a hierarchical paging storage system |
US4466059A (en) * | 1981-10-15 | 1984-08-14 | International Business Machines Corporation | Method and apparatus for limiting data occupancy in a cache |
US4429363A (en) * | 1981-10-15 | 1984-01-31 | International Business Machines Corporation | Method and apparatus for managing data movements from a backing store to a caching buffer store |
-
1981
- 1981-10-15 US US06/311,570 patent/US4500954A/en not_active Expired - Fee Related
-
1982
- 1982-07-20 JP JP57125203A patent/JPS5876956A/ja active Granted
- 1982-08-25 DE DE8282107802T patent/DE3278651D1/de not_active Expired
- 1982-08-25 EP EP82107802A patent/EP0077451B1/en not_active Expired
- 1982-09-21 CA CA000411849A patent/CA1187199A/en not_active Expired
- 1982-09-24 AU AU88673/82A patent/AU548748B2/en not_active Ceased
- 1982-10-14 ES ES516477A patent/ES8308109A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
CA1187199A (en) | 1985-05-14 |
AU548748B2 (en) | 1986-01-02 |
US4500954A (en) | 1985-02-19 |
JPS5876956A (ja) | 1983-05-10 |
EP0077451B1 (en) | 1988-06-08 |
EP0077451A2 (en) | 1983-04-27 |
ES516477A0 (es) | 1983-07-01 |
DE3278651D1 (en) | 1988-07-14 |
JPS6238731B2 (es) | 1987-08-19 |
AU8867382A (en) | 1983-04-21 |
EP0077451A3 (en) | 1986-03-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19971201 |