ES8202969A1 - Procedimiento de arbitracion centralizada de varias unidadesde tratamiento de un sistema multiprocesador - Google Patents

Procedimiento de arbitracion centralizada de varias unidadesde tratamiento de un sistema multiprocesador

Info

Publication number
ES8202969A1
ES8202969A1 ES501877A ES501877A ES8202969A1 ES 8202969 A1 ES8202969 A1 ES 8202969A1 ES 501877 A ES501877 A ES 501877A ES 501877 A ES501877 A ES 501877A ES 8202969 A1 ES8202969 A1 ES 8202969A1
Authority
ES
Spain
Prior art keywords
centralised
arbiter
arbitration
level
processing units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES501877A
Other languages
English (en)
Other versions
ES501877A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
ALE International SAS
Original Assignee
Thomson CSF Telephone SA
Le Materiel Telephonique Thomson CSF
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF Telephone SA, Le Materiel Telephonique Thomson CSF filed Critical Thomson CSF Telephone SA
Publication of ES8202969A1 publication Critical patent/ES8202969A1/es
Publication of ES501877A0 publication Critical patent/ES501877A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

PROCEDIMIENTO Y DISPOSITIVO DE ARBITRACION CENTRALIZADA DE VARIAS UNIDADES DE TRATAMIENTO DE UN SISTEMA MULTIPROCESADOR. SE DISTRIBUYEN LAS UNIDADES DE TRATAMIENTO (UC) EN VARIOS GRUPOS O NIVELES (&) CADA UNO DE LOS CUALES LLEVA EL MISMO NUMERO (N) DE UNIDADES DE TRATAMIENTO, ATRIBUYENDOSE A CADA UNO DE ESTOS NIVELES UNA SOLA O VARIAS PRIORIDADES, SEGUN UN CICLO PRINCIPAL Y UNA SOLA O VARIAS PRIORIDADES A CADA UNA DE LAS UNIDADES DE TRATAMIENTO EN EL INTERIOR DE CADA NIVEL SEGUN CICLOS SECUNDARIOS. LOS DIFERENTES NIVELES TAMBIEN PODRIAN LLEVAR NUMEROS DIFERENTES DE UNIDADES DE TRATAMIENTO Y ESTAR ESTAS UNIDADES DISTRIBUIDAS EN SUBNIVELES DENTRO DE CADA NIVEL.
ES501877A 1980-05-06 1981-05-05 Procedimiento de arbitracion centralizada de varias unidadesde tratamiento de un sistema multiprocesador Granted ES501877A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8010086A FR2482331B1 (fr) 1980-05-06 1980-05-06 Procede d'arbitration centralisee, et arbitreur centralise pour systeme multiprocesseur

Publications (2)

Publication Number Publication Date
ES8202969A1 true ES8202969A1 (es) 1982-03-01
ES501877A0 ES501877A0 (es) 1982-03-01

Family

ID=9241662

Family Applications (1)

Application Number Title Priority Date Filing Date
ES501877A Granted ES501877A0 (es) 1980-05-06 1981-05-05 Procedimiento de arbitracion centralizada de varias unidadesde tratamiento de un sistema multiprocesador

Country Status (5)

Country Link
US (1) US4493022A (es)
EP (1) EP0039635B1 (es)
DE (1) DE3167153D1 (es)
ES (1) ES501877A0 (es)
FR (1) FR2482331B1 (es)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3170828D1 (en) * 1980-07-08 1985-07-11 Thomson Csf Mat Tel Method and apparatus for arbitrating between a plurality of sub-systems
IT1140233B (it) * 1981-10-20 1986-09-24 Italtel Spa Unita' di controllo dei circuiti di interfaccia di ingresso-uscita di un elaboratore elettronico
EP0121030B1 (fr) * 1983-03-29 1987-11-11 International Business Machines Corporation Dispositif d'arbitrage pour l'attribution d'une ressource commune à une unité sélectionnée d'un système de traitement de données
US4760515A (en) * 1985-10-28 1988-07-26 International Business Machines Corporation Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis
US4760521A (en) * 1985-11-18 1988-07-26 White Consolidated Industries, Inc. Arbitration system using centralized and decentralized arbitrators to access local memories in a multi-processor controlled machine tool
JPS62231338A (ja) * 1986-03-31 1987-10-09 Toshiba Corp 優先順位決定方法および装置
GB2196762B (en) * 1986-10-27 1990-12-19 Burr Brown Ltd Interleaved access to global memory by high priority source
GB2197506A (en) * 1986-10-27 1988-05-18 Burr Brown Ltd Providing and handling break points in a software monitor
US4881195A (en) * 1986-11-26 1989-11-14 Rockwell International Corp. Multi-requester arbitration circuit
US5388228A (en) * 1987-09-30 1995-02-07 International Business Machines Corp. Computer system having dynamically programmable linear/fairness priority arbitration scheme
US4924380A (en) * 1988-06-20 1990-05-08 Modular Computer Systems, Inc. (Florida Corporation) Dual rotating priority arbitration method for a multiprocessor memory bus
JPH0468461A (ja) * 1990-07-10 1992-03-04 Canon Inc 資源管理方式
US5247675A (en) * 1991-08-09 1993-09-21 International Business Machines Corporation Preemptive and non-preemptive scheduling and execution of program threads in a multitasking operating system
EP0770961A3 (en) * 1995-10-24 2001-04-11 Konica Corporation Memory access system
US5954809A (en) * 1996-07-19 1999-09-21 Compaq Computer Corporation Circuit for handling distributed arbitration in a computer system having multiple arbiters
KR20200036461A (ko) * 2018-09-28 2020-04-07 삼성전자주식회사 메모리 디바이스들 사이의 직접 통신을 위한 메모리 시스템 및 메모리 디바이스

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3353160A (en) * 1965-06-09 1967-11-14 Ibm Tree priority circuit
BE754135A (fr) * 1969-10-17 1970-12-31 Burroughs Corp Circuit selecteur a grande vitesse
US3905023A (en) * 1973-08-15 1975-09-09 Burroughs Corp Large scale multi-level information processing system employing improved failsaft techniques
US4334288A (en) * 1979-06-18 1982-06-08 Booher Robert K Priority determining network having user arbitration circuits coupled to a multi-line bus
US4320457A (en) * 1980-02-04 1982-03-16 General Automation, Inc. Communication bus acquisition circuit
US4363096A (en) * 1980-06-26 1982-12-07 Gte Automatic Electric Labs Inc. Arbitration controller providing for access of a common resource by a duplex plurality of central processing units
US4395753A (en) * 1980-06-26 1983-07-26 Gte Automatic Electric Labs Inc. Allocation controller providing for access of multiple common resources by a plurality of central processing units
US4412281A (en) * 1980-07-11 1983-10-25 Raytheon Company Distributed signal processing system

Also Published As

Publication number Publication date
FR2482331A1 (fr) 1981-11-13
ES501877A0 (es) 1982-03-01
EP0039635B1 (fr) 1984-11-14
EP0039635A1 (fr) 1981-11-11
US4493022A (en) 1985-01-08
DE3167153D1 (en) 1984-12-20
FR2482331B1 (fr) 1986-03-21

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001