ES8201330A1 - Un sistema computador redundante - Google Patents
Un sistema computador redundanteInfo
- Publication number
- ES8201330A1 ES8201330A1 ES500296A ES500296A ES8201330A1 ES 8201330 A1 ES8201330 A1 ES 8201330A1 ES 500296 A ES500296 A ES 500296A ES 500296 A ES500296 A ES 500296A ES 8201330 A1 ES8201330 A1 ES 8201330A1
- Authority
- ES
- Spain
- Prior art keywords
- data
- computers
- computer system
- shift registers
- translation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/187—Voting techniques
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/83—Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
SISTEMA COMPUTADOR REDUNDANTE QUE COMPRENDE AL MENOS DOS COMUTADORAS CON DISPOSITIVOS DE ENTRADA Y SALIDA Y VARRATAMIENTO DE DATOS. UNA LINEAS DE CABLES (32,34)IAS MEMORIAS, EN EL CUAL LOS COMPUTADORES PROCESAN LOS DATOS EN PARALELO, YA SEA SINCRONICAMENTE O CON UNA TRASLACION DE TIEMPO, SIENDO COMPROBADOS LOS RESULTADOR POR COMPARACION. CONSTA DE DOS COMPUTADORAS (R1,R2), DE DOS REGISTROS DE ENTRADA DE DATOS (E1,E2), DE DOS REGISTROS DE SALISA (A1,A2), DE UN DISPOSITIVO DE SELECCION Y CONMUTACION Y REALIMENTACION (SR1,SR2), CADA UNO DE LO CUALES ESTA ASOCIADO CON UNO DE LOS COMPUTADORES EN PARALELO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19803009355 DE3009355C2 (de) | 1980-03-12 | 1980-03-12 | Redundante Rechenanlage |
Publications (2)
Publication Number | Publication Date |
---|---|
ES8201330A1 true ES8201330A1 (es) | 1981-12-16 |
ES500296A0 ES500296A0 (es) | 1981-12-16 |
Family
ID=6096896
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES500296A Granted ES500296A0 (es) | 1980-03-12 | 1981-03-12 | Un sistema computador redundante |
Country Status (5)
Country | Link |
---|---|
BE (1) | BE887906A (es) |
CH (1) | CH652838A5 (es) |
DE (1) | DE3009355C2 (es) |
ES (1) | ES500296A0 (es) |
YU (1) | YU41455B (es) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3324313A1 (de) * | 1983-07-06 | 1985-01-17 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Einrichtung zur signaltechnisch sicheren darstellung von information auf einem datensichtgeraet |
BG48904A1 (en) * | 1985-04-30 | 1991-06-14 | Werk Signal Sicherungstech Veb | Device for connecting of computers |
DE102009054637A1 (de) * | 2009-12-15 | 2011-06-16 | Robert Bosch Gmbh | Verfahren zum Betreiben einer Recheneinheit |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RO63302A (fr) * | 1971-02-23 | 1978-08-15 | Int Standard Electric Corp | Dispositif pour le control continu le fonctionnement tu traitement des informations et l'emission des telegrammes des donnees,aux instalations de chemin de fer commandes pal un ordinateur de proces |
DE2303828A1 (de) * | 1973-01-26 | 1974-08-01 | Standard Elektrik Lorenz Ag | Steuerverfahren mit drei parallel betriebenen rechnern |
-
1980
- 1980-03-12 DE DE19803009355 patent/DE3009355C2/de not_active Expired
-
1981
- 1981-03-06 CH CH151181A patent/CH652838A5/de not_active IP Right Cessation
- 1981-03-12 BE BE2/59049A patent/BE887906A/fr not_active IP Right Cessation
- 1981-03-12 ES ES500296A patent/ES500296A0/es active Granted
- 1981-03-12 YU YU64281A patent/YU41455B/xx unknown
Also Published As
Publication number | Publication date |
---|---|
BE887906A (fr) | 1981-09-14 |
DE3009355A1 (de) | 1981-09-17 |
DE3009355C2 (de) | 1984-08-30 |
YU41455B (en) | 1987-06-30 |
CH652838A5 (en) | 1985-11-29 |
ES500296A0 (es) | 1981-12-16 |
YU64281A (en) | 1983-06-30 |
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