ES497457A0 - 2 mejoras en los sistemas de control para tratamiento de da-tos, para una memoria amortiguadora del sistema de permuta - Google Patents

2 mejoras en los sistemas de control para tratamiento de da-tos, para una memoria amortiguadora del sistema de permuta

Info

Publication number
ES497457A0
ES497457A0 ES497457A ES497457A ES497457A0 ES 497457 A0 ES497457 A0 ES 497457A0 ES 497457 A ES497457 A ES 497457A ES 497457 A ES497457 A ES 497457A ES 497457 A0 ES497457 A0 ES 497457A0
Authority
ES
Spain
Prior art keywords
tos
treatment
control systems
permit system
damping memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES497457A
Other languages
English (en)
Other versions
ES8201343A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8201343A1 publication Critical patent/ES8201343A1/es
Publication of ES497457A0 publication Critical patent/ES497457A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
ES497457A 1979-12-06 1980-12-04 2 mejoras en los sistemas de control para tratamiento de da-tos, para una memoria amortiguadora del sistema de permuta Granted ES497457A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15841779A JPS5680872A (en) 1979-12-06 1979-12-06 Buffer memory control system

Publications (2)

Publication Number Publication Date
ES8201343A1 ES8201343A1 (es) 1981-12-16
ES497457A0 true ES497457A0 (es) 1981-12-16

Family

ID=15671290

Family Applications (1)

Application Number Title Priority Date Filing Date
ES497457A Granted ES497457A0 (es) 1979-12-06 1980-12-04 2 mejoras en los sistemas de control para tratamiento de da-tos, para una memoria amortiguadora del sistema de permuta

Country Status (8)

Country Link
US (1) US4395763A (es)
EP (1) EP0030463B1 (es)
JP (1) JPS5680872A (es)
AU (1) AU535788B2 (es)
BR (1) BR8007988A (es)
CA (1) CA1149965A (es)
DE (1) DE3071782D1 (es)
ES (1) ES497457A0 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4533995A (en) * 1981-08-03 1985-08-06 International Business Machines Corporation Method and system for handling sequential data in a hierarchical store
US4504902A (en) * 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
JPS5958681A (ja) * 1982-09-28 1984-04-04 Fujitsu Ltd ペ−ジイン制御方式
US4627000A (en) * 1984-04-12 1986-12-02 General Electric Company Apparatus and method for copying data from one electronic demand register to another
US4942518A (en) * 1984-06-20 1990-07-17 Convex Computer Corporation Cache store bypass for computer
US4646233A (en) * 1984-06-20 1987-02-24 Weatherford James R Physical cache unit for computer
JPH0616272B2 (ja) * 1984-06-27 1994-03-02 株式会社日立製作所 メモリアクセス制御方式
JPS61112260A (ja) * 1984-11-07 1986-05-30 Hitachi Ltd 多重階層記憶システムにおけるスワツプ制御装置
JP3024422B2 (ja) * 1993-04-01 2000-03-21 三菱電機株式会社 プログラマブルコントローラおよびプログラマブルコントローラの運転方法
KR100247467B1 (ko) * 1997-11-07 2000-03-15 윤종용 엠엠씨 커맨드를 이용한 교체 블록 로딩 방법
US10891227B2 (en) * 2018-11-29 2021-01-12 International Business Machines Corporation Determining modified tracks to destage during a cache scan

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1196752A (en) * 1967-05-04 1970-07-01 Int Computers Ltd Improvements relating to Data Handling Arrangements.
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3735360A (en) * 1971-08-25 1973-05-22 Ibm High speed buffer operation in a multi-processing system
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
FR129151A (es) * 1974-02-09
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
US4161024A (en) * 1977-12-22 1979-07-10 Honeywell Information Systems Inc. Private cache-to-CPU interface in a bus oriented data processing system

Also Published As

Publication number Publication date
BR8007988A (pt) 1981-06-23
AU6479980A (en) 1981-06-11
JPS6330655B2 (es) 1988-06-20
ES8201343A1 (es) 1981-12-16
DE3071782D1 (en) 1986-10-30
EP0030463B1 (en) 1986-09-24
AU535788B2 (en) 1984-04-05
EP0030463A3 (en) 1983-03-16
JPS5680872A (en) 1981-07-02
US4395763A (en) 1983-07-26
CA1149965A (en) 1983-07-12
EP0030463A2 (en) 1981-06-17

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001