ES459932A1 - Perfeccionamientos introducidos en sistemas de memoria vir- tual. - Google Patents

Perfeccionamientos introducidos en sistemas de memoria vir- tual.

Info

Publication number
ES459932A1
ES459932A1 ES459932A ES459932A ES459932A1 ES 459932 A1 ES459932 A1 ES 459932A1 ES 459932 A ES459932 A ES 459932A ES 459932 A ES459932 A ES 459932A ES 459932 A1 ES459932 A1 ES 459932A1
Authority
ES
Spain
Prior art keywords
dlat
translation
counter
stored
virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES459932A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES459932A1 publication Critical patent/ES459932A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29L—INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
    • B29L2030/00—Pneumatic or solid tyres or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Perfeccionamientos introducidos en sistemas de memoria virtual en una instalación de tratamiento de datos, que comprende por lo menos un dispositivo de tratamiento de datos central, una memoria principal y dispositivos de memoria periféricos así como un dispositivo de control de memoria para la manipulación o administración de memorias, con el fin de realizar directamente el acceso a lugares de memoria en un bastidor de memoria de la memoria principal, caso de que esté disponible la conversión de la dirección virtual solicitada en una dirección real correspondiente en la memoria principal.
ES459932A 1976-06-21 1977-06-20 Perfeccionamientos introducidos en sistemas de memoria vir- tual. Expired ES459932A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/697,817 US4053948A (en) 1976-06-21 1976-06-21 Look aside array invalidation mechanism

Publications (1)

Publication Number Publication Date
ES459932A1 true ES459932A1 (es) 1978-04-01

Family

ID=24802683

Family Applications (1)

Application Number Title Priority Date Filing Date
ES459932A Expired ES459932A1 (es) 1976-06-21 1977-06-20 Perfeccionamientos introducidos en sistemas de memoria vir- tual.

Country Status (12)

Country Link
US (1) US4053948A (es)
JP (1) JPS52156518A (es)
AU (1) AU511393B2 (es)
BR (1) BR7704024A (es)
CA (1) CA1075824A (es)
CH (1) CH617781A5 (es)
DE (1) DE2726488C2 (es)
ES (1) ES459932A1 (es)
FR (1) FR2391509A1 (es)
GB (1) GB1520239A (es)
IT (1) IT1113580B (es)
SE (1) SE421152B (es)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4241401A (en) * 1977-12-19 1980-12-23 Sperry Corporation Virtual address translator utilizing interrupt level code
US4453230A (en) * 1977-12-29 1984-06-05 Tokyo Shibaura Electric Co., Ltd. Address conversion system
JPS54111726A (en) * 1978-02-22 1979-09-01 Hitachi Ltd Control unit for multiplex virtual memory
US4376297A (en) * 1978-04-10 1983-03-08 Signetics Corporation Virtual memory addressing device
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
US4215402A (en) * 1978-10-23 1980-07-29 International Business Machines Corporation Hash index table hash generator apparatus
US4277826A (en) * 1978-10-23 1981-07-07 Collins Robert W Synchronizing mechanism for page replacement control
EP0019358B1 (en) * 1979-05-09 1984-07-11 International Computers Limited Hierarchical data storage system
GB2052117B (en) * 1979-07-04 1982-10-20 Int Computers Ltd Data processing systems
JPS5644180A (en) * 1979-09-17 1981-04-23 Nec Corp Information retrieval device
US4403283A (en) * 1980-07-28 1983-09-06 Ncr Corporation Extended memory system and method
JPS58185856U (ja) * 1982-06-04 1983-12-10 株式会社東芝 複写装置
GB2127189B (en) * 1982-09-18 1986-11-05 Int Computers Ltd Automatic invalidation of validity tags in data store
US4714990A (en) * 1982-09-18 1987-12-22 International Computers Limited Data storage apparatus
JPH0658646B2 (ja) * 1982-12-30 1994-08-03 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション デ−タ持続性が制御される仮想記憶アドレス変換機構
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
JPS60142451A (ja) * 1983-12-29 1985-07-27 Fujitsu Ltd アドレス変換制御方式
DE3572233D1 (en) * 1984-09-28 1989-09-14 Siemens Ag Circuit arrangement for clearing storage entries in an address translation memory
US4821171A (en) * 1985-05-07 1989-04-11 Prime Computer, Inc. System of selective purging of address translation in computer memories
US4777589A (en) * 1985-06-28 1988-10-11 Hewlett-Packard Company Direct input/output in a virtual memory system
US4757447A (en) * 1986-07-28 1988-07-12 Amdahl Corporation Virtual memory system having identity marking for common address space
JP2510605B2 (ja) * 1987-07-24 1996-06-26 株式会社日立製作所 仮想計算機システム
JPH01303527A (ja) * 1988-05-31 1989-12-07 Hitachi Ltd 共有資源の管理方法
GB8814077D0 (en) * 1988-06-14 1988-07-20 Int Computers Ltd Data memory system
US5175543A (en) * 1991-09-25 1992-12-29 Hewlett-Packard Company Dictionary reset performance enhancement for data compression applications
JP3074897B2 (ja) * 1992-01-23 2000-08-07 日本電気株式会社 メモリ回路
DE19516949A1 (de) * 1994-05-11 1996-02-15 Gmd Gmbh Speichervorrichtung zum Speichern von Daten
US6510508B1 (en) * 2000-06-15 2003-01-21 Advanced Micro Devices, Inc. Translation lookaside buffer flush filter
US6938145B2 (en) * 2002-12-04 2005-08-30 Bull Hn Information Systems Inc. Associative memory system with a multi-digit incrementable validity counter
US6915405B2 (en) * 2002-12-04 2005-07-05 Bull Hn Information Systems Inc. Emulated target associative memory system with a multi-digit incrementable validity counter
US7069389B2 (en) 2003-11-26 2006-06-27 Microsoft Corporation Lazy flushing of translation lookaside buffers
US7788464B2 (en) 2006-12-22 2010-08-31 Microsoft Corporation Scalability of virtual TLBs for multi-processor virtual machines
US8112174B2 (en) * 2008-02-25 2012-02-07 International Business Machines Corporation Processor, method and computer program product for fast selective invalidation of translation lookaside buffer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
US3839706A (en) * 1973-07-02 1974-10-01 Ibm Input/output channel relocation storage protect mechanism
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
JPS5642072B2 (es) * 1975-02-21 1981-10-02

Also Published As

Publication number Publication date
DE2726488A1 (de) 1977-12-29
AU511393B2 (en) 1980-08-14
CA1075824A (en) 1980-04-15
SE7706913L (sv) 1977-12-22
IT1113580B (it) 1986-01-20
DE2726488C2 (de) 1984-05-17
SE421152B (sv) 1981-11-30
JPS52156518A (en) 1977-12-27
CH617781A5 (es) 1980-06-13
FR2391509B1 (es) 1980-01-04
GB1520239A (en) 1978-08-02
BR7704024A (pt) 1978-04-04
FR2391509A1 (fr) 1978-12-15
US4053948A (en) 1977-10-11
AU2630777A (en) 1979-01-04
JPS5733622B2 (es) 1982-07-17

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