ES446087A1 - Device for transferring numerical information asynchronously in series - Google Patents

Device for transferring numerical information asynchronously in series

Info

Publication number
ES446087A1
ES446087A1 ES446087A ES446087A ES446087A1 ES 446087 A1 ES446087 A1 ES 446087A1 ES 446087 A ES446087 A ES 446087A ES 446087 A ES446087 A ES 446087A ES 446087 A1 ES446087 A1 ES 446087A1
Authority
ES
Spain
Prior art keywords
clock
series
parallel
numerical information
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES446087A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeumont Schneider SA
Original Assignee
Jeumont Schneider SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeumont Schneider SA filed Critical Jeumont Schneider SA
Publication of ES446087A1 publication Critical patent/ES446087A1/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045Correction by a latch cascade

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Numerical Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)

Abstract

A device for transferring numerical information in series in an asynchronous manner, used as an intermediate arrangement between the arrival of a way of transmitting information and a receiver having a clock not synchronized with that of the transmitter, characterized in that it contains; a clock regenerator-recuperator at the arrival of the transmission path; a group of three serial registers for sequentially storing the numerical information leaving the regenerator, the first record being a displacement register of the series-parallel type sent by the clock retriever, the second being a buffer register of the parallel-parallel type, and the third being a displacement register of the parallel-series type whose reading is sent by the receiver's clock; and a logic circuit, in series with a schmitt scale, to command the transfer of information from the second register to the third according to the respective time bases of the clock recuperator and receiver clock. (Machine-translation by Google Translate, not legally binding)
ES446087A 1975-03-20 1976-03-16 Device for transferring numerical information asynchronously in series Expired ES446087A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7508697A FR2305073A1 (en) 1975-03-20 1975-03-20 Series and asynchronous mode - counteracts data loss or erroneous data transfer to receiver

Publications (1)

Publication Number Publication Date
ES446087A1 true ES446087A1 (en) 1977-06-01

Family

ID=9152822

Family Applications (1)

Application Number Title Priority Date Filing Date
ES446087A Expired ES446087A1 (en) 1975-03-20 1976-03-16 Device for transferring numerical information asynchronously in series

Country Status (14)

Country Link
JP (1) JPS51117506A (en)
AU (1) AU1217376A (en)
BE (1) BE839686A (en)
BR (1) BR7601608A (en)
DD (1) DD123633A5 (en)
DE (1) DE2611473A1 (en)
ES (1) ES446087A1 (en)
FR (1) FR2305073A1 (en)
IT (1) IT1057451B (en)
LU (1) LU74589A1 (en)
NL (1) NL7602762A (en)
OA (1) OA05274A (en)
SE (1) SE7602742L (en)
ZA (1) ZA761687B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2538976A1 (en) * 1982-12-29 1984-07-06 Servel Michel SYSTEM FOR SWITCHING SYNCHRONOUS PACKETS OF FIXED LENGTH
GB8430167D0 (en) * 1984-11-29 1985-01-09 Emi Ltd Data communications network
EP0379279A3 (en) * 1989-01-17 1991-09-11 Marconi Instruments Limited Data transmission synchroniser

Also Published As

Publication number Publication date
DD123633A5 (en) 1977-01-05
IT1057451B (en) 1982-03-10
JPS51117506A (en) 1976-10-15
OA05274A (en) 1981-02-28
DE2611473A1 (en) 1976-09-30
BE839686A (en) 1976-07-16
BR7601608A (en) 1976-09-21
ZA761687B (en) 1977-05-25
SE7602742L (en) 1976-09-21
NL7602762A (en) 1976-09-22
FR2305073A1 (en) 1976-10-15
LU74589A1 (en) 1976-09-01
AU1217376A (en) 1977-09-22

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