ES424364A1 - System for testing a data-processing unit - Google Patents
System for testing a data-processing unitInfo
- Publication number
- ES424364A1 ES424364A1 ES424364A ES424364A ES424364A1 ES 424364 A1 ES424364 A1 ES 424364A1 ES 424364 A ES424364 A ES 424364A ES 424364 A ES424364 A ES 424364A ES 424364 A1 ES424364 A1 ES 424364A1
- Authority
- ES
- Spain
- Prior art keywords
- unit
- elements
- test
- data processing
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 abstract 2
- 210000000056 organ Anatomy 0.000 abstract 1
- 208000024891 symptom Diseases 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
- Debugging And Monitoring (AREA)
Abstract
Test system of a data processing unit, P1 connectable with at least one other data processing unit P2 and with optional OG organs and composed of functional elements comprising memory elements M1 and M2 respectively consisting of initializable and non-initializable bistable elements simultaneously, a permanent memory R0 in which the operating microprograms are registered, a circuit I for initialization of the elements M1 before the data processing in the unit P1, sent manually and connected to the inputs of the memory R0, characterized in that It is integrated in unit P1 by test microprograms registered in a zone Z of memory R0, by circuit I, and by test circuits T, contained in unit P1, connected to an input and output of initialization circuit I and with the outputs of the R0 memory, the test microprograms being granted to test all the functional elements of the P1 unit from an initial reference state and to collect, by the detection of functional errors of these elements, all the symptoms S associated with each of all the foreseeable faults in the P1 unit, comprising the test circuits T means b1 to put all the bistable elements of the M2 elements in an initial reference state and detectors E1 and E2 connected by their inputs with the functional elements of the unit P1 to detect in it all the errors produced respectively in the course of the test and in the course of data processing, so that, circuit I being sent manually before data processing and automatically in case of error detection in the course of data processing, said test system allows the Direct location of a fault among all the foreseeable faults in the P1 unit. (Machine-translation by Google Translate, not legally binding)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7309558A FR2221740B1 (en) | 1973-03-16 | 1973-03-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES424364A1 true ES424364A1 (en) | 1976-09-01 |
Family
ID=9116427
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES424364A Expired ES424364A1 (en) | 1973-03-16 | 1974-03-16 | System for testing a data-processing unit |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS49128653A (en) |
DE (1) | DE2412179A1 (en) |
ES (1) | ES424364A1 (en) |
FR (1) | FR2221740B1 (en) |
GB (1) | GB1455078A (en) |
IT (1) | IT1007713B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2549256B1 (en) * | 1983-06-22 | 1985-11-29 | Philips Ind Commerciale | AUTOMATIC METHOD AND MACHINE FOR SIMULTANEOUSLY TESTING COMPUTER SYSTEMS |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1338303A (en) * | 1959-12-31 | 1963-09-27 | Ibm | Saved program calculators |
US3405258A (en) * | 1965-04-07 | 1968-10-08 | Ibm | Reliability test for computer check circuits |
-
1973
- 1973-03-16 FR FR7309558A patent/FR2221740B1/fr not_active Expired
-
1974
- 1974-03-14 DE DE19742412179 patent/DE2412179A1/en not_active Withdrawn
- 1974-03-15 GB GB1175674A patent/GB1455078A/en not_active Expired
- 1974-03-15 JP JP49029290A patent/JPS49128653A/ja active Pending
- 1974-03-16 ES ES424364A patent/ES424364A1/en not_active Expired
- 1974-04-08 IT IT2069674A patent/IT1007713B/en active
Also Published As
Publication number | Publication date |
---|---|
FR2221740B1 (en) | 1976-06-11 |
DE2412179A1 (en) | 1974-09-19 |
IT1007713B (en) | 1976-10-30 |
FR2221740A1 (en) | 1974-10-11 |
JPS49128653A (en) | 1974-12-10 |
GB1455078A (en) | 1976-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE72066T1 (en) | SELF-TESTING COMPUTING CIRCUIT ARRANGEMENT. | |
GB1253648A (en) | Improvements in or relating to computing systems | |
GB1137778A (en) | Data processing apparatus | |
DE69126498D1 (en) | Recovery method and device for a pipeline processing unit of a multiprocessor system | |
GB1131085A (en) | Improvements in or relating to the testing and repair of electronic digital computers | |
GB1308497A (en) | Data processing arrangements | |
FR2232255A5 (en) | ||
ES321587A1 (en) | Verification provision to find troubles or failures in a data processing system, equipped with memory. (Machine-translation by Google Translate, not legally binding) | |
GB1070421A (en) | Improvements in or relating to computer error checking circuitry | |
GB1104967A (en) | Signal translating arrangements | |
ES424364A1 (en) | System for testing a data-processing unit | |
GB1247746A (en) | Data processing machines | |
US3814920A (en) | Employing variable clock rate | |
US3573445A (en) | Device for programmed check of digital computers | |
US3459927A (en) | Apparatus for checking logical connective circuits | |
US3779458A (en) | Self-checking decision logic circuit | |
GB1334262A (en) | Data processing system | |
JPS57167200A (en) | Memory backup circuit | |
SU798853A1 (en) | Processor with reconfiguration | |
JPS5515510A (en) | Check system of information processing system | |
GB1336296A (en) | Integrated circuit arrangments | |
JPS5764399A (en) | Data processing device | |
ES349578A1 (en) | Data processing system. (Machine-translation by Google Translate, not legally binding) | |
JPS57132245A (en) | Testing system for arithmetic circuit | |
SU712960A1 (en) | Decorder monitoring device |