ES409420A1 - Un sistema para proceso de datos. - Google Patents

Un sistema para proceso de datos.

Info

Publication number
ES409420A1
ES409420A1 ES409420A ES409420A ES409420A1 ES 409420 A1 ES409420 A1 ES 409420A1 ES 409420 A ES409420 A ES 409420A ES 409420 A ES409420 A ES 409420A ES 409420 A1 ES409420 A1 ES 409420A1
Authority
ES
Spain
Prior art keywords
word
bit
contents
instruction
index register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES409420A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES409420A1 publication Critical patent/ES409420A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54533—Configuration data, translation, passwords, databases

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Executing Machine-Instructions (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Complex Calculations (AREA)

Abstract

Un sistema para proceso de datos con un procesador y una memoria para almacenar diversas palabras de datos constituidas por bites. Dicho procesador incluye un registrador de índice para almacenar el encaminamiento relativo de una palabra de datos en una tabla de dicha memoria. También incluye medios para tener acceso a esta palabra desde dicha tabla empleando dicho encaminamiento relativo y medios para determinar la posición del primer bit de dicha palabra que está predeterminada por dos condiciones. Todos estos bites de la palabra están ordenados de un modo predeterminado. Dicho procesador incluye medios (AU,CU) para combinar el encaminamiento relativo y la posición del primer bit en la palabra para obtener la posición de dicho primer bit en la tabla de memoria (IJT)
ES409420A 1971-12-10 1972-12-07 Un sistema para proceso de datos. Expired ES409420A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BE776495A BE776495A (nl) 1971-12-10 1971-12-10 Gegevensverwerkend stelsel, (uitv.: s. kobus, j. janssens en w.zoile).

Publications (1)

Publication Number Publication Date
ES409420A1 true ES409420A1 (es) 1975-12-16

Family

ID=3858992

Family Applications (1)

Application Number Title Priority Date Filing Date
ES409420A Expired ES409420A1 (es) 1971-12-10 1972-12-07 Un sistema para proceso de datos.

Country Status (13)

Country Link
US (1) US3930235A (es)
AR (1) AR200005A1 (es)
AU (1) AU474228B2 (es)
BE (1) BE776495A (es)
BR (1) BR7208637D0 (es)
DE (1) DE2259994A1 (es)
ES (1) ES409420A1 (es)
FR (1) FR2164378A5 (es)
GB (1) GB1367709A (es)
IT (1) IT971530B (es)
NL (1) NL7216745A (es)
YU (1) YU34946B (es)
ZA (1) ZA727887B (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6030973B2 (ja) * 1980-01-18 1985-07-19 日本電気株式会社 高速パタ−ン発生器
US5193159A (en) * 1986-09-24 1993-03-09 Hitachi, Ltd. Microprocessor system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3394350A (en) * 1965-01-14 1968-07-23 Burroughs Corp Digital processor implementation of transfer and translate operation
US3504349A (en) * 1967-09-27 1970-03-31 Ibm Address examination mechanism for use in a system operating with dynamic storage relocation

Also Published As

Publication number Publication date
IT971530B (it) 1974-05-10
FR2164378A5 (es) 1973-07-27
AU474228B2 (en) 1976-07-15
BR7208637D0 (pt) 1973-08-30
BE776495A (nl) 1972-06-12
ZA727887B (en) 1973-07-25
AR200005A1 (es) 1974-10-15
NL7216745A (es) 1973-06-13
DE2259994A1 (de) 1973-07-19
US3930235A (en) 1975-12-30
GB1367709A (en) 1974-09-18
YU302472A (en) 1979-10-31
YU34946B (en) 1980-04-30
AU4959272A (en) 1974-06-06

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19870207