ES336127A1 - Parity checking system - Google Patents

Abstract

In a parity checking system, predetermined test data is applied to a device to provide, if the device is operating correctly, output data of predetermined parity which is then combined with a fixed value parity bit and parity checked. In a computer (Fig. 1, not shown), a word (including parity bit) is odd parity checked (8) when read from a store (1), before use (without the parity bit) in an ALU, i.e. arithmetic and logic unit (3). The ALU output is reinserted into the store (1) together with a parity bit generated (7) for it, after a further parity check. To test the ALU etc., a diagnostic routine is initiated in which two test words are read from the store (1) and processed in the ALU, the words being chosen so that in the absence of error, the result has even parity. A pseudoparity bit, which is always " one ", is combined with it and a parity check (8) carried out. The computer can be parallel or serial. In a data transmission system (Fig. 2, not shown), a predetermined number of multi-bit parallel message words are transmitted in turn serially by bit, each word being staticized and provided (19) with a parity bit at the receiver. When the predetermined number of words have been received, a counter reverses a (relay or transistor) switch (20) to combine a pseudoparity bit, which is always " one ", with a predetermined word of even parity transmitted after the message words. A parity check is then carried out on this last (combined) word and if it does not have odd parity, an error has occurred. In this case, the transmitter is caused to send the predetermined word again and if this time the parity is correct, the message words are retransmitted. The system could alternatively be serial throughout.