ES2958838A1 - FLYBACK CONTROLLER AND BATTERY CHARGING SYSTEM - Google Patents

Abstract

Flyback controller (10) and battery charging system (8). The flyback controller (10), configured to regulate a flyback power supply (1) with transformer (T1) and transistor (Q1), comprises a first (13) and second (14) central processing unit; a memory (15); current sampling blocks (17a) in the primary of the transformer (T1); an input voltage sampling block (18) on the primary of the transformer (T1); an output voltage sampling block (19) on the secondary side of the transformer (T1); a temperature sampling block (20) of the transformer (T1); a pulse width modulation block (21); a transformer voltage control block (22) to prevent saturation of the transformer primary (T1) or the transistor (Q1); and a communication unit (23) responsible for communicating the first central processing unit (13) with an external master processing unit (50) to receive control commands.

Description

DESCRIPTION

FLYBACK CONTROLLER AND BATTERY CHARGING SYSTEM

field of invention

The present invention falls within the field of semiconductors and hardware architecture for flyback controllers with applications in battery charging systems, capacitors or supercapacitors and in cell or battery balancing systems, among other applications.

Background of the invention

Currently, there are numerous analog controllers to regulate the output voltage and/or current. These controllers operate at different input and output voltage ranges, and are governed by one or no central processing unit (CPU).

The products that currently exist on the market can be classified into two groups based on their hardware architecture:

- Analog architecture: This architecture is characterized by the use of simple components with minimal programming capacity. These types of designs seek to minimize the software design and base their configuration on the use of resistors and the control of leakage currents.

- Digital architecture: This type of architecture is characterized by the use mainly of microcontrollers. The design of this type of architecture requires the division of the design between software and hardware. This division makes the creation phase of a final product more expensive in terms of time and complexity since all the functional pieces have to be joined together in the final production phase.

However, current controllers have a technological limitation in terms of their adaptability to applications such as peak voltage programming radio frequency systems, high power defibrillator systems and circuits, battery charging and balancing systems, and solar charging systems for isolated applications.

Although the flyback topology is widely used, its application in charging systems requires important design variations, since the charging phase could extend for hours. Due to this, factors such as switching frequency, temperature, current or the integral state of the system must be monitored very precisely. These functional characteristics create the need to design a specific architecture for a flyback controller that allows optimizing the final product, which is the objective of the present invention.

The proposal of the present invention establishes the union of an analog architecture and a digital architecture with high optimization, selecting the minimum elements necessary to maximize resources, design space, performance and costs.

Description of the invention

The present invention refers to a specific and adaptable mixed architecture for flyback controllers, and a battery charging system that uses said flyback controllers. The hardware architecture of the flyback controllers is made up of analog and digital blocks for a flyback topology specialized in high voltage charging system such as batteries, capacitors or supercapacitors, with bidirectional possibility, whose configuration is described below.

The proposed invention uses groups of blocks and components necessary for the creation of a flyback controller specialized in charging systems with a programmable range and designed for integration into a single integrated circuit (SOC technology, System on Chip).

A first aspect of the present invention relates to a flyback controller for regulating a flyback power supply that includes a transformer and a transistor regulated by the flyback controller. The flyback controller comprises the following blocks or elements:

- A first central processing unit and a second central processing unit, responsible for controlling the operation of the flyback controller (10) in real time.

- A memory, responsible for storing data in real time and the execution program of the central processing units.

- A first current sampling block, responsible for measuring the current in the primary of the transformer for processing by the second central processing unit.

- An input voltage sampling block, responsible for reading and adapting the input voltage in the primary of the transformer for processing by the second central processing unit.

- An output voltage sampling block, responsible for reading and adapting the output voltage on the secondary side of the transformer for processing by the second central processing unit.

- A temperature sampling block, responsible for reading and adapting the temperature of the transformer for processing by the second central processing unit.

- A pulse width modulation block, responsible for the synchronization and control of pulse width modulators from a target voltage.

- A transformer voltage control block, responsible for controlling the voltage on the primary of the transformer to avoid saturation of the primary of the transformer or the transistor.

- A communication unit, responsible for communicating the first central processing unit with an external master processing unit to receive control commands.

According to a first application, the flyback controller is used to control the tension of a piezoelectric actuator.

In another application, the flyback controller is used to manage the charging of a battery, preferably by connecting it in parallel with at least one or more additional flyback controllers. In this case the flyback controller preferably comprises a synchronization unit responsible for synchronization, in phase or out of phase, with the additional flyback controllers through the use of a synchronization signal. The flyback controller may comprise a second current sampling block, responsible for monitoring the load current in the secondary of the transformer, based on measurements from a Hall effect sensor, for processing by the second central processing unit. The second central processing unit is preferably configured to control the current in the primary and/or secondary of the transformer by activating interruptions when a programmed current limit is exceeded.

A second aspect of the present invention relates to a battery charging system comprising a plurality of flyback controllers described above. In one embodiment, the battery charging system comprises:

- A plurality of flyback power supplies connected in parallel feeding a battery, where each flyback power source comprises a flyback controller, and where each flyback controller comprises a synchronization unit responsible for synchronization, in phase or out of phase, between the flyback controllers by using a synchronization signal.

- A master processing unit in charge of controlling the battery charge by sending control commands to the communication unit of the flyback controllers.

In another embodiment, the battery charging system comprises:

- A first and a second flyback controller that comprise a synchronization unit responsible for synchronizing between the flyback controllers through the use of synchronization signals. The first flyback controller is connected to the primary of the transformer and has an input voltage sampling block for reading the input voltage at the primary of the transformer. The second flyback controller is connected to the secondary of the transformer and includes an output voltage sampling block for reading the output voltage on the secondary of the transformer.

- Some master processing units connected to the respective communication units of the flyback controllers, where the master processing units are in charge of controlling the battery charge by sending control commands to the flyback controllers.

The flyback controller of the present invention provides, among others, the following advantages:

• Possibility of programming and configuration in the production phase.

• Application ranges of 12 - 1000 Volts.

• Possibility of calibration to solve process variations in the case of a semiconductor.

• Current ranges from 1 -50 amps.

• Switching range from 500khz to 100Hz.

• Control of states T1, T2 and T3 in discontinuous conduction mode (DCM).

• Control of transients coming from the power supply (V<in>).

• Good response in transient regime.

• Control and monitoring against saturation of the flyback transformer.

• Real-time programming and monitoring capacity on:

<o>Input voltage.

<o>Output voltage.

<o>Current ranges.

<o>Temperature ranges.

<o>Hardware variation: transformer, sampling resistors or regulator precision.

• Control against overcurrents:

<o>In the primary of the transformer, determined by the control mode.

<o>In the secondary of the transformer, during the discharge phase.

• Multi-configuration without changing the hardware in:

<o>Bidirectional regulator.

<o>Single or double switching unidirectional regulator.

<o>Possibility of synchronization in phase, out of phase and in tree mode.

The invention has, among others, the following industrial applications: high voltage charging systems (capacitors, batteries or supercapacitors) and balance systems (battery cells or packs).

The present invention solves the following technical problems of the state of the art at the electronic level:

- Control and programming of cycles (T1, T2 and T3) in DCM mode (discontinuous driving mode), and includes the possibility of changing from CCM mode (continuous driving mode) to DCM depending on the state of the system and the interpretation of the same by the controller.

- Control and programming for different component selections of the current limits of the conduction states T1, T2 and T3.

- Fault detection for long loading times in states T2 and T3, through the use of CPUs and clock interruptions. These interruptions are programmable, and therefore easily adaptable to different charging systems or environments.

- Improvement of the latency of interruption detection and control of the PWM1/2 pulse modulation pins with respect to the commands of the control units.

- Functional improvement against interference from communication buses in the control system, by isolating buses using RAM memory.

- Control of the current in the primary and secondary with the use of interruptions, whose response is programmable depending on the environment or configuration. This DAC configuration adapts cycle by cycle depending on the output voltage. The maximum or minimum value is configurable based on the assigned CPU.

- Programmable multipurpose architecture without the need to use systems such as RTOS (real-time operating system).

- Possibility of controlling driving and operating modes based on the temperature in the controller.

- Control of the precision of the charging system and adaptability to disturbances in the input voltage, real-time configuration and battery failure. This is done by sampling these signals.

- Synchronization of several controllers based on clock signals, to increase current ranges. Operation in synchronous, asynchronous or tree modes, only during the load phase, to reduce operating times. This mode is configured with a digital command.

- Specific memory architecture to maximize hardware resources and design costs.

At the product level, the present invention solves the following state-of-the-art problems:

- Simplification of the manufacturing phase of battery charging products, through the maximization of memory resources and their specialized partition.

- Possibility of configuring multiple application ranges and environments, using multiplexers. This allows the use of other passive or active components to be reduced.

The present invention advantageously allows:

- Programming and configuration flexibility at multiple ranges.

- Flexibility of programming and configuration in unidirectional or bidirectional mode by symmetrical and identical blocks in VINSENSE and VOUTSENSE, in the proposed architecture and application.

- Calibration capacity of the ISENSE, VINSENSE, VOUTSENSE, VPRI blocks when the hardware affects the precision, using the digital to analog converters (DACs) of each block. It allows minimizing the design impact and solving variations due to manufacturing processes (otherwise it would be necessary to change resistances, the precision of which is difficult to find).

- Digital reconfiguration for voltages and currents, for extensive configuration, only with digital commands. Otherwise, components would have to be desoldered and the system re-verified.

- Minimization of firmware design and complexity in the design of final products for the flyback application.

The invention covers the architecture and control system of a charging system (battery or capacitor) consisting of a flyback converter designed to be controlled by a mixed analog/digital system, that is, incorporating digital and analog blocks. The present invention differs from state-of-the-art converters by the union of the following types of blocks:

• ADC: Analog to digital converter.

• DAC: Digital to analog converter.

• AO: Operational amplifiers.

• CPU: Central processing unit.

• Memories.

• PLLs: Phase tracking loops.

• Voltage regulators.

Brief description of the drawings

Next, a series of drawings that help to better understand the invention and that are expressly related to an embodiment of said invention that is presented as a non-limiting example of it are briefly described.

Figure 1 represents a schematic of a typical flyback power supply.

Figure 2A shows a schematic diagram of a flyback controller according to an embodiment of the present invention. Figure 2B shows the signals to be controlled by the flyback controller of the embodiment of Figure 2A. Figure 2C shows the synchronization of two flyback controllers in parallel applied to a charging system. Figure 2D shows the voltage signals (V1,V2) and times (T1,T2) to be controlled in the embodiment of Figure 2C. Figure 2E shows the signals to be controlled by performing Figure 2C for the SINCIN signals in phase-shift synchronization. Figure 2F shows the signals to be controlled by performing Figure 2E for the SINCIN signals in phase synchronization. Figure 2G shows a dual control and synchronization mode of two dual switching flyback controllers. Figure 2H shows the signals used in synchronizing two dual-switching flyback controllers.

Figure 3 illustrates the hardware architecture of a flyback controller according to an embodiment of the present invention.

Figure 4 shows an embodiment of the clock division of the two CPUs.

Figure 5 shows a proposed memory architecture for the two CPUs according to one embodiment.

Figure 6 describes the ADC analog block according to a possible embodiment.

Figure 7 shows the process of converting analog to digital signals by the ADC block.

Figure 8 illustrates an embodiment of the TSENSE analog block, which receives a signal from a temperature sensor.

Figure 9 shows the operation of the TSENSE block.

Figure 10 illustrates one embodiment of the VPRI analog block.

Figure 11 shows the operation of the VPRI block.

Figure 12 represents the hierarchy of buses and blocks of the proposed architecture according to one embodiment.

Figure 13A illustrates one embodiment of the ISENSE analog block (the same block depicted in the figure for ISENSE1 and ISENSE2). Figure 13B illustrates the operation of the ISENSE1 and ISENSE2 blocks in relation to applications with high noise and transients due to the conduction of Q1.

Figure 14 represents an embodiment of the analog DAC block.

Figure 15 illustrates the operation of the controller in DCM mode.

Figure 16 describes the operation of the controller in CCM mode.

Figure 17 represents an embodiment of the VOUTSENSE analog block. The same scheme corresponds to the VINSENSE analog block.

Figure 18 describes the PWM digital block.

Figure 19 describes the proposed operation of CPU2 interrupt execution.

Figure 20 illustrates the operation and description of the charging phases.

Figure 21 illustrates a flow chart of the control algorithm according to one embodiment.

Figure 22 illustrates a flowchart of the scheduling algorithm according to one embodiment.

Figure 23 shows a flow chart of the protection algorithm according to one embodiment.

Figure 24 describes the GPIO/PWM digital block.

Figures 25A and 25B describe the synchronization mode according to one embodiment.

Figure 26 illustrates the operation of the synchronization system.

Figure 27 shows an application of the present invention in radio frequency and a defibrillator system.

Figure 28 illustrates an application of the present invention in battery balancing systems.

Figure 29 shows an application of the present invention in a bidirectional system.

Figure 30 shows an application of the present invention in a solar energy use system.

Detailed description of the invention

Figure 1 shows a basic schematic of a typical flyback power supply 1, which is a regulated power supply with a high-power flyback type topology regulated by voltage or current, which allows adjusting voltages in a certain voltage range and is capable of providing a programmable voltage.

The flyback power supply 1 comprises a main controller or regulator (flyback controller 10), a transformer T1, a transistor Q1, and a set of resistors (R1, R3, R4, R5, R6) and capacitors (C1, C3). Flyback power supply 1 operates as a battery charger, with primary current sampling (I_SENSE), output voltage sampling (VOUT_SENSE), and optionally input voltage sampling (VIN_SENSE). Sampling of these voltages and currents is done by voltage division to prevent damage to the flyback controller 10. The VIN_SENSE voltage is divided by resistors R3 and R4, the VOUT_SENSE voltage is divided by resistors R5 and R6, and the calculation The I_SENSE current is determined by sampling the voltage across resistor R1. The use of this topology allows the miniaturization of the hardware architecture and its simplification. The flyback 1 power supply is programmable in voltage and current ranges. The programming of said voltage is carried out by controlling the duty cycle of the transistor Q1 by the flyback controller 10. As a general case, the output voltage of a flyback topology is governed by the following relationship (where N is the winding ratio of the transformer T1, D is the duty cycle of transistor Q1, V<in>is the input voltage or voltage of the flyback power supply 1, VOUT is the output voltage or voltage of the flyback power supply 1):

Figure 2 shows a schematic diagram of a control system 7 of a piezoelectric actuator 2 using a flyback controller 10 according to an embodiment of the present invention. These systems, known as “piezomotiori”, are characterized by having multiple voltage ranges that can range from a few volts to 1000 V, since being capacitive actuators, their extension, activation or force capacity depends on the voltage used. The example in Figure 2A shows a control circuit for a positive voltage actuator. This voltage and control allows control over the variables detailed in the graph of Figure 2B. The rise or fall time, determined by T1 and T2 in the graphs in Figure 2B, depends on the resistance R2. Sampling the voltage present in the piezoelectric element through an amplifier 3 allows readjustment of the voltage range based on commands from a master processing unit 50.

The required blocks included in the flyback controller 10 for effective control of the output voltage are the following (in addition to the clock generation and regulation blocks necessary for its operation):

- First central processing unit 13 (CPU1) and second central processing unit 14 (CPU2): responsible for controlling the operation of the flyback controller 10 in real time, from software housed in memory 15

- Memory 15: responsible for storing data in real time and the execution program of the CPUs (13,14).

- Current sampling block 17a (ISENSE1): responsible for sensing the current in the primary of transformer T1 for subsequent processing by the second CPU 14 (CPU2).

- Input voltage sampling block 18 (VINSENSE): responsible for reading and adapting the input voltage in the primary of transformer T 1 for subsequent processing by the second CPU 14 (CPU2).

- Output voltage sampling block 19 (VOUTSENSE): responsible for reading and adapting the output voltage on the secondary of transformer T1, for subsequent processing by the second CPU 14.

- Temperature sampling block 20 (TSENSE): responsible for reading and adapting the temperature of transformer T1 for subsequent processing by the second CPU 14.

- PWM 21 block (pulse width modulation): responsible for the synchronization and control of pulse width modulators, based on the system's target voltage.

- Transformer voltage control block 22 (VPRISENSE): responsible for controlling the voltage in the primary of transformer T1 to avoid saturation of the primary of transformer T1 or of the transistor Q1;

- Communication unit 23 (SCI block): responsible for communication and transmission of the real-time operation of the system, communicating the first central processing unit 13 with the external master processing unit (50), so that the central processing unit 13 can receive control commands from the master processing unit (50).

- 33 timers, used by the CPUs (13,14).

The illustration shown in Figure 2A is considered ideal for low power. For high powers, the reading of the voltages is subjugated to the need for a galvanic isolation system, through the use of an opto-coupler or a differential amplifier with galvanic isolation in the VOUTSENSE voltage reading.

Figure 2C shows, according to an embodiment of the present invention, a schematic diagram of a battery charging system 8 using a plurality of flyback controllers connected in parallel. In particular, Figure 2C shows the synchronization of two flyback controllers (10a,10b) in parallel (although more flyback controllers can be connected in parallel) applied to charge a high current absorption battery 9 or storage element. The synchronization of two or more flyback controllers in parallel allows the generation of current pulses, which depending on whether their synchronization is in phase, phase shift or tree, can multiply the current by as many controllers in parallel when they are synchronized in phase (Figure 2F to create a continuous charging system by mitigating the timing losses during the conduction state of transistor Q1 if the timing is out of phase (Figure 2That mitigates the timing losses of Q1.

During battery charging 9, high current ranges are assumed to exist; Therefore, monitoring the charging current, although not mandatory, is recommended. The monitoring of the load current has been represented in Figure F2C from a Hall effect sensor 4, whose adaptation is carried out by a differential amplifier 5 for processing from the second CPU 14 (CPU2) and a second block current sampling device 17b (ISENSE2) which has the function of reading and accommodating the currents captured in the secondary of the transformer T 1.

Advantageously, the battery charging system 8 of Figure 2C allows the reduction of charging times by synchronizing the flyback controllers (10a, 10b) with the use of a synchronization signal (SYNCIN). Said signal has an effect on the pulse width modulator signal that acts on the transistor Q1, after its processing by the second CPU 14 (CPU2). Another additional advantage is the simple monitoring of the current in the secondary of the transformer T1 without the need for galvanic isolation by using a Hall effect sensor 4. As shown in Figure 2D, this circuit only has control over the voltages V1, V2 and times T1 or T2. The target voltage reading can be processed by any of the flyback controllers (10a,10b) in Figure 2C. The master processing unit 50 has control over the loading state, activation or deactivation of the synchronization from the SCI block 23 and its processing by the first CPU 13 (CPU1).

The synchronization of the different flyback controllers (10a, 10b) in parallel is carried out using a digital synchronization signal (SYNCIN) that, when activated on the rising edge, activates the PWM1 signal of the pulse width modulator that acts on the transistor Q1, so that in phase synchronization mode the current ranges applied to the load are increased, and in phase synchronization mode there is a delay to create a continuous current load.

The blocks required in the flyback controllers for effective control of the battery charging system 8 represented in Figure 2C are the following (in addition to the clock generation and regulation blocks necessary for its operation):

- First CPU 13 (CPU1) and second CPU 14 (CPU2).

- Memory 15.

- Current sampling blocks 17a (ISENSE1) and 17b (ISENSE2).

- Input voltage sampling block 18 (VINSENSE).

- Output voltage sampling block 19 (VOUTSENSE).

- Temperature sampling block 20 (TSENSE).

- PWM block 21.

- Transformer voltage control block 22 (VPRISENSE).

- SCI Block 23.

- Timers 33.

- SYNC 6 synchronization block or unit, responsible for synchronization between the flyback controllers through the use of a synchronization signal (SYNCIN).

Figure 2G shows a schematic diagram of another embodiment of a battery charging system 8 using a plurality of flyback controllers. According to this embodiment, a dual control and synchronization mode of two dual switching flyback controllers (a first flyback controller 10c connected to the primary of the transformer T1 and a second flyback controller 10d connected to the secondary of the transformer T1) is realized.

This control and synchronization is performed through the use of the SYNCIN and SYNCOUT signals, as shown in Figure 2H, with the objective of synchronizing the control modes of the controllers from the primary and secondary. This embodiment aims to mitigate the integration and programmability in the manufacturing phase of flyback controllers or power modules for multiple ranges in battery charging or balancing systems, since depending on whether the battery 9 is divided into packages with multiple cells Voltage ranges may vary, also requiring, in some cases, bidirectional control mode. The minimum blocks required for effective output voltage control are: first CPU 13 (CPU1), second CPU 14 (CPU2), memory 15, current sampling block 17a (ISENSE1), input voltage sampling block 18 ( VINSENSE) in the first flyback controller 10c, output voltage sampling block 19 (VOUTSENSE) in the second flyback controller 10d, temperature sampling block 20 (TSENSE), PWM block 21, VPRISENSE block 22, SCI block 23, timers 33, SYNC 6 block, in addition to the clock generation and regulation blocks necessary for its operation.

Figure 3 illustrates a block diagram of the hardware architecture of a flyback controller 10 according to one embodiment. The flyback controller 10 represented in the example in the figure is used within a power system (flyback power supply 1) to charge a battery 9 or capacitor and includes the following functional blocks:

- Internal oscillator 11: functional block responsible for generating the clock signal for all digital blocks, such as CPUs (central processing units), memory or communication buses.

- PLL 12 (phase tracking loop): Block responsible for multiplying the reference signal coming from the oscillator and dividing it between the following functional blocks such as CPUs, ADCs (analog to digital converters), memory, communication buses, as shown. represented in Figure 4, which shows the division of CPU1/CPU2 clocks according to a possible realization of the proposed architecture.

- CPUs (13,14): Central processing units that comprise a first CPU 13 (CPU1) and a second CPU 14 (CPU2) responsible for controlling the operation of the flyback controller 10 in real time, from software hosted in a memory 15.

- Memory 15: Functional block responsible for storing data in real time and the execution program of the CPUs (13,14). It may include, for example, a ROM memory 15a, an OTP memory 15b (one-time programmable), a flash memory 15c, a shared RAM memory 15d between CPU1 and CPU2, and a CPU1 SRAM memory 15e (for CPU1) and a CPU2 15f SRAM memory (for CPU2). Figure 5 shows the proposed minimum CPU1/CPU2 memory division and architecture according to one embodiment, including a CPU1 register bank 15g, a CPU2 register bank 15h, a CPU1 vector table 15i, a CPU2 vector table 15j and some parameters. 15k configuration included in 15c flash memory. Each element is described below:

• ROM memory 15a: Storage of a boot loader (or bootloader). This software has the function of activating the program in its basic functions. In the event of a memory failure, the bootloader would always have control and read capability over all memory regions.

• Register bank (15g,15h): Memory region that has the configuration registers of each of the attached blocks.

• Vector table (15i,15j): Memory region that contains interrupt control and start addresses in RAM.

• Shared memory CPU1/CPU2 15d: Exchange memory that has the function of sharing data and variables between CPU1 and CPU2 in real time. Protection values, voltages and target current are programmed in this region.

• SRAM memory (15e,15f): Execution memory used during the execution of the firmwares where, in the normal execution period CPU1/CPU2, vector table (interrupts) and values of writing and reading registers of each block are stored. functional. Each CPU is assigned a start and end address for reading.

• 15c flash memory: Memory used to store the firmware, both for CPU1 and CPU2. This software has the final functional capability of the battery charging system. Each CPU is assigned a start and end address for reading. Copying data from flash memory to RAM is done exclusively by CPU1. In this region, 15k configuration parameters are programmed, including protection values, calibration, target voltages and current, in the predetermined address.

• OTP Memory: Memory with the function of storing manufacturing data, such as date, location and operator. Limited access only from CPU1.

- ADC block 16 (analog to digital converter): The ADC block 16 has the function of reading the analog variables and switching the multiplexers for processing by the CPUs (13,14). The ADC block 16 can read or sample the values of input voltage VINSENSE, output voltage VOUTSENSE and transformer temperature TSENSE from the control of a multiplexer 27 (using the signal reg_mux_adc_ctrl, as shown in Figure 6 that describes the block ADC 16 according to a possible realization). Figure 7 shows the process of converting analog signals to digital: By activating in the second CPU 14 (CPU2) one of its timers 33 and setting it to a certain frequency, a stable clock signal is generated, which generates an interrupt of time on CPU2. This activation of the interrupt allows CPU2 to jump over a region of SRAM memory (Figure 5), in which by controlling the multiplexer signal reg_mux_adc_ctrl (Figure 6), it allows the reading of the signals coming from the VOUTSENSE pins ( vout_diff_sense), VINSENSE (vin_diff_sense), TSENSE (Temp_diff_sense), or ADJ (adj_sense). This signal can be controlled so that each of the readings is x1, x2, or xn up to the timer limit.

- ISENSE current sampling blocks (17a,17b): Current sensing blocks that have the function of reading and accommodating the currents captured in the primary (first current sampling block 17a, ISENSE1) and secondary (second sampling block current 17b, ISENSE2) of transformer T1 for subsequent processing by the CPUs (13,14).

- Input voltage sampling block 18 (VINSENSE): Block responsible for reading and adapting the input voltage in the primary of transformer T1 for subsequent processing by the ADC 16 and the second CPU 14 (CPU2).

- Output voltage sampling block 19 (VOUTSENSE): Block responsible for reading and adapting the output voltage on the secondary of transformer T1, for subsequent processing by ADC 16 and the CPU in charge (second CPU 14) .

- Temperature sampling block 20 (TSENSE): The TSENSE 20 block is responsible for reading and adapting the temperature of the transformer T 1, for subsequent processing by the ADC 16 and the CPU in charge (second CPU 14). Figure 8 illustrates one embodiment of the TSENSE block 20, which receives the output signal from a temperature sensor 29. Figure 9 shows the operation of the TSENSE block 20 of Figure 8. The TSENSE block 20 is designed to capture the temperature signal coming from a specific component, using thermal or other single output diodes. The use of the DAC2 (Figure 8), controlled from the cpu_dac2_reg signal, allows the calibration of the voltage reading and the adaptation of said voltage to a range that allows solving the ADC offset error.

- PWM 21: Block responsible for synchronizing and controlling the pulse width modulators PWM1 and PWM2, based on the system's target voltage.

- VPRI 22: Block responsible for controlling the voltage in the primary of transformer T1 during the charging phase. Figure 10 illustrates an embodiment of the VPRI block 22. Figure 11 shows the operation of the VPRI block 22 of Figure 10, where the DAC3, the diode D1 and the resistors R7 and R8, allow control to avoid saturation of the transformer primary or the transistor Q1 . The post-conduction transient of transistor Q1 depends on the output voltage, and the remaining energy during conduction phases 2 or 3 depends on the CCM or DCM conduction modes. This block allows the control of these transients to protect the circuit by programming the DAC3 depending on the state of charge. This reference could be used to determine the output voltage, but only in specific applications.

- Communication unit 23 (SCI /UART /I2C): Block responsible for communication and transmission of the real-time operation of the system.

- GPIO (General Purpose Input/Output) 24: Block in charge of controlling digital signals, both input and output. The pins involved are: PWM1, PWM2, PG, CHARGE, SYNCIN and SYNCOUT.

- DACs block (digital to analog converters): Block of several digital-analog converters (DACn_a, DACn_b, DACn_c) 25 in charge of adjusting digital parameters such as reference voltages, current limits, calibration values or voltage limits, in the blocks VINSENSE 18, VOUTSENSE 19, TSENSE 20, VPRI 22, ISENSE1 17a and ISENSE2 17b. The DACs 25 allow calibration in the manufacturing phase and compensate for hardware errors due to different causes. These errors (V<Error m em>) are stored in memory for later processing. The final value of the DAC (V<DACx>) in the ISENSE1 or ISENSE2 blocks would be the reference value (V<vaiue ref>) plus the addition or subtraction of the error stored in memory during the manufacturing phase (V<Error_mem>) .

- Regulators 26: The voltage difference between the analog (v_ana) and digital (v_digi) blocks makes it necessary to use internal regulators. These regulators adapt the voltage for the correct precision of ADCs, DACs and digital control. The supply pins are determined by VDD and VS (Figure 3).

- Multiplexer 27: They are controlled through a comparator block 30 represented in Figure 12, which illustrates the hierarchy of buses and blocks of the proposed architecture according to a possible embodiment. It has the function of controlling the DACs of the ISENSE1 17a, ISENSE2 17b, VINSENSE 18, VOUTSENSE 19, TSENSE 20 blocks.

Battery charge control is carried out on the second CPU 14 (CPU2). The division into two central processing units (CPU1 and CPU2) allows performance improvement by assigning different tasks to each one, so the implementation of a real-time operating system (RTOS) is not necessary. Communication between CPU1 13 and CPU2 14 is carried out through the shared RAM memory region 15d. Load control is determined by discontinuous driving mode (DCM), with two functional variations:

1. Programmed load: During the initial operating state, transistor Q1 conducts up to a certain limit, programmed by the digital-to-analog converter DAC1 25, represented in Figure 13A (which describes the current sampling blocks ISENSE1 17a and ISENSE 2 17b and a comparator block 28) and in Figure 14 (where the DACs 30 digital-to-analog converter block is represented, which includes a CPU2 peripheral bus interface 31 to communicate with the CPU2 14, a DACs control unit 32 and the DACs themselves 25 ), and configured from an IPRI_LIMIT communication command, on CPU1 13. Figure 13B illustrates the operation of the ISENSE1 and ISENSE2 blocks in relation to applications with high noise and transients due to the conduction of Q1, where the interruption is detected before the noise, the “Noise Area” window is the time the circuit needs to be quiet after switching Q1, and the adaptation window is the instant of time for the controller to read the environment variables of the ADC or driving the rest of the elements, these moments being processed by CPU2.

When said IPRI_LIMIT limit is reached, the ISENSE current sampling block (Figure 15, which describes, for the DCM discontinuous conduction mode, the control of the states T1 (Q1=ON, D1=OFF), T2 (Q1 = OFF, D1 =ON) and T3 (Q1 =OFF, D1 =OFF), the IPRI current in the primary of transformer T1 and the ISEC current in the secondary of transformer T1), either by rising or falling free, activates the interrupt cpu_pwm_isr_x (where x is 1 for ISENSE1 and 2 for ISENSE2). From this state, CPU2 14 deactivates transistor Q1 (going to state T2, programming the configuration state of Q1 to OFF) depending on the output voltage VOUT, programmed using a VOUT_COMMANDO command, through CPU1 13 Said output voltage V<out> is sampled and conditioned from the VOUTSENSE 19 block.

The differential error of the value of VOUT_COMMANDO and the value read by the VOUTSENSE block 19 affects the DAC 1 and DAC2 of the ISENSE blocks (17a,17b), since during the final loading phase the ideal control mode is a driving mode continuous CCM (Figure 16, which describes the control of the states T1 (Q1=ON, D1=OFF) and T2 (Q1=OFF, D1=ON) of the CCM continuous driving mode) to avoid damage to the battery 9 The VOUTSENSE 19 block performs direct or differential sampling with the DAC5 reference value controlled by the VOUT_COMMAND command (Figure 17, which describes the VOUTSENSE 19 block) and cpu_mux_dac1/2 multiplexer control. If the direct value is selected, the computation would be performed in the CPU2 14 firmware.

2. Charging with current control: During the initial operating state, transistor Q1 conducts up to a limit determined and programmed by the DAC1 (Figures 13 and 14) in the ISENSE1 block 17a. The value of DAC1 is configured from the IPRI_LIMIT communication command, from CPU1 13. When said IPRI_LIMIT limit is reached, the ISENSE block (Figure 15), either by up or down frame, activates the cpu_pwm_isr interrupt. From this state, CPU2 14 deactivates transistor Q1 and activates transistor Q2. The ISEC load current is sampled, therefore this limit is sampled in the ISENSE2 block 17b, from DAC1 or DAC2 (Figure 13), programmed with the ISEC_LIMIT command. The control of the T3 state of the DCM discontinuous driving mode is carried out from the cpu_pwm_d3_isr interrupt and its programming from the DCM_D3_COMMANDO command. When the interrupt cpu_pwm_d3_isr_x (where x is 1 for ISENSE1 and is 2 for ISENSE2) has been activated on CPU2, transistor Q2 is disabled and the corresponding timer starts counting up to the DCM_D3_COMMANDO limit as it triggers the timing interrupt. When the termination interrupt is activated, conduction mode T1 begins, with the state of transistor Q1 activated. This operation is carried out in parallel; Therefore, CPU2 is in charge of other operations, such as protection, or reading the ADC. The value of the DACs in the ISENSE1 and ISENSE2 blocks is determined by the value of the output voltage and the final state of charge. These parameters are configured with the VOUT_COMMANDO command, just like the scheduled load.

Each of the time instants determined by T3 or T2 in the programmed mode is realized with the activation of time interruptions. This is done by using a timer within CPU2, as shown in Figure 12. The accuracy of this timer depends on the characteristics of the PLL and the CPU, as well as their reference frequencies. The latencies between the switching speed of the comparators of the comparator block 28 in the ISENSE1 and ISENSE2 blocks and the detection of the CPU could cause a short circuit; Therefore, it is necessary to use control signals as shown in Figure 18, which describes the PWM block 21. The control of the PWM1 or PWM2 pin requires the control of the cpu_pwm_d3_isr_x, cpu_pwm_isr signals and the CPU2 signals controlled by reg_pin_pwm1 and reg_pin_pwm2. These signals can be multiplexed from the pwm2_mux multiplexer control. Figure 19 includes an example of the proposed operation for the execution of interrupts (ADC_isr, cpu_pwm_isr, cpu_pwm_d3_isr) of the ADC block 16 and PWM 21 on CPU2.

During the entire charging phase, the controller samples the different signals such as: input voltage V<in> (Figure 3) from VINSENSE, operating temperature from the temperature sampling block 20 TSENSE, the status of the transformer after discharge from VPRI block 22.

Activation or deactivation of the charge mode can be done by an OPERATION command determined in a system configuration phase that will be described later, or by using the CHARGE digital pin (Figure 3).

As shown in Figure 20, which describes the operation of the charging phases, the operation of the charge depends on the state of the charging system. Control is performed by sampling the output voltage V<out>from VOUTSENSE. The proposed minimum charging phases are detailed below:

<o>Initialization phase 40: The charging system performs current charging control. The charging system has a low target voltage, therefore during the conduction state of Q1 the primary of transformer T1 is charged to a high limit. During the second conduction state of Q2, transformer T1 discharges onto battery 9 or capacitor. The initialization phase is set to a first load voltage limit (for example, up to 10% of the target voltage), controlled by the state of the differential value of the VOUT_COMMANDO command and the value of VOUTSENSE.

<o>Charging phase 41: The charging phase 41 is established between a first charging voltage limit (e.g. 10% of the target voltage) and a second charging voltage limit (e.g. 90% of the target voltage), with a similar operation to the initialization phase (charging with current control), but with progressive control of the IPRI_LIMIT command and its attached DAC.

<o>Regulation phase 42: Battery 9 voltage is near its limit determined by the VOUT_COMMAND command. When the voltage exceeds the second load voltage limit (e.g. 90%), from this state the ideal conduction mode is a CCM continuous conduction mode. For this reason, the control of IPRI_LIMIT and ISEC_LIMIT, and their attached DACs (Figures 13 and 14) are programmed to avoid overcharging the battery 9 until it is fully charged and the charging system is deactivated.

Figure 21 represents a flow chart of a control algorithm according to one embodiment. When loading or activating the controller is done from the CHARGE pin or the OPERATION command, CPU2 activates the PWM1 pin from low to high. This causes the current in the primary to increase to the limit programmed by the DAC2 using the ISENSE1A_COMMANDO command. When the limit is reached, the cpu_pwm_isr_x signal goes from high to low, therefore activating the related interrupt in CPU2. This activation causes CPU2 to jump to the RAM region pre-programmed in the vector table. When this function is activated, it sets the state of the PWM1 pin low. The CPU2, based on the state of the OPERATION command in bit (2), can determine whether only the ISENSE1 block (scheduled load) or ISENSE1 and ISENSE2 (regulated load) should be used. If the load mode is programmed, CPU2 returns to its original position, activating the Toff timer on its way, which controls the conduction state of D1; If the interrupt is activated, it deactivates said timer and modifies the state of the PWM1 pin, setting it to a high level. If, on the other hand, the load is regulated, CPU2 activates the PWM2 pin, setting it to a high level, CPU2 returns to its origin until the interrupt cpu_pwm_D3_isr is activated, jumping in the same way to another pre-programmed memory region in the vector table, setting the state of the PWM2 pin low. If the driving mode is discontinuous, CPU2 will activate the timer at a predetermined time instant for state T3 of the discontinuous driving mode. Once T3 is activated, after the return of CPU2 to its source memory position, it will activate the PWM1 pin again.

The flyback controller 10 has a pre-programming phase, where the CPUs are programmed, since the memory is initially without running firmware for CPU1 and CPU2. Figure 22 shows a scheduling algorithm for CPU1 and CPU2, according to one embodiment. The operation of the flyback controller is carried out by CPU1 and a bootloader. The bootloader is located in ROM 15a. The ROM memory 15a can be programmed in production, which allows the reduction of work times during the manufacturing phase of the flyback controller.

The boot loader programmed in ROM memory 15a has basic operating commands, such as: Read memory address, program memory address, controller status and firmware execution. The precision of such commands is determined by the precision of the CPU and the selected communication bus frame. Below are a series of minimum commands proposed in the boot loader:

- BOOTLOADER_VERSION: Reading the bootloader version.

- REG_ADDR_COMMANDO: Loading the address of a specific register (read or write).

- REG_DATO_COMMANDO: Loading of data from a specific registry.

- FLASH_ADDR_COMMANDO: Storage of the flash address to be read or programmed.

- FLASH_DATO_COMMANDO: Data to be stored in the flash address.

- FLASH_CONTROL_COMMANDO: Storage control over FLASH address and firmware execution

The programming phase state does not provide any functionality to the flyback controller in its regulation or charging phase. Therefore it is necessary to load a control firmware in flash memory 15c or SRAM (15e,15f), depending on its partition between CPU1 and CPU2. Programming into the relevant FLASH memory regions is carried out using programmed bootloader commands. Once the CPU1 and CPU2 firmwares have been loaded into the flash memory regions 15c via the controller communication bus, the firmware execution is performed in the SRAM memory (15e,15f) as it has better speed. of execution. Therefore, the firmware housed in 15c flash memory must be loaded into RAM after each reboot, since RAM only has temporary storage.

The flyback controller 10 also has a configuration phase, in which the system configuration is carried out by communicating commands for subsequent storage in memory. The precision (size) of the commands can be set between 8 and 32 bits, depending on the precision of the selected CPU. A series of commands proposed as examples are described below:

- OPERATION: Digital control command of the controller, allowing charging start/stop, master configuration in synchronization mode and slave configuration in synchronization mode.

- VOUT_TRIM_COMMANDO: Output voltage calibration command.

- VOUT_MODO_COMMANDO: Output voltage mode selection command (digital or analog).

- VOUT_COMMANDO: Output voltage programming command. DAC5 control.

- VOUT_MARGEN_HIGH: Maximum output voltage.

- VOUT_MARGEN_LOW: Minimum output voltage.

- VIN_OV_COMMANDO: Control against overvoltages in V<in>.

- VIN_UV_ALERTA: Control against low voltages in V<in>.

- PARAM1_COMMANDO: Parameter configuration command 1.

- VPRI_COMMANDO: Reference voltage parameter for VPRI. DAC3 control.

- ISENSE1A_COMMANDO: DAC1 control command cpu_dac1_reg_1.

- ISENSE2A_COMMANDO DAC1 control command cpu_dac1_reg_2.

- READ_VIN: Command to read the input voltage V<in>.

- READ_IIN: Command to read the input current I<in>.

- READ_IOUT: Command to read average load current. DAC1 and DAC4 states.

- READ_VOUT: Command to read the output voltage V<out>.

- LEER_TEMP: Temperature reading command.

- LEER_FLASH_COMMANDO: Flash memory reading command.

- ESCRIBIR_FLASH_COMMANDO: Flash memory writing command.

- FIRMWARE VERSION: Firmware version.

- HARDWARE VERSION: Hardware version.

The configuration phase is carried out exclusively on CPU1. The programmed commands have a functional effect on CPU2, and their configuration is carried out on the DACs and the control parameters of the control loop.

Once the system is programmed and configured, based on the selected hardware components, the next phase of operation is the battery charge control, described above. Both CPU1 and CPU2 find their limitation in the implemented instruction set. The minimum necessary instructions proposed for the CPUs are detailed below:

- AND: Logical AND operation.

- OR: Logical OR operation.

- SUB: Subtraction Operation.

- ADD/ADDC: Add/Add Operation with Carriage Return.

- CMP: Comparison operation.

- MOV: Move operation.

- SHIFTING: Move bits to the left or right.

- CLR: Registry Cleanup Operation.

- MULT/DIV (CPU2 only): Multiplication and division.

- CALL/STEP/RETURN: Jump functions to memory addresses.

- LW/SW: Information loading and saving functions.

The flyback controller 10 also has a protection phase, which has the function of analyzing the operation of the system in the event of failures. This programming is carried out using the following commands, based on the use of CPU1 and its placement in the shared memory region between CPU1 and CPU2:

- VOUT_OV_FALLO: Protection against overvoltages.

- VOUT_ALERTA: Overvoltage range warning.

- IPRI_OC_FALLO: Protection against primary and secondary overcurrents.

- ISEC_OC_FALLO: Protection against envelope in the secondary.

- VIN_OV_ALERTA: Control against high voltages in the input voltage V<in>.

- VIN_UV_ALERTA: Control against low voltages in the input voltage V<in>.

- STATUS CMD: System status command.

- TEMP_OTP_FALLO: Over-temperature detection command.

Said monitoring and control is carried out from CPU2. The fault status is displayed by using the PG pin (“Power Good”, Figure 3), or by reading the STATUS_CMD command, which updates the shared memory region between CPU1 and CPU2, which can be read from of the CPU1 communication bus. The configuration of such commands depends on the system configuration as well as your application environment. Figure 23 shows a flow chart of a protection algorithm according to one embodiment. Once the ADC read control timer activates, CPU2 reads the status of the input values of the VINSENSE, VOUTSENSE, TSENSE, or ADJ pins, from the multiplexer control reg_mux_adc_ctrl. Once the voltages have been processed, CPU2 reviews the value of said ranges from the pre-programmed values through CPU1 and the commands VIN_OV_ALERTA, VIN_UV_ALERTA or TEMP_OTP_FALLO, the faults are activated in value STATUS_CMD, which is read from CPU1.

The flyback controller 10 also has a synchronization phase, the function of which is to synchronize different flyback controllers 10 in parallel to increase the charging current range or provide continuous operation during the charging phase. As shown in Figure 3, the proposed synchronization mode is carried out through the SYNCIN pins (for connection with a master processing unit 50 or a master flyback controller) and SYNCOUT (for connection with a slave flyback controller 51 ). Said synchronization mode is carried out by selecting said value in the OPERATION command established in the configuration phase.

The SYNCIN signal is read by means of rising and falling edge interruptions on CPU2, and its direct transmission on the PWM block, cpu_sincin_isr, as shown in Figure 24, which describes the GPIO block 24 and PWM 21. The generation of SYNCOUT is done from CPU2 14 and the value read from VOUTSENSE in relation to the VOUT_COMMANDO command programmed in the shared memory region. The transmit signal over PWM1 is transmitted over the SYNCOUT signal simultaneously. The SYNCOUT signal can be multiplexed for direct output from PWM1 or from the CPU. This mutiplexing is done from cpu_syncout_mux.

As shown in Figures 25A and 25B, where the synchronization mode is described, the synchronization phase can only be performed during the charging phase up to a certain percentage determined by VOUT_COMMANDO. When each controller detects a higher voltage, it deactivates, and performs voltage control to avoid overloading or damaging load cells. Figure 26 shows the operation of the synchronization system, with the switching on and off of transistors Q1 and Q2 depending on the value of the SYNCIN signal.

The flyback converter 10 of the present invention can be used in multiple applications. Figure 27 shows several flyback controllers (10e, 10f, 10g, 10h) in a radio frequency application or that determined by Figure 2C. The synchronization of the conduction of the primary transistor Q1 and the secondary conduction element allows increasing the load current in a more efficient way, without the design of a new transformer. This synchronization is performed from the SYNCIN/SYNCOUT signals, as detailed in Figure 2D, and the synchronization modes are detailed in Figures 2E and 2F. The general status of the system is determined from the PG (Power Good) pin, using a digital pin, which allows a faster response to a failure.

In Figure 28, several flyback controllers (10a, 10b) are applied in a battery balancing system. High voltage charging systems are made up of cell packs. Each package has multiple cells configured in series and parallel. This splitting of cells causes the target voltage of the entire block to be unevenly realized, so the packs and cells can become unbalanced. Dividing regulators into packages allows for more efficient charging of the entire cell block. This division requires the implementation of multiple flyback regulators for different voltage ranges. As detailed in the illustration, these regulators can be synchronized to load the system more efficiently using digital signals (SYNCIN and SYNCOUT). The general status of the system is determined from the PG (Power Good) pin, using a digital pin, which allows a faster response to a failure.

The embodiment of Figure 29 is similar to that shown in Figure 2G.

Finally, the realization of Figure 30 shows the application in a solar energy use system, determined by the circuit of Figure 2C. Solar charging systems do not have a constant current flow, so at times of day during high hours of solar radiation the adaptation of the ISENSE1 and ISENSE2 block must be modified to charge the charging element in a more efficient way. This ability to not be able to generate power continuously requires the use of an intermediate storage system. This control of the external state of the system is carried out with the master processing unit 50 (or a control and regulation unit), and its communication from the SCI block and the CPU1.

Claims (10)

1. A flyback controller (10), configured for the regulation of a flyback power supply (1) that includes a transformer (T1) and a transistor (Q1) regulated by the flyback controller (10), characterized in that the flyback controller (10) includes: - a first central processing unit (13) and a second central processing unit (14), responsible for controlling the operation of the flyback controller (10) in real time; - a memory (15), responsible for storing data in real time and the execution program of the central processing units (13,14); - a first current sampling block (17a), responsible for measuring the current in the primary of the transformer (T1) for processing by the second central processing unit (14); - an input voltage sampling block (18), responsible for reading and adapting the input voltage in the primary of the transformer (T1) for processing by the second central processing unit (14); - an output voltage sampling block (19), responsible for reading and adapting the output voltage in the secondary of the transformer (T1) for processing by the second central processing unit (14); - a temperature sampling block (20), responsible for reading and adapting the temperature of the transformer (T1) for processing by the second central processing unit (14); - a pulse width modulation block (21), responsible for synchronizing and controlling pulse width modulators from a target voltage; - a transformer voltage control block (22), responsible for controlling the voltage in the primary of the transformer (T1) to avoid saturation of the primary of the transformer (T1) or the transistor (Q1); and - a communication unit (23), responsible for communicating the first central processing unit (13) with an external master processing unit (50) to receive control commands. 2. The flyback controller according to claim 1, characterized in that it is configured to control the tension of a piezoelectric actuator (2). 3. The flyback controller according to claim 1, characterized in that it is configured to control the charge of a battery (9) by connecting it in parallel with at least one additional flyback controller (10b). 4. The flyback controller according to claim 3, characterized in that it comprises a synchronization unit (6) responsible for synchronization, in phase or out of phase, with the at least one additional flyback controller (10b) through the use of a synchronization signal (SYNCIN). 5. The flyback controller according to claim 3 or 4, characterized in that it comprises a second current sampling block (17b), responsible for monitoring the load current in the secondary of the transformer (T1), from the measurements of a Hall effect sensor (4), for processing by the second central processing unit (14). 6. The flyback controller according to claim 5, characterized in that the second central processing unit (14) is configured to control the current in the primary and secondary of the transformer (T1) by activating interruptions when a limit is exceeded. of current (IPRI_LIMIT, ISEC_LIMIT) programmed. 7. A battery charging system (8), characterized in that it comprises a plurality of flyback controllers (10a,10b; 10c,10d) according to claim 1. 8. The battery charging system according to claim 7, characterized in that it comprises: - a plurality of flyback power sources (1a, 1b) connected in parallel feeding a battery (9), where each flyback power source (1a, 1b) comprises a flyback controller (10a, 10b) according to claim 1, and where each flyback controller (10a, 10b) comprises a synchronization unit (6) responsible for synchronizing, in phase or out of phase, between the flyback controllers (10a, 10b) through the use of a synchronization signal (SYNCIN); and - a master processing unit (50) in charge of controlling the battery charge (9) by sending control commands to the communication unit (23) of the flyback controllers (10a, 10b). 9. The battery charging system according to claim 8, wherein the flyback controllers (10a, 10b) of the flyback power supplies (1a, 1b) comprise a second current sampling block (17b), responsible for monitoring the current. load on the secondary of the transformer (T1) from the measurements of a Hall effect sensor (4). 10. The battery charging system according to claim 7, characterized in that it comprises: - a first flyback controller (10c) connected to the primary of the transformer (T1) and with an input voltage sampling block (18) for reading the input voltage on the primary of the transformer (T1); - a second flyback controller (10d) connected to the secondary of the transformer (T1) and with an output voltage sampling block (19) for reading the output voltage on the secondary of the transformer (T1); - master processing units (50c, 50d) connected to the respective communication units (23) of the flyback controllers (10c, 10d) and responsible for controlling the battery charge (9) by sending some commands control to flyback controllers (10c,10d); and where each flyback controller (10c, 10d) comprises a synchronization unit (6) responsible for synchronizing between the flyback controllers (10c, 10d) through the use of synchronization signals (SYNCIN, SYNCOUT).