ES2869865T3 - Método y aparato para realizar operaciones de recolección y copia SIMD - Google Patents

Método y aparato para realizar operaciones de recolección y copia SIMD Download PDF

Info

Publication number
ES2869865T3
ES2869865T3 ES17729733T ES17729733T ES2869865T3 ES 2869865 T3 ES2869865 T3 ES 2869865T3 ES 17729733 T ES17729733 T ES 17729733T ES 17729733 T ES17729733 T ES 17729733T ES 2869865 T3 ES2869865 T3 ES 2869865T3
Authority
ES
Spain
Prior art keywords
memory
processor
addresses
simd
copy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES17729733T
Other languages
English (en)
Spanish (es)
Inventor
Eric Wayne Mahurin
Jakub Pawal GOLAB
Lucian Codrescu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ES2869865T3 publication Critical patent/ES2869865T3/es
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Image Processing (AREA)
  • Display Devices Of Pinball Game Machines (AREA)
ES17729733T 2016-06-24 2017-06-06 Método y aparato para realizar operaciones de recolección y copia SIMD Active ES2869865T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/192,992 US20170371657A1 (en) 2016-06-24 2016-06-24 Scatter to gather operation
PCT/US2017/036041 WO2017222798A1 (en) 2016-06-24 2017-06-06 Method and apparatus for performing simd gather and copy operations

Publications (1)

Publication Number Publication Date
ES2869865T3 true ES2869865T3 (es) 2021-10-26

Family

ID=59054330

Family Applications (1)

Application Number Title Priority Date Filing Date
ES17729733T Active ES2869865T3 (es) 2016-06-24 2017-06-06 Método y aparato para realizar operaciones de recolección y copia SIMD

Country Status (8)

Country Link
US (1) US20170371657A1 (enExample)
EP (1) EP3475808B1 (enExample)
JP (1) JP7134100B2 (enExample)
KR (1) KR102507275B1 (enExample)
CN (1) CN109313548B (enExample)
ES (1) ES2869865T3 (enExample)
SG (1) SG11201810051VA (enExample)
WO (1) WO2017222798A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10795678B2 (en) * 2018-04-21 2020-10-06 Microsoft Technology Licensing, Llc Matrix vector multiplier with a vector register file comprising a multi-port memory
US10782918B2 (en) * 2018-09-06 2020-09-22 Advanced Micro Devices, Inc. Near-memory data-dependent gather and packing
KR102811045B1 (ko) 2020-03-06 2025-05-21 삼성전자주식회사 데이터 버스, 그것의 데이터 처리 방법 및 데이터 처리 장치
US12443412B2 (en) 2022-01-30 2025-10-14 Simplex Micro, Inc. Method and apparatus for a scalable microprocessor with time counter
US12190116B2 (en) 2022-04-05 2025-01-07 Simplex Micro, Inc. Microprocessor with time count based instruction execution and replay
US12288065B2 (en) 2022-04-29 2025-04-29 Simplex Micro, Inc. Microprocessor with odd and even register sets
US12282772B2 (en) * 2022-07-13 2025-04-22 Simplex Micro, Inc. Vector processor with vector data buffer

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761706A (en) * 1994-11-01 1998-06-02 Cray Research, Inc. Stream buffers for high-performance computer memory system
US5887183A (en) * 1995-01-04 1999-03-23 International Business Machines Corporation Method and system in a data processing system for loading and storing vectors in a plurality of modes
US6513107B1 (en) * 1999-08-17 2003-01-28 Nec Electronics, Inc. Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page
US7484062B2 (en) * 2005-12-22 2009-01-27 International Business Machines Corporation Cache injection semi-synchronous memory copy operation
US7454585B2 (en) * 2005-12-22 2008-11-18 International Business Machines Corporation Efficient and flexible memory copy operation
US8432409B1 (en) * 2005-12-23 2013-04-30 Globalfoundries Inc. Strided block transfer instruction
US8060724B2 (en) * 2008-08-15 2011-11-15 Freescale Semiconductor, Inc. Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
US9218183B2 (en) * 2009-01-30 2015-12-22 Arm Finance Overseas Limited System and method for improving memory transfer
US20120060016A1 (en) * 2010-09-07 2012-03-08 International Business Machines Corporation Vector Loads from Scattered Memory Locations
US8635431B2 (en) * 2010-12-08 2014-01-21 International Business Machines Corporation Vector gather buffer for multiple address vector loads
WO2013180738A1 (en) * 2012-06-02 2013-12-05 Intel Corporation Scatter using index array and finite state machine
US8972697B2 (en) * 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
US10049061B2 (en) * 2012-11-12 2018-08-14 International Business Machines Corporation Active memory device gather, scatter, and filter
US9563425B2 (en) * 2012-11-28 2017-02-07 Intel Corporation Instruction and logic to provide pushing buffer copy and store functionality
JP6253514B2 (ja) * 2014-05-27 2017-12-27 ルネサスエレクトロニクス株式会社 プロセッサ

Also Published As

Publication number Publication date
CN109313548B (zh) 2023-05-26
SG11201810051VA (en) 2019-01-30
KR102507275B1 (ko) 2023-03-06
KR20190020672A (ko) 2019-03-04
WO2017222798A1 (en) 2017-12-28
BR112018076270A8 (pt) 2023-01-31
EP3475808B1 (en) 2021-04-14
BR112018076270A2 (pt) 2019-03-26
US20170371657A1 (en) 2017-12-28
EP3475808A1 (en) 2019-05-01
CN109313548A (zh) 2019-02-05
JP7134100B2 (ja) 2022-09-09
JP2019525294A (ja) 2019-09-05

Similar Documents

Publication Publication Date Title
ES2869865T3 (es) Método y aparato para realizar operaciones de recolección y copia SIMD
TWI697228B (zh) 用於密碼雜湊運算之硬體加速器
US20170083313A1 (en) CONFIGURING COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION IN BLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)
CN109062608B (zh) 用于独立数据上递归计算的向量化的读和写掩码更新指令
US20180121386A1 (en) Super single instruction multiple data (super-simd) for graphics processing unit (gpu) computing
CN108369511A (zh) 用于基于通道的跨步存储操作的指令和逻辑
US20140047218A1 (en) Multi-stage register renaming using dependency removal
JP2013242892A (ja) マイクロプロセッサ内において複数のレジスタユニットからの対応する半語ユニットを結合するための方法及びシステム
EP3326060B1 (en) Mixed-width simd operations having even-element and odd-element operations using register pair for wide data elements
KR20190033084A (ko) 로드 스토어 유닛들을 바이패싱하여 스토어 및 로드 추적
US10942745B2 (en) Fast multi-width instruction issue in parallel slice processor
US8977835B2 (en) Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency
US20170046156A1 (en) Table lookup using simd instructions
JP6911102B2 (ja) アドレス生成時のロード及びストアキューの割り当てのためのシステム及び方法
CN105700855B (zh) 用于改进simd knn实现的设备、方法、系统和机器可读介质
US20190196839A1 (en) System and method for increasing address generation operations per cycle
CN108475242B (zh) 冲突掩码生成
US9747232B2 (en) Data processing device
US20170046160A1 (en) Efficient handling of register files
BR112018076270B1 (pt) Método e aparelho para realizar operações de coleta e cópia simd
HK1260879A1 (en) Method and apparatus for performing simd gather and copy operations
US9501278B2 (en) Method and device for data transmission between register files
US20220365780A1 (en) Inserting a proxy read instruction in an instruction pipeline in a processor
CN121175659A (en) Fetching branch instructions beyond predicted taken in a fetch bundle of a processor-based device