ES2795820B2 - Programmable photonic integrated circuit and related method of operation - Google Patents

Description

DESCRIPTION

PROGRAMMABLE PHOTONIC INTEGRATED CIRCUIT AND OPERATION METHOD

RELATED

OBJECT OF THE INVENTION

The present invention refers to a programmable photonic integrated circuit that comprises at least one programmable photonic module or nucleus, and / or other photonic units as specific high-performance blocks, capable of implementing multipurpose signal processing, through the appropriate programming of its resources. and routing within circuits and blocks to achieve multi-functional operation and selection of its input and output ports. The invention also relates to scalable programmable photonic integrated circuits arranged in a multi-core modular approach to increase the overall system processing power and / or add a multitude of functionalities enabled by complex photonic circuits and parallelization, as well as related methods of operation. .

BACKGROUND OF THE INVENTION

Programmable Multifunctional Photonics (PMP) seeks to design common and multipurpose configurations of integrated optical hardware that can implement a wide variety of functionalities through the appropriate programming of a large set of reconfigurable basic processing units or elements. Various authors have covered theoretical works proposing different configurations and design principles for programmable circuits based on cascade beam splitters or Mach-Zehnder interferometers (MZIs). These proposals offer versatile hardware solutions for implementing programmable circuits, but none of them address the scalability challenges that limit their evolution and practical use.

The performance of programmable multifunctional photonics and its ability to perform complex operations is proportional to the number of tunable units and basic processing elements that can be integrated. These architectures are plagued with similar limitations that embedded electronics face in relation to the number of transistors per chip.

In the case of programmable multipurpose photonic integrated circuits, the experimental demonstrations reported so far are mainly proofs of concept with small-scale integration of tunable elements. Scalability limits arise from: the maximum number of basic units built into the chip, which in turn are limited by the footprint and size of the lattice of the lithography process used, accumulated losses within the circuit and optical interfaces, the ability to interconnect and pack a large number of electronic ports and, finally, the ability to interconnect a large number of optical ports

With regard to accumulated losses, even considering an unlimited number of programmable unit cells, the maximum circuit size will be limited by the loss of optical power due to propagation through the waveguides and components within the processor core.

Regarding the electrical interface, the electrical routing of the control signals imposes a system overhead that consumes a valuable part of the design. In some cases, the distribution of the routing tracks requires an extended redistribution of the optical components over the circuit to ensure the match between the electrical layer on the chip and the optical layer. This creates size problems and limits the final integration density.

It is common to find inefficient programming in large-scale single-core programmable photonic processors when the use of high-performance peripheral building blocks is required. This problem arises when the location of the high-performance building blocks is not optimal for the required functionality and the signal is forced to travel relatively long distances through the core. This introduces additional losses in the circuit and increases the need for resources in the processor, which are used only for internal interconnection purposes.

To mitigate the aforementioned limitations, a solution is required that allows the number of programmable unit cells in the circuit to be scaled.

Multicore processors are well known in the field of electronics, where these architectures revolve around the use of two or more computing units or cores placed in a single processor. The architecture is based on a strategy of "divide and conquer" within a given clock cycle in which when physical limitation presents scaling challenges, a "scaling out" approach is adopted [Add ref., 10.1.1.687.5977, (Venu, 2011) ].

In the field of optical integrated circuits (PICs), some multicore architectures have been proposed, mainly to implement interconnection on chip networks, which in turn are applied to data centers and transceivers. These solutions employ different types of cores: photonic crossover point matrix switches, photonic transmission and selection circuit routers, and wavelength division multiplexing (WDM), and electronic processors.

1. Cross point switches [(A. Shacham, 2007), (Luca Ramini, 2012)]:

This approach is based on connecting cores that implement cross-point switching matrices. Each "basic unit" of this approach is usually composed of ring resonators arranged in a matrix layout, with the basic unit present at each node. Some implementations also include the use of multi-channel waveguide buses that integrate wavelength division multiplexing operation.

2. Broadcast routing and WDM round robin [(T. Alexoudi, 2019), (Martijn Heck, 2014)]:

This approach is based on the use of MUX-DEMUX devices such as the MUX-DEMUX of waveguide arrays and / or signal diffusion trees based on directional couplers or MMI, together with selective units, in the form of semiconductor or resonator optical amplifiers. in ring.

3. Multicore electronic processors assisted by photonic devices

This approach is based on electronic processors interconnected by photonic links. For its implementation, the architecture requires the use of photonic components that make the transition from the electronic domain to the optical domain (modulators) and photodetectors to translate the signal from the optical domain to the electronic domain found in each nucleus. The interconnection between electronic nuclei is carried out by means of a photonic network using different techniques

These approaches have some attributes in common, namely:

to. Photonic nuclei:

1. They are based on application-specific fixed blocks (matrix switchers and / or demultiplexers) generally applied to network routing or optical interconnections (ie, they do not perform optical signal processing tasks).

2. They are based on switches instead of tunable couplers, that is, both cores operate with digital on / off states represented by a 1 or a 0 respectively by programming the switch in the bar state (state 1) or cross (state 0) respectively, while intermediate states between 0 and 1 are not used.

3. They are fixed and rigid in their designs. While both can be used to selectively route the channel to various outputs, they cannot be used to perform any other function or replicate any other circuit on demand. b. Electronic cores:

1. Photonics is only used to assist in the interconnection between electronic nuclei.

2. Photonic, electro-optical and optoelectronic components are required at each interface with the electronic core.

DESCRIPTION OF THE INVENTION

The invention described here solves the scalability and performance problems described above for programmable photonic integrated circuits and enables the design and implementation of scalable programmable photonic integrated circuits through a multicore architecture where two or more programmable photonic cores and / or additional high-performance blocks, they are interconnected to provide a clear technical advantage to current approaches in terms of ease of large-scale circuit fabrication, performance, electrical / optical interconnection, and scalability. In addition, the multi-core modular approach enables fast and efficient configuration of parallel and multi-tasking computation and / or processing operations and the exploitation of their inherent advantages.

The object of the invention is based on the interconnection of cores of multifunctional programmable photonic processors. Each core includes a reconfigurable array of photonic gates arranged in a mesh of optical waveguides.

Each gate is capable of performing basic analog operations on its input optical signals (independently reconfigurable phase shift and optical power division). In addition, each core can include a set of high-performance photonic blocks specifically designed to perform complex photonic and electro-optical operations. The combination and interconnection of the above components / resources defines a single module or kernel. Therefore, and in view of the above, it can be seen that the present object of the invention allows the implementation of one or more simultaneous photonic circuits and / or multi-port linear transformations by means of the adequate programming of its resources, that is to say, of the circuits of each core and the input and output ports.

The invention relates to a programmable photonic integrated circuit comprising:

- at least two photonic blocks, where at least one of the at least two photonic blocks is a programmable photonic nucleus comprising:

i. a reconfigurable optical waveguide mesh array of photonic gates configured to perform optical analog operations;

wherein the at least one programmable photonic core is configured to be programmed and reconfigured to provide signal processing tasks through recursive, non-recursive signal propagation, or combined recursive and non-recursive signal propagation.

Optionally, each of the at least one programmable photonic core further comprises a set of high performance internal photonic blocks configured to perform photonic and electro-optical operations.

Optionally, each of the at least one programmable photonic core further comprises optical I / O ports, wherein each of the at least one programmable photonic core is connected to at least one programmable photonic core through the I / O ports. opticians.

Optionally, each of the at least one programmable photonic core further comprises a set of high performance transition photonic blocks configured to perform photonic and electro-optical operations and furthermore to be connected to the optical I / O ports.

Optionally, each of the at least one programmable photonic core is combined with a communication network configured to route the optical signals from each of the at least one programmable photonic core.

Optionally, each of the at least one programmable photonic nucleus is connected to an adjacent programmable photonic nucleus.

Optionally, each of the at least one programmable photonic core further comprises an auxiliary switching or routing layer.

Optionally, each of the at least one programmable photonic nucleus is connected to a non-adjacent programmable photonic nucleus.

Optionally, each of the at least one programmable photonic core is directly connected through at least one optical I / O port to a distribution network.

Optionally, the distribution network connecting at least one programmable photonic core is configured to distribute dedicated routing blocks in each programmable photonic core.

Optionally, the distribution network connecting the at least one programmable photonic core is configured to distribute dedicated routing blocks in a centralized subsystem.

Optionally, the at least one programmable photonic nucleus is distributed over a two-dimensional layer.

Optionally, the at least one programmable photonic core is distributed over three-dimensional stacked layers, each layer comprising a programmable photonic core.

Optionally, the at least one programmable photonic core is distributed over three-dimensional stacked layers, each layer comprising at least one programmable photonic core.

Optionally, the programmable photonic integrated circuit further comprises optical connectors or couplers configured to allow an interconnection between the at least one programmable photonic core of the layer or layers.

Optionally, the programmable photonic integrated circuit further comprises an integrated platform in which the photonic nuclei are physically interconnected.

Optionally, the at least one photonic nuclei are optically and electrically connected.

Optionally, the programmable photonic integrated circuit further comprises at least one optical power monitor to which at least one programmable photonic core is connected.

Optionally, the programmable photonic integrated circuit also comprises blocks oriented to applications such as sensors, detectors, antennas, measurement blocks, transmission, electronic integrated circuits selected from DAC or ADC, controllers, monitors and / or amplifiers to which the at least one of the programmable cores is connected.

Optionally, the programmable photonic integrated circuit further comprises an electrical subsystem that drives actuators or on-chip actuators / receivers, an electrical subsystem that monitors optoelectronic readings, and an electronic processor or microprocessor that executes the optimization and configuration programs.

Optionally, the programmable photonic integrated circuit further comprises a control plane and / or a software layer distributed over different subsystems that is configured to control the at least one programmable photonic core.

Optionally, the programmable photonic integrated circuit further comprises a control plane and / or an aggregated software layer in a single system that is configured to control the at least one programmable photonic core.

Optionally, each of the at least one programmable photon nucleus is connected to multiple adjacent programmable photonic nuclei.

Optionally, the communication network is a dedicated communication network configured to route the optical signals from each of the at least one core. programmable photonic.

Optionally, the communication network is a dedicated communication network configured to allow interconnection of the programmable photonic core with another non-adjacent programmable photonic core through the auxiliary switching or routing layer.

Optionally, the programmable photonic integrated circuit is implemented and integrated on a chip.

Optionally, the chip follows a homogeneous PIC integration in which the at least one programmable photonic nucleus is integrated into the same substrate.

Optionally, the chip follows a heterogeneous PIC integration in which the at least one programmable photonic core is integrated into the same substrate.

Optionally, the chip follows an on-board integration approach (chiplet type) in which a common substrate or common platform is used to apply a plug-and-play connection to design the at least one. programmable photonic core based on a desired performance of a processor.

The invention further relates to a method for operating the programmable photonic integrated circuit described above, in which the method comprises connecting and using the at least one programmable photonic nucleus so that a signal from a programmable photonic nucleus enters at least another programmable photonic nucleus, in a particular sequence where the programmable photonic integrated circuit progresses in series.

Optionally, the method comprises connecting and using the at least one programmable photonic nucleus so that a signal from a programmable photonic nucleus enters at least one other programmable photonic nucleus following a particular sequence where the programmable photonic integrated circuit divides and processes the signals on the at least one programmable photonic nucleus before combining it into a different programmable photonic nucleus.

Optionally, the method comprises programming the at least one programmable photonic nucleus to perform independent tasks at the same time, operating in parallel.

The proposed photonic architecture based on the programmable photonic integrated circuit of the invention dramatically increases the number of advantages inherent in field programmable photonic hardware approaches, which are expanded by the circuit topologies introduced by the invention. These include:

• Scalability of multipurpose programmable photonic circuits.

• Shorter production and marketing times.

• Lower non-recurring engineering and prototype development costs. • • Financial risk reduction by developing ideas and translating them into ASPIC. • • Multifunctional and multitasking operation.

• • Circuit optimization.

• • Regular designs and reduced space.

• • Better performance and reproducibility of programmable photonic analog blocks.

• • Greater number of alternative circuit topologies not constrained by geometric factors.

• • Programming of more complex and versatile circuits. Increased number of ports, that is, inputs and outputs

• • Improved functionality

• • Improved electrical and optical interface.

• • Better performance when programming larger and more complex circuits.

• • Reduction and mitigation of optical crosstalk and tuning crosstalk.

• • Future scalability with lower design and verification costs.

The programmable photonic integrated circuit proposed in the invention is suitable for the following applications:

• Aerospace and defense sectors (avionics, communications, secure solutions, space)

• Automotive sector (high resolution video, image processing, vehicle connectivity and networks, infotainment)

• Data centers (servers, routers, switches, gateways) • High performance computing (servers, super computers, SIGINT systems, RADAR, beamforming systems, quantum computing, neural networks)

• Design of photonic integrated circuits (ASPIC prototyping, hardware emulation)

• Wired and wireless communications (optical transport networks, 5G network processing connectivity interfaces, mobile backhaul)

• Hardware accelerators.

• Deep and machine learning applications.

• Artificial intelligence

• Smart transceivers.

• Quantum photonic processors

Thus, the technical innovation proposed in this invention includes the architectures along with the workflows and control protocols of multicore programmable photonic integrated processors that allow large-scale integration of programmable processing cells and can exploit the parallelization of multiple tasks. At the same time, it provides a significant performance improvement compared to current architectures. It achieves an improvement in functionality with respect to several factors, including but not limited to scalability, performance, and multitasking efficiency.

The photonic cores of the present invention are not mere programmable interconnect subsystems that cannot be reconfigured to provide signal processing tasks through non-recursive or recursive signal propagation. Therefore, these cores take advantage of the additional degree of freedom that is independent of the application. The overall device here can be defined in this way as a reconfigurable network of reconfigurable signal processing cores.

DESCRIPTION OF THE FIGURES

In order to complement the description that is made and in order to help better understand the characteristics of the invention, according to a preferred practical embodiment thereof, said description is accompanied, as an integral part thereof, by a set of figures where, in an illustrative and non-limiting way, the following has been represented:

Figure 1 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention, where the illustration shows an example of multicore processor implementation with unlimited interconnection.

Figure 2 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention.

Figure 3 shows non-limiting examples of schematic diagrams of the proposed photonic architecture of the invention.

Figure 4 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention.

Figure 5 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention.

Figure 6 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention.

Figure 7 (left) shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention. Figure 7 (right) shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention.

Figure 8 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention.

PREFERRED EMBODIMENT OF THE INVENTION

In a preferred embodiment of the object of the invention, a device is considered as shown in Figure 1 where a set of at least two, but preferably a larger amount of multipurpose programmable photonic circuits are added and connected in modules or cores, where each Programmable photonic IC core or module is used in conjunction with other programmable photonic circuits, or additional functional blocks which may be high performance blocks, specific functionality blocks or other similar units. These blocks have programmable features and perform optical signal processing on a photonic chip.

It should be noted that the design of Figure 1 does not assume any particular interconnection geometry or topology for the multipurpose programmable photonic circuit present in each core or module and that the resulting design shown there is for illustrative purposes only. Although various sub-core architectures can be considered, here we illustrate the design with a very basic hexagonal waveguide mesh connected to a set of 8 high-performance building blocks and high-performance transition blocks. Figures 1-3 show examples of possible interconnect and architecture options, but are not limited to just these examples. In particular, the schematic of such a multipurpose multicore programmable photonic processor is shown in Figure 1 for a particular multicore processor with unconstrained interconnect architecture. In this architecture, each processing core is connected to up to 4 neighboring cores through its optical I / O ports. The replication and interconnection of this module with its neighboring cores leads to a simple processing network that is characterized by its simplicity, scalability, low design costs and versatility. Some design variations may incorporate high-performance building blocks placed on the optical interface to perform specific functions including, but not limited to, optical signal amplification and non-linear operations. In some cases, it is beneficial to access the cores without the need to directly access their internal resources or have hardware that can support both as required through control software. Figure 2 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention, where the illustration shows an implementation example of an implementation of a multicore processor with distributed interconnection. In this architecture, each processing core is combined with a communication network that routes the optical signals from each modular core. The replication and interconnection of this module with its neighboring cores leads to an on-chip processing and communication network characterized by its efficiency, scalability, low design cost and versatility. This architecture works in a similar way to the field programmable photonic gate array architecture, where the user has access to large amounts of general processing resources. As in the previous approach, the design does not have a centralized resource that can become larger and more complicated as the number of cores increases. Therefore, the complexity of the design and the complexity of the verification are independent of the number of cores.

The above two approaches do not allow direct interconnection of cores that are not adjacent to each other. Figure 3 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention, where the illustration shows an example of implementation of a multicore processor with centralized interconnection. This scheme allows the interconnection of a given core with other non-neighboring cores using an auxiliary switching / routing layer. This design is interesting in multicore processors with a reduced number of cores, but the price that must be paid translates into scalability issues and additional verification and customization requirements for each hardware update.

By properly programming each core or module, the multipurpose multi-core programmable photonic processor can implement complex photonic circuits either autonomous and / or in parallel, as well as signal processing transformers by decomposing different optical processing circuits into different programmable photonic processor modules. and interconnecting them afterwards. The goal then is to achieve a functional advantage brought by the modular approach and increase performance, scalability, versatility and add new superior processing capabilities.

In particular, the invention is illustrated in Figures 4-6, where it is shown how complex optical signal processing circuits can be configured by programming the proposed device. In particular, we show how the multicore processor with unlimited interconnect architecture programs a complex circuit distributed over 4 cores, the ability to add sections of the circuit working in parallel, and the ability to perform independent multitasking operations.

The multipurpose multi-core programmable photonic processor combines the programmability of basic programmable photonic processors into a scalable interconnect structure, enabling programmable circuits with scalable processing capabilities and with additional functionality such as enhanced circuit parallelization. Therefore, the complexity of the processing derives from interconnectivity internal to the core and between cores. In addition, it solves the main problems related to the scalability of programmable photonic circuits, where increasing the density of its programmable unit cells has the cost of introducing adverse effects such as optical crosstalk, tuning crosstalk, non-scalable electrical and optical interface, and limited footprint in manufacturing processes. Multicore programmable photonic processor architectures include the interconnection of several general-purpose cores and emerge as an elegant solution to scale the performance of conventional photonic processors Since the scalability limits of single-core processors are exacerbated when a With the largest number of programmable unit cells in the circuit, a straightforward approach is to use an architecture that integrates and interconnects several smaller cores.

Control of this entire device, including all interconnected blocks, can be accomplished using individual software to control each core, or it can be added to a software interface leading to a common means of driving, programming, controlling, and reconfiguring all hardware. A common software allows intelligent programming and management of resources to achieve optimal configurations in terms of number of components used, power consumption, programming efficiency, mitigation of side effects (optical and tuning crosstalk).

EXAMPLES OF OPERATION

The disaggregated nature of multicore photonic processors allows for a broad set of modes of operation. In this section we illustrate some non-limiting examples:

Figure 4 shows a diagram of Progressive Programming in series of distributed circuits (Serialization) where the illustration shows an example of configuration of a Multicore processor with non-limited interconnection where a complex circuit is programmed on 4 cores following a series arrangement. The circuit includes ring resonator programming (in the first core), dispersive delay in a high-performance building block, optical amplifier in a transition HPB, (in the second core) an optical splitter, a formation network of beams, (in the third core) a sixth order finite impulse response filter and (in the fourth core) a branch with an optical attenuator implemented by a high performance building block and a branch with a high quality factor filter Q and a polarization filter. The complex photonic circuit configuration in a single-core processor is limited by the number of optical ports, programmable unit cells, and high-performance blocks available in the circuit. Also, the accumulation of non-ideal effects (optical and crosstalk during phase adjustment) and the large number of programmable unit cells required to perform complex operations could quickly limit the circuitry that the inner core can implement. Figure 4 illustrates how the multicore architecture divides and distributes the circuit over the cores. The programmed circuit is not intended for any application and is simply configured to highlight the main capabilities of this mode of operation. In this case, the first core (top left) configures an optical ring resonator in the inner core, accesses a dispersive delay provided by the HPB 7, and amplifies the optical signal before connecting to the next core. The next core (top right) splits the optical signal into two paths. The first path feeds a programmed optical beamformer, demonstrating the benefits of the multi-core approach for circuits that require multiple paths and optical ports. The other route goes to the interconnected exit to access the third core. The third core (bottom right) implements an optical lattice filter in its core based on three unbalanced MZIs and routes the two filter outputs to the next and last core. The last core (bottom left) distributes one of the optical interconnects to an optical attenuator and the other optical connection to a cascade of an HPB filter and a polarization filter, respectively.

Figure 5 shows a programming scheme of circuits distributed in parallel (Parallelization) where the illustration shows an example of the configuration of a Multicore processor with unlimited interconnection where a complex circuit is programmed on 4 cores following a parallel configuration. The circuit includes programming the Mach-Zehnder modulator (upper left core), an optical splitter and an optical amplifier, (upper right core) an optical filter with two outputs, (lower left core) an optical filter based on an MZI and four ring resonators and (lower right core) a combiner and a photodetector. Some circuits include divisions of circuits into blocks that run in parallel. Although possible on single-core processors, the programming of these circuits can be limited when programmed on a single core individually. In this case, interference between branches of the circuit running in parallel can reduce overall processing performance. To mitigate this effect, multicore architectures can distribute sections of the same circuit that run in parallel over different processing cores. Figure 5 illustrates the programming of a circuit distributed in 4 cores. The first core (top left) gets the input signal and accesses an MZI modulator before splitting and routing it to the second (top right) and the third nucleus (bottom left). Each core contains a different optical filter. In the first case, it is a third order ring resonator architecture that extracts the passband and feeds it to the fourth core (bottom right) and the stop band or reflection response to an external port. The second case (bottom left) is an optical filter that combines lattice filters and optical ring resonators before directing the two output ports to the fourth core. The last nucleus (lower right) receives the signal from two different nuclei. The signal coming from the lower left core is detected by a high speed photodiode block. The second signal from the lower left core is combined with the optical signal from the upper right core before accessing the optical output port.

Figure 6 shows a programming scheme of independent circuits (multitasking), where the illustration shows an example of configuration of a Multicore processor with unlimited interconnection where two independent complex circuits are programmed on 4 cores implementing a multitasking operation. The circuit includes a cascade of two unit blocks with a non-linear intermediate section (upper cores) and another cascade of a 4-ring filtering section in an array followed by a 4x4 multiport interferometer. The last key advantage of multicore photonic processors lies in their ability to perform independent tasks at the same time. This capability can also be exploited in single-core processors, but additional optimization techniques are required to mitigate crosstalk between the two circuits. In short, the processor programs two or more circuits that run in parallel and perform independent tasks. The circuits can be of the same design or totally different. Additionally, the circuits can be distributed across different cores or can be programmed to share some of the available resources in the same core for cases including, but not limited to, demanding applications. Figure 6 illustrates an example where the multicore architecture programs two independent circuits. The upper cores configure a 6-mode two-layer neural network. The cores located at the bottom of the processor set up an initial filtering stage before accessing a 4x4 interferometer followed by a non-linear matrix.

PHYSICAL IMPLEMENTATION

The physical implementation of the PROGRAMMABLE MULTI-PURPOSE PHOTONIC PROCESSOR requires an integrated optical approach, either based on a silicon photonics platform and / or a hybrid / heterogeneous III-V, and / or group IIV-Vs and / or barium titanate and / or any other chalcogenide and / or platform II-VI. It is not only limited to the integration of programmable photonic integrated circuits with other integrated circuits and / or photonic blocks, but also with electronic integrated circuits and back blocks of this nature.

Regarding the programmable photonic blocks, the photonic technology options currently available are based on any phase or amplitude tuning effect such as: MEMS, thermo-optic, electro-optic, opto-mechanical effects, electro-capacitive effects or non-volatile phase actuators. These phase shifters and actuators are integrated into any interferometric structure with two or more ports

For its physical implementation, different possibilities of architectures and integration approaches are considered, which can be classified as follows:

ARCHITECTURES:

Heterogeneous architectures: Although one of the key benefits of multicore architectures is the replication of the same drive core, the range of applications can be expanded if each core employs different HPBs as well as inner core topologies. As an illustrative example, Figure 7 (a) shows an example configuration of a Multicore processor with unconstrained interconnection implementing a heterogeneous architecture where 4 cores have a different internal composition. In particular, each core includes a set of high-performance processing blocks and a different waveguide mesh arrangement (hexagonal, triangular, square, and lead). That is, it is a 4-core architecture with different internal cores for each module: hexagonal mesh architecture, triangular mesh architecture, square mesh architecture, and a rectangular multiport interferometer. Note also that each one can integrate different HPBs. The key advantage of this implementation resides in the availability of specific resources required by some applications. For example, the forward feed mesh illustrated in the lower right core can be implemented by the hexagonal mesh, but in a less efficient manner.

2D architectures: 2D architectures can be implemented considering current PIC standards and their integration. 2D architectures would most commonly be found in the form of connecting from one chip to another in the photonic equivalent of making a "short" by connecting optical fibers or waveguides coming out of different chips. This can be done with a singular package of different photonic chips on the same or different integration platforms.

3D architectures (single-core and multi-core): Figure 7 (b) shows a 3D architecture with 4 cores, each connected to its neighbors by vertical interconnections. That is, it is a multicore processor with programming without interconnection limitations in which cascaded circuits are programmed in a form of 3D integration. Connections between the cores are made by waveguide couplers designed to couple light in the vertical direction to an upper / lower layer of waveguides.

Stacking 3D architectures are based on placing multiple cores in a 3D design (as shown in Fig. 7) to improve performance relative to processing power. Single-core designs have scalability limited by the lattice size of the fabrication tools. Post-assembly of such a core can be done by individually stacking layers to form multiple cores and thus exceed those limits, but then the form factor is compromised. A solution in which the form factor can be drastically reduced while showing an increase Multiple in performance is 3D stacking whereby such cores are arranged in stacks of layers placed one on top of the other with interconnections running through each to form a larger and functionally more powerful unit. Stacking can be configured in parallel to aid parallel processing, giving the ability to perform functionality in parallel. A mixed 2D and 3D multicore architecture can also be implemented.

LEVEL OF INTEGRATION:

On-chip integration: On-chip integration implies that the photonic nucleus is connected to neighboring nuclei or additional functional blocks with the nucleus and elements on the same substrate. On-chip integration can be accomplished using a multitude of approaches, the most common of which are listed below:

Homogeneous PIC Integration - In this approach, all cores are made in the same build round on a single PIC die. Multiple cores can be implemented using this approach and the key advantage of smooth integration comes from the very small form factor that can be achieved. Single-core implementation in programmable PICs is limited by the strict geometric constraints presented by the size of the lattice. In this approach as presented in the present invention, a non-limiting example is a multicore processor formed by manufacturing the same core through a single wafer and with one or more cores being defined as the unit manufactured in a lattice. All or some of the different segments of the wafer with the core (s) defined in a lattice are left interconnected, that is, the different dies are not cut, but are left as a conglomerate interconnection of multiple dies with cores to give rise to a multi-core processor where all cores are defined and configured purely during manufacturing, eliminating the need to interconnect the different cores during packaging. This approach then relaxes the demands on PIC packaging, increases performance, and makes hardware realization easier through a simpler process flow.

Heterogeneous integration of PICs: Heterogeneous PICs are based on the integration of two or more different materials on the same chip substrate. The most common executions of this approach can be seen with InP active devices integrated with small form factor SOI circuits or with the low loss SiN platform, but can even be extended to other materials such as barium titanate (BTO), graphene, chalcogenides, etc. The photon gain medium does not exist in pure SOI or SiN technology circuits, so this approach adds a great deal of functionality, including but not limited to on-chip laser integration, as well as gain elements that, in turn, they can help achieve multi-core multi-architectures. The implementation itself relies on a thin layer of InP or other III-V material "sticking" in specific sections, on top of an SOI or SiN chip. The light, in these sections, is evanescently coupled from the guides of SOI or SiN waveforms to InP sections to induce gain or as efficient phase modulation sections. The process of "bonding" is carried out via means such as BCB or other polymers by wafer bonding techniques or may involve other means such as micro-transfer printing.

•

• On- board integration ( chiplet type): the basis of this implementation is to divide the chip design (co-design) and the manufacturing considering its basic function that can come, for example, in the form of functional subsystem blocks such as the core, active blocks such as lasers and half gain, non-linear blocks, etc. Once these blocks have been manufactured and the subassembly made (individual chip packaging), they will be placed on a platform that is an interlaced substrate and then packaged in a single unit. Chiplets address the drawback that there is no one-size-fits-all approach to making the ones needed to meet today's needs. This implementation is not only limited to the aggregation of multipurpose photonic blocks and / or other high performance photonic blocks, but can also include pure electronic blocks including but not limited to controllers, monitors, ADCs, DACs, amplifiers, sensors and antennas.

Figure 8 shows a non-limiting example of a schematic diagram of the proposed photonic architecture of the invention, where the illustration shows an example of implementation of a MULTI-PURPOSE PROGRAMMABLE PHOTONIC PROCESSOR in a design that contains multiple cores and where each core can be connected in plug-and-play mode or following a chiplet-like approach whereby a common platform shown in green is used to interconnect two or more programmable photonic blocks with other programmable photonic blocks or functional units. All of these units are represented in the schematic as black boxes as they can include two or more programmable PICs and / or high performance photonic building blocks that can be expanded to include pure electronic ICs such as controllers, monitors, ADCs, DACs, sensors. , antennas, etc.

In addition, all of the above implementations may employ a power and control subsystem to allow control and operation of the multipurpose multi-core programmable photonic processor. Control and driving circuits allow extraction and reading of optical signals and activation of photonic actuators

Claims (32)

1. A programmable photonic integrated circuit comprising: - at least two photonic blocks, where at least one of the at least two photonic blocks is a programmable photonic nucleus comprising: i. a reconfigurable optical waveguide mesh array of photonic gates configured to perform optical analog operations; wherein the at least one programmable photonic core is configured to be programmed and reconfigured to provide signal processing tasks through recursive, non-recursive signal propagation, or combined recursive and non-recursive signal propagation. The programmable photonic integrated circuit according to claim 1, wherein each of the at least one programmable photonic core further comprises a set of high performance internal photonic blocks configured to perform photonic and electro-optical operations. The programmable photonic integrated circuit according to claim 1, wherein each of the at least one programmable photonic core further comprises optical I / O ports, wherein each of the at least one programmable photonic core is connected to at least one programmable photonic core through the optical I / O ports. The programmable photonic integrated circuit according to claim 3, wherein each of the at least one programmable photonic core further comprises a set of high performance transition photonic blocks configured to perform photonic and electro-optical operations and furthermore to be connected to the optical I / O ports. The programmable photonic integrated circuit according to claim 1, wherein each of the at least one programmable photonic core is combined with a communication network configured to route the optical signals from each of the at least one programmable photonic core. 6. The programmable photonic integrated circuit according to any of the claims above 4 or 5, wherein each of the at least one programmable photonic nucleus is connected to an adjacent programmable photonic nucleus. The programmable photonic integrated circuit according to claim 1, wherein each of the at least one programmable photonic core further comprises an auxiliary switching or routing layer. The programmable photonic integrated circuit according to claim 7, wherein each of the at least one programmable photonic nucleus is connected to a non-adjacent programmable photonic nucleus. The programmable photonic integrated circuit according to any one of claims 3 or 4, wherein each of the at least one programmable photonic core is directly connected through at least one optical I / O port to a network of distribution. The programmable photonic integrated circuit according to claim 9, wherein the distribution network connecting at least one programmable photonic core is configured to distribute dedicated routing blocks in each programmable photonic core. The programmable photonic integrated circuit according to claim 9, wherein the distribution network connecting the at least one programmable photonic core is configured to distribute dedicated routing blocks in a centralized subsystem. The programmable photonic integrated circuit according to claim 1, wherein the at least one programmable photonic core is distributed over a two-dimensional layer. The programmable photonic integrated circuit according to claim 1, wherein the at least one programmable photonic core is distributed over stacked three-dimensional layers, each layer comprising a programmable photonic core. The programmable photonic integrated circuit according to claim 1, wherein the at least one programmable photonic core is distributed over stacked three-dimensional layers, each layer comprising at least one programmable photonic core. The programmable photonic integrated circuit according to any of claims 12 to 14, further comprising optical connectors or couplers configured to allow an interconnection between the at least one programmable photonic core of the layer or layers. The programmable photonic integrated circuit according to claim 1, further comprising an integrated platform in which the photonic nuclei are physically interconnected. The programmable photonic integrated circuit according to claim 1, wherein the at least one photonic nuclei are optically and electrically connected. The programmable photonic integrated circuit according to claim 1, further comprising at least one optical power monitor to which at least one programmable photonic core is connected. 19. The programmable photonic integrated circuit according to claim 1, further comprising blocks oriented to applications such as sensors, detectors, antennas, measurement, transmission blocks, electronic integrated circuits selected from DAC or ADC, controllers, monitors and / or amplifiers to which the at least one of the programmable cores is connected. The programmable photonic integrated circuit according to claim 1, further comprising an electrical subsystem that drives actuators or on-chip actuators / receivers, an electrical subsystem that monitors optoelectronic readings, and an electronic processor or microprocessor that executes optimization programs. and configuration. 21. The programmable photonic integrated circuit according to claim 1, further comprising a control plane and / or a software layer distributed over different subsystems that is configured to control the at least one programmable photonic core. 22. The programmable photonic integrated circuit according to claim 1, further comprising a control plane and / or an aggregated software layer in a single system that is configured to control the at least one programmable photonic core. 23. The programmable photonic integrated circuit according to claim 1, wherein each of the at least one programmable photonic nucleus is connected to multiple adjacent programmable photonic nuclei. 24. The programmable photonic integrated circuit according to claim 5, wherein the communication network is a dedicated communication network configured to route the optical signals from each of the at least one programmable photonic core. 25. The programmable photonic integrated circuit according to claims 5 and 7, wherein the communication network is a dedicated communication network configured to allow interconnection of the programmable photonic nucleus with another non-adjacent programmable photonic nucleus through the auxiliary layer of switching or routing. 26. The programmable photonic integrated circuit according to claim 1, which is implemented and integrated on a chip. 27. The programmable photonic integrated circuit according to claim 26, wherein the chip follows a homogeneous PIC integration in which the at least one programmable photonic nucleus is integrated into the same substrate. 28. The programmable photonic integrated circuit according to claim 26, wherein the chip follows a heterogeneous PIC integration in which the at least one programmable photonic core is integrated into the same substrate. 29. The programmable photonic integrated circuit according to claim 26, wherein the chip follows an on-board integration approach (chiplet type) in which a common substrate or a common platform is used to apply a plug-and-socket connection. play to design the at least one. programmable photonic core based on a desired performance of a processor. 30. A method for operating the programmable photonic integrated circuit of any of the preceding claims, wherein the method comprises connecting and using the at least one programmable photonic nucleus so that a signal from one programmable photonic nucleus enters at least one other programmable photonic nucleus, in a particular sequence where the programmable photonic integrated circuit progresses in series. 31.

A method of operating the programmable photonic integrated circuit of any of claims 1 to 29, wherein the method comprises connecting and using the at least one programmable photonic nucleus so that a signal from a programmable photonic nucleus enters at least one other nucleus. Programmable photonic following a particular sequence where the programmable photonic integrated circuit splits and processes the signals on the at least one programmable photonic nucleus before combining them into a different programmable photonic nucleus. 32. A method for operating the programmable photonic integrated circuit of any of claims 1 to 29, wherein the method comprises programming the at least one programmable photonic core to perform independent tasks at the same time, operating in parallel.