ES2447216A1

ES2447216A1 - High speed electricity storage device for loading and unloading (Machine-translation by Google Translate, not legally binding)

Info

Publication number: ES2447216A1
Application number: ES201200881A
Authority: ES
Inventors: Javier Luis LÓPEZ SEGURA
Original assignee: Individual
Current assignee: Individual
Priority date: 2012-09-11
Filing date: 2012-09-11
Publication date: 2014-03-11
Anticipated expiration: 2032-09-11
Also published as: ES2447216B1

Abstract

High-speed loading and unloading electricity storage device, comprising: - two capacitors (10, 10 ') formed by positive (1) and negative (2) conductive horizontal sheets connected respectively to vertical positive (5) and negative (6) electrodes, the capacitors arranged so that the positive vertical electrodes (5) ) of one capacitor are faced with the negative vertical electrodes (6) of the other capacitor; - a dielectric sheet (11) between both capacitors; - a distributor (15) for connecting positive electrodes (5) and negative electrodes (6) so that they can be soldered to a printed circuit. This device assumes a new type of capacitor with a minimum inductance and that can charge and discharge electrical energy at a higher frequency than current capacitors. (Machine-translation by Google Translate, not legally binding)

Description

DISPOSITIVO DE ALMACENAMIENTO DE ELECTRICIDAD DE ALTA VELOCIDAD DE CARGA Y DESCARGA HIGH SPEED CHARGING AND DISCHARGE ELECTRICITY STORAGE DEVICE

OBJECT OF THE INVENTION

5 La presente invención se refiere a un dispositivo de almacenamiento de energía de alta velocidad. The present invention relates to a high speed energy storage device.

STATE OF THE TECHNIQUE

Actualmente existen numerosos dispositivos de almacenamiento de energía eléctrica, There are currently numerous electrical energy storage devices,

10 la presente patente se refiere a sistemas de almacenamiento electrostático, en adelante llamaremos condensadores. En numerosas ocasiones los condensadores son cargados y descargados a muy alta frecuencia, produciéndose resonancias internas lo cual produce oscilaciones que no pueden ser filtradas. Las oscilaciones internas se trasmiten fuera produciendo un ruido 10 This patent refers to electrostatic storage systems, hereinafter we will call capacitors. On many occasions the capacitors are charged and discharged at a very high frequency, producing internal resonances which produces oscillations that cannot be filtered. Internal oscillations are transmitted outside producing a noise

15 en los circuitos electrónicos que hay conectados al condensador. La resonancia interna se debe a la presencia de inductancia parásita dentro del condensador y que no puede ser eliminada desde fuera del condensador. La duración de la señal generada es inversamente proporcional a la impedancia del 15 in the electronic circuits that are connected to the capacitor. The internal resonance is due to the presence of parasitic inductance inside the capacitor and cannot be removed from outside the capacitor. The duration of the generated signal is inversely proportional to the impedance of the

condensador, la cual es L / C , siendo C la capacidad del condensador y L la 20 inductancia parásita. A menor inductancia parásita antes se amortigua la oscilación. Es necesario por tanto reducir la inductancia parásita al mínimo posible. Los condensadores almacenan su energía en sándwiches de láminas paralelas conductoras positivas 1 y negativas 2 separadas por láminas de material aislante 3, desde ahora llamaremos dieléctrico (ver Figura 1). capacitor, which is L / C, where C is the capacitor's capacity and L is the parasitic inductance. A lower parasitic inductance before the oscillation is damped. It is therefore necessary to reduce the parasitic inductance to the minimum possible. The capacitors store their energy in sandwiches of parallel conductive plates positive 1 and negative 2 separated by sheets of insulating material 3, from now on we will call dielectric (see Figure 1).

25 La inductancia parásita L de estas láminas viene dada por la ecuación: L=U*H*T/A siendo U la constante de permeabilidad eléctrica, H la distancia entre láminas conductoras positiva 1 y negativa 2, T la longitud del condensador y A el ancho del 25 The parasitic inductance L of these sheets is given by the equation: L = U * H * T / A where U is the constant of electrical permeability, H the distance between positive conductive sheets 1 and negative 2, T the capacitor length and A the width of

mismo. Por tanto para reducir la inductancia al mínimo hay que reducir la longitud T, same. Therefore, to reduce the inductance to a minimum, the length T must be reduced,

30 incrementar el ancho A y reducir la distancia entre láminas H al mínimo. Dicho de forma sencilla, tal y como puede verse en la Figura 2 cada carga Q que sale del condensador en una dirección tiene que tener otra carga Q viajando en sentido opuesto lo más cerca posible entre sí entrando en dicho condensador, siendo asimismo la longitud del camino lo más corta posible. 30 increase the width A and reduce the distance between sheets H to a minimum. Simply stated, as can be seen in Figure 2, each load Q leaving the capacitor in one direction must have another charge Q traveling in the opposite direction as possible from each other entering said capacitor, the length of the path as short as possible.

35 Existe una tecnología que es la llamada quot;IDCquot; en la cual cada lámina horizontal tiene numerosas pestañas (4,4’). Las pestañas 4 de las láminas positivas 1 se sitúan encima una de la otra y las pestañas 4’ de las láminas negativas 2 también pero alternadas con las anteriores, tal y como aparece en la Figura 3a. Entre láminas positivas 1 y negativas 2 se ponen láminas dieléctricas 3. 35 There is a technology called "IDCquot; in which each horizontal sheet has numerous tabs (4.4 ’). The tabs 4 of the positive sheets 1 are placed on top of each other and the tabs 4 'of the negative sheets 2 also but alternated with the previous ones, as shown in Figure 3a. Between positive 1 and negative 2 sheets, dielectric sheets 3 are placed.

5 Al salir una carga Q por la pestaña 4 de una lámina positiva 1, una carga Q entra por una pestaña 4’ de la lámina negativa 2 adyacente, cumpliéndose que la distancia D (en la dimensión de anchura) entre carga Q saliente y carga Q entrante es el ancho A del condensador dividido por el número de pestañas, tal y como aparece en la Figura 3b. 5 When a load Q exits the flange 4 of a positive sheet 1, a charge Q enters through a flange 4 'of the adjacent negative sheet 2, provided that the distance D (in the width dimension) between the outgoing load Q and load Incoming Q is the width A of the condenser divided by the number of tabs, as shown in Figure 3b.

10 Como puede verse en la Figura 3c, uniendo las láminas positivas 1 bajan unos electrodos verticales positivos 5 y análogamente bajan electrodos negativos 6 uniendo láminas negativas 2. Estos electrodos (5,6) bajan no solo por la cara frontal sino que además lo hace por la cara posterior tal y como aparece en la Figura 3d. Hay otros diseños que hacen 10 As can be seen in Figure 3c, joining the positive plates 1 lower positive vertical electrodes 5 and similarly lower negative electrodes 6 joining negative plates 2. These electrodes (5,6) descend not only on the front face but also do on the back side as it appears in Figure 3d. There are other designs that make

15 variaciones de esta tecnología que compensan muy bien la inductancia de las láminas horizontales pero sin embargo no compensan adecuadamente la inductancia de los electrodos. Hay además otro efecto no deseado y es que la impedancia de las láminas 15 variations of this technology that compensate very well for the inductance of the horizontal blades but nevertheless do not adequately compensate for the inductance of the electrodes. There is also another unwanted effect and that is the impedance of the sheets

horizontales, L / C , es muy baja al ser muy pequeña la distancia entre láminas H. 20 Sin embargo la impedancia entre electrodos (5,6) es mucho mayor puesto que su inductancia, que depende de la distancia D entre electrodos, es mucho mayor. Al ser la diferencia entre las impedancias de las láminas horizontales y las impedancias de los electrodos muy grande, durante una descarga brusca aparecen oscilaciones. Es muy común ver con un osciloscopio unos picos muy altos de muy alta frecuencia entre 25 bornes de un condensador. horizontal, L / C, the distance between sheets H. is very small, however the impedance between electrodes (5,6) is much greater since its inductance, which depends on the distance D between electrodes, is much greater. Being the difference between the impedances of the horizontal blades and the impedances of the electrodes very large, during an abrupt discharge oscillations appear. It is very common to see very high peaks of very high frequency between 25 terminals of a capacitor with an oscilloscope.

DESCRIPTION OF THE INVENTION

La presente invención busca resolver los inconvenientes expuestos anteriormente mediante la compensación de la inductancia de los electrodos o líneas descendientes. 30 Un aspecto de la presente invención consiste en construir dos condensadores (10,10’) como el de la Figura 4a (en la cual por simplificar la figura no aparecen representados las láminas aislantes) y unir ambos tal y como aparece en la Figura 4b por el lado de los electrodos con una lámina de dieléctrico 11 en medio, de modo que los electrodos positivos 5 del primer condensador 10 se encuentran en frente sin tocarlo con el 35 correspondiente electrodo negativo 6 del segundo condensador 10’ separados por el The present invention seeks to solve the problems set forth above by compensating the inductance of the electrodes or descending lines. One aspect of the present invention consists in constructing two capacitors (10,10 ') such as that of Figure 4a (in which the insulating sheets are not represented by simplifying the figure) and joining both as shown in Figure 4b on the side of the electrodes with a dielectric sheet 11 in the middle, so that the positive electrodes 5 of the first capacitor 10 are in front without touching it with the corresponding negative electrode 6 of the second capacitor 10 'separated by the

dieléctrico 11. La idea es que las cargas que viajen por los electrodos compensen su inductancia tal y como aparece en la Figura 2. Una vez unidos ambos condensadores (10.10’) en uno solo, los electrodos quedan abajo alternándose los positivos y negativos tal y como se ve en la Figura 4c, una vista superior de los condensadores dielectric 11. The idea is that the charges that travel through the electrodes compensate for their inductance as it appears in Figure 2. Once both capacitors (10.10 ') are joined into one, the electrodes are down alternating the positive and negative as and as seen in Figure 4c, a top view of the capacitors

5 mostrados en la Figura 4b. Otro aspecto de la presente invención es que los electrodos positivos 5 y negativos 6 y la lámina dieléctrica 11 que los separa están fabricados en una sola pieza, que puede ser un circuito impreso de dos o más capas. Otro aspecto de la presente invención consiste en unir en la base de los dos 5 shown in Figure 4b. Another aspect of the present invention is that the positive and negative electrodes 6 and the dielectric sheet 11 that separates them are made in one piece, which can be a printed circuit of two or more layers. Another aspect of the present invention consists in joining at the base of the two

10 condensadores (10,10’) los electrodos positivos 5 a un lado y los negativos 6 a otro. A esta disposición la llamaremos de ahora en adelante quot;distribuidorquot;. Un ejemplo de realización del distribuidor 15 aparece en las Figuras 5a y 5b, consistente en un circuito impreso o PCB de dos capas (una primera capa 12 y una segunda capa 12’). Siguiendo con las Figuras 5a y 5b, la primera capa 12 se une a los electrodos (5,6) del 10 capacitors (10.10 ’) the positive electrodes 5 on one side and the negative electrodes 6 on the other. We will call this provision from now on quot; distributorquot ;. An example of embodiment of the distributor 15 appears in Figures 5a and 5b, consisting of a printed circuit or two-layer PCB (a first layer 12 and a second layer 12 ’). Continuing with Figures 5a and 5b, the first layer 12 joins the electrodes (5,6) of the

15 condensador o bien soldándolo o bien pegando con pegamento conductor. Por otro lado la segunda capa 12’ une a un lado los electrodos positivos y los electrodos negativos por el otro. Es importante notar que la segunda capa 12’ queda en el exterior del condensador y sirve para soldar el condensador a circuitos impresos. La segunda capa 12’ cubre por debajo a la primera capa 12 poniendo una lámina positiva debajo 15 condenser either by welding it or by gluing with conductive glue. On the other hand, the second layer 12 ’links the positive electrodes and the negative electrodes on the other. It is important to note that the second layer 12 ’is outside the condenser and serves to weld the capacitor to printed circuits. The second layer 12 ’covers the first layer 12 below by putting a positive sheet underneath

20 de la conexión positiva 13, que actúa como conector positivo 1’, y una lámina negativa debajo de la conexión negativa 13’, que actúa como conector negativo 2’. Esto se hace así para reducir la inductancia tal y como se indica en la Figura 2. Por motivo de simplicidad de las Figuras 5a y 5b no se ha dibujado la lámina dieléctrica que debe haber entre capas ni entre electrodos. En la Figura 5a se muestran en la primera capa 20 of the positive connection 13, which acts as a positive connector 1 ’, and a negative sheet below the negative connection 13’, which acts as a negative connector 2 ’. This is done to reduce the inductance as indicated in Figure 2. For the sake of simplicity of Figures 5a and 5b the dielectric sheet must not be drawn between layers or between electrodes. In Figure 5a they are shown in the first layer

25 12 las conexiones (13,13’) con la segunda capa 12’. Otro aspecto de la presente invención consiste en que las pestañas (4,4’) en vez de ser rectangulares (según se muestra en la Figura 6a) pueden tener forma de trapezoide, tal y como aparece en la Figura 6b. El motivo es que además de reducir la distancia entre carga Q saliente y entrante, la adaptación de impedancia lámina25 12 the connections (13,13 ’) with the second layer 12’. Another aspect of the present invention is that the tabs (4.4 ’) instead of being rectangular (as shown in Figure 6a) can be trapezoid-shaped, as shown in Figure 6b. The reason is that in addition to reducing the distance between outgoing and incoming load Q, the impedance adaptation sheet

30 electrodo se incrementa de forma gradual. Además al ser los ángulos menos agudos simplifica la fabricación. Aun otro aspecto de la presente invención es que en lugar de una placa PCB de dos capas (12,12’) el distribuidor 15 tenga forma de delta de modo que la distancia del punto medio 19 (en la cara de conexión del distribuidor 15) de los dos condensadores 30 electrode gradually increases. In addition to being the less acute angles simplifies manufacturing. Still another aspect of the present invention is that instead of a two-layer PCB board (12,12 ') the distributor 15 has a delta shape so that the distance from the midpoint 19 (on the connection face of the distributor 15) of the two capacitors

35 (10,10’) a la punta 18 del distribuidor 15 sea lo más parecida posible a la distancia entre un punto extremo 20 (en la cara de conexión del distribuidor 15) de ambos condensadores y dicha punta 18. El condensador resultante se suelda al circuito por dicha punta 18 (con un conector positivo 1’ y un conector negativo 2’) tal y como aparece en la Figura 7a y que una vez terminado queda como en la Figura 7b. 35 (10.10 ') to the tip 18 of the distributor 15 is as close as possible to the distance between an end point 20 (on the connection face of the distributor 15) of both capacitors and said tip 18. The resulting capacitor is soldered to the circuit through said tip 18 (with a positive connector 1 'and a negative connector 2') as it appears in Figure 7a and which once finished is as in Figure 7b.

5 Aún otra manera de resolver la construcción es montar ambos condensadores (10,10’), dos de ellos directamente sobre el circuito impreso o PCB, uno en cada cara del mismo. En ese caso el PCB puede tener tres capas (una primera capa 16, una segunda capa 16’ y una tercera capa 16’’), como se indica en las Figuras 8a, 8b y 8c, quedando el conjunto como indica la Figura 8d, donde se ha omitido la segunda capa 5 Yet another way to solve the construction is to mount both capacitors (10,10 ’), two of them directly on the printed circuit or PCB, one on each side of it. In that case the PCB can have three layers (a first layer 16, a second layer 16 'and a third layer 16' '), as indicated in Figures 8a, 8b and 8c, the assembly being as indicated in Figure 8d, where the second layer has been omitted

10 16’ que está en medio y que sirve para conectar entre sí los electrodos positivos 5 del primer condensador 10 con los electrodos positivos 5 del segundo condensador 10’. Asimismo conecta los electrodos negativos 6 de los dos condensadores (10,10’). En la Figura 8a se muestran, en la primera capa 16, las conexiones 17 con la segunda capa 16’. De igual forma, en la Figura 8c se muestran, en la tercera capa 16’’, las 10 16 ’which is in the middle and which serves to connect the positive electrodes 5 of the first capacitor 10 with the positive electrodes 5 of the second capacitor 10’. It also connects the negative electrodes 6 of the two capacitors (10.10 ’). In Figure 8a, connections 17 with the second layer 16 'are shown in the first layer 16. Similarly, Figure 8c shows, in the third layer 16 ’, the

15 conexiones 17’ con la segunda capa 16’. Hay otra manera de reducir la distancia entre carga Q saliente y entrante , útil en aquellos casos donde no se pueden montar componentes en la cara de abajo del circuito impreso 22. En este caso la solución se puede ver en las Figuras 9a y 9b, y que consiste en dar profundidad a los electrodos en contacto con los condensadores 15 connections 17 ’with the second layer 16’. There is another way to reduce the distance between outgoing and incoming load Q, useful in those cases where components cannot be mounted on the underside of the printed circuit 22. In this case the solution can be seen in Figures 9a and 9b, and which consists in giving depth to the electrodes in contact with the capacitors

20 (10,10’) para luego distribuir los electrodos a un lado y a otro con una primera estructura 21 en forma troncocónica o cuadrangular que se conecta los electrodos positivos 5, habiendo una segunda estructura 21’ simétrica que conecta los electrodos negativos 6. En la Figura 9c se puede ver estas estructuras (21,21’), con los condensadores (10,10’), montadas justo al lado de un dispositivo electrónico 23 al que 20 (10,10 ') and then distribute the electrodes to one side and another with a first structure 21 in a truncated conical or quadrangular form that connects the positive electrodes 5, there being a second symmetrical structure 21' that connects the negative electrodes 6. In Figure 9c shows these structures (21,21 '), with the capacitors (10,10'), mounted just next to an electronic device 23 to which

25 está conectado mediante el circuito impreso 22. Como puede verse en la Figura 9a hay unas flechas que indican cómo las cargas Q entrantes y salientes pasan una cerca de la otra. El motivo de alargar los electrodos (5,6) no es otro que el de dar un camino amplio a las cargas de salida y entrada hacia las estructuras troncocónicas. 25 is connected by the printed circuit 22. As can be seen in Figure 9a there are arrows indicating how the incoming and outgoing Q charges pass close to each other. The reason for lengthening the electrodes (5,6) is none other than to give a wide path to the output and input charges towards the truncated conical structures.

30 BREVE DESCRIPCIÓN DE LAS FIGURAS Una explicación más detallada del dispositivo de acuerdo con realizaciones de la invención se da en la siguiente descripción basada en las figuras adjuntas en las que: La figura 1 muestra como se fabrican los condensadores y que consiste en apilar sucesivamente láminas positivas y negativas, poniendo entre éstas láminas BRIEF DESCRIPTION OF THE FIGURES A more detailed explanation of the device according to embodiments of the invention is given in the following description based on the attached figures in which: Figure 1 shows how the capacitors are manufactured and consisting of successively stacking sheets positive and negative, putting between these plates

35 dieléctricas o sea aislantes para que no se cortocircuiten entre sí. 35 dielectric or insulating so that they do not short-circuit each other.

La figura 2 muestra como deben circular las cargas dentro del condensador para que la inductancia sea mínima. Las figura 3a y 3b muestran un condensador de tecnología quot;IDCquot;, que es como el anterior pero con muchas pestañas, estando éstas en ambos lados del condensador. Figure 2 shows how the charges must circulate inside the condenser so that The inductance is minimal. Figures 3a and 3b show a technology capacitor "IDCquot ;, which is like the anterior but with many tabs, these being on both sides of the condenser.

5 La figura 3b muestra dicho condensador con los electrodos ya ensamblados. Las figuras 3c y 3d muestran los electrodos verticales positivos y negativos, originados al unir las láminas positivas y negativas. La figura 4a indica como se construye una mitad del condensador y que consiste en láminas alternas positivas y negativas. Además entre las láminas positivas y negativas 5 Figure 3b shows said capacitor with the electrodes already assembled. Figures 3c and 3d show the positive and negative vertical electrodes, originated by joining the positive and negative sheets. Figure 4a indicates how one half of the capacitor is constructed and that it consists of alternating positive and negative sheets. Also between the positive and negative sheets

10 se colocan láminas aislantes que no aparecen en el dibujo por simplificar el mismo. Las láminas positivas se unen entre sí pegando o soldando a electrodos verticales positivos. Las láminas negativas se unen asimismo a electrodos negativos La figura 4b muestra un condensador objeto de la invención, formado por dos condensadores descritos en la figura 4a con una lámina aislante entre ambos. Es de 10 insulating sheets are placed that do not appear in the drawing to simplify it. The positive sheets are joined together by gluing or welding to positive vertical electrodes. The negative sheets are also attached to negative electrodes Figure 4b shows a capacitor object of the invention, formed by two capacitors described in Figure 4a with an insulating sheet between them. It is

15 notar que el condensador de enfrente tiene cada electrodo positivo uno negativo en frente y viceversa. La figura 4c muestra a estos dos condensadores ensamblados formando uno solo, todo vistos desde arriba. La figura 5a muestra las dos capas del llamado quot;distribuidorquot; que se pone debajo del 15 Note that the opposite capacitor has each positive electrode a negative one in front and vice versa. Figure 4c shows these two capacitors assembled forming one, all viewed from above. Figure 5a shows the two layers of the so-called "distributor"; that gets under the

20 condensador de las Figuras 4b y 4c. Las dos capas montadas son un circuito PCB y sirven para unir los electrodos positivos a un lado y los negativos a otro. La figura 5b muestra como se ensamblan las dos capas a los electrodos y las dos mitades del condensador. En el dibujo se omite las láminas de dieléctrico que hay entre capas y la que hay entre las dos filas de electrodos. Las quot;Xquot; de la Figura 5a indican los puntos 20 capacitor of Figures 4b and 4c. The two mounted layers are a PCB circuit and serve to connect the positive electrodes on one side and the negative electrodes on the other. Figure 5b shows how the two layers are assembled to the electrodes and the two halves of the capacitor. In the drawing, the dielectric sheets between layers and the one between the two rows of electrodes are omitted. The "Xquot; of Figure 5a indicate the points

25 donde se ponen los pasa caras que unen las dos capas del PCB. La figura 6a muestra láminas con pestañas rectangulares y la 6b es una lámina con pestañas trapezoidales. La figura 7a muestra un distribuidor en forma de delta. La figura 7b muestra el condensador con el aislante puesto listo para montarse en el PCB. Las láminas 25 where the face passes connecting the two layers of the PCB are placed. Figure 6a shows sheets with rectangular tabs and 6b is a sheet with trapezoidal tabs. Figure 7a shows a delta-shaped distributor. Figure 7b shows the capacitor with the insulator placed ready to be mounted on the PCB. The sheets

30 positivas y negativas se pueden extender para ocupar mayor superficie. Las figuras 8a, 8b y 8c muestran las tres capas de un circuito impreso donde se han de soldar los dos condensadores, uno se suelda en la primera capa y el otro por debajo en la tercera capa. Las cruces (“X”) muestran las conexiones entre primera capa y segunda capa, y entre la segunda capa y la tercera capa. Entre la primera capa 30 positive and negative can be extended to occupy more surface. Figures 8a, 8b and 8c show the three layers of a printed circuit where the two capacitors have to be soldered, one is welded in the first layer and the other below in the third layer. The crosses ("X") show the connections between the first layer and the second layer, and between the second layer and the third layer. Between the first layer

35 y la segunda capa se pone una lámina aislante y entre la segunda capa y la tercera capa también, aunque no aparecen en la figura para simplificar. En la Figura 8d aparecen las capas primera y tercera y los dos condensadores, no apareciendo la segunda capa por sencillez del dibujo. En las Figuras 9a y 9b aparece un condensador solo en el cual se le ha dado 35 and the second layer is placed an insulating sheet and between the second layer and the third layer also, although they do not appear in the figure to simplify. In Figure 8d the first and third layers and the two capacitors appear, the second layer not appearing due to the simplicity of the drawing. A capacitor appears only in Figures 9a and 9b in which it has been given

5 profundidad a la estructura que separa los electrodos positivos y negativos. En la Figura 9a se muestra con flechas las cargas entrantes y salientes que tienen una distancia mínima entre sí. En la Figura 9c se muestra el condensador ensamblado una vez instalado en un circuito impreso o PCB al lado del componente electrónico al cual está conectado. 5 depth to the structure that separates the positive and negative electrodes. In Figure 9a, the incoming and outgoing loads with a minimum distance from each other are shown with arrows. Figure 9c shows the assembled capacitor once installed in a printed circuit or PCB next to the electronic component to which it is connected.

DESCRIPTION OF AN EMBODIMENT

Un primer modo de realización se muestra en las Figuras 4b y 4c, donde los electrodos (5,6) de dos condensadores (10, 10’) se unen con una lámina de dieléctrico 11 en medio. Otro modo de realización aparece en la figura 5b, consiste en la A first embodiment is shown in Figures 4b and 4c, where the electrodes (5,6) of two capacitors (10, 10 ') are joined with a dielectric sheet 11 in the middle. Another embodiment appears in Figure 5b, consisting of the

15 fabricación completa de un condensador formado por dos condensadores , con una estructura debajo que llamamos distribuidor y cuya construcción sigue según figuras 5a y 5b. Las pestañas de las láminas conductoras positivas y negativas pueden ser rectangulares, según se muestra en la Figura 6a, o trapezoidales, según se muestra en la Figura 6b. 15 Complete manufacture of a capacitor consisting of two capacitors, with a structure under which we call distributor and whose construction follows according to figures 5a and 5b. The tabs of the positive and negative conductive sheets can be rectangular, as shown in Figure 6a, or trapezoidal, as shown in Figure 6b.

20 Otro modo de realización aparece en las figuras 7a y 7b y consiste en dos condensadores que se unen en uno solo unidos por dos filas de electrodos y un distribuidor en forma de delta. Aún otro modo de realización aparece en las figura 8d y que consiste en soldar o pegar las dos mitades del condensador en la cara superior e inferior de un circuito 20 Another embodiment appears in Figures 7a and 7b and consists of two capacitors that are joined in only one joined by two rows of electrodes and a delta-shaped distributor. Yet another embodiment appears in figures 8d and that consists of welding or gluing the two halves of the capacitor on the upper and lower face of a circuit

25 impreso o PCB de al menos tres capas como las descritas en las figuras 8a, 8b y 8c. Aún otro modo cuando no se puede montar componentes en el PCB por la cara inferior se muestra en las figuras 9a y 9b, y que una vez ensamblados puede verse como quedan en el dibujo 9c donde se ha instalado al lado del componente electrónico donde va conectado. 25 printed or PCB of at least three layers as described in Figures 8a, 8b and 8c. Still another way when components cannot be mounted on the PCB by the underside is shown in Figures 9a and 9b, and once assembled it can be seen as they are in drawing 9c where it has been installed next to the electronic component where it is connected .

Claims

1. High-speed loading and unloading electricity storage device, characterized in that it comprises:

--: dos condensadores (10,10’) formados por láminas horizontales conductoras two capacitors (10,10 ’) formed by conductive horizontal sheets

5 positive (1) and negative (2) with a plurality of tabs (4.4 ') and connected respectively to positive (5) and negative (6) vertical electrodes, both capacitors being arranged so that the positive vertical electrodes (5 ) of one capacitor face the negative vertical electrodes (6) of the other capacitor; Y

10 - a dielectric sheet (11) between both rows of electrodes.

2. Device according to claim 1, characterized in that it additionally has a distributor (15) responsible for connecting the positive vertical electrodes (5) and the negative vertical electrodes (6) of both capacitors (10,10 ’)

15 respectively to a positive connector (1 ’) and a negative connector (2’) so that they can be soldered to a printed circuit.

3. Device according to claim 2, characterized in that the distributor

(15) is formed by a two-layer printed circuit (12.12 ’), so that the 20 capacitors (10.10’) are welded on the same side of said printed circuit.

4. Device according to claim 2, characterized in that the distributor

(15) is a delta-shaped structure, with the positive (1 ’) and negative (2’) connectors at the tip (18) of the distributor.

5. Device according to claim 2, characterized in that the distributor is formed by a three-layer printed circuit (16,16 ', 16' '), so that the capacitors (10,10') are welded on opposite faces of said printed circuit.

Device according to claim 2, characterized in that the distributor comprises a first (21) and a second (21 ') conical or quadrangular shaped structure both located on one side of one of the capacitors and connected respectively to the electrodes positive verticals (5) and negative vertical electrodes (6) of the capacitors (10.10 ').

7. Device according to any of the preceding claims, characterized in that the tabs (4.4 ’) of the positive (1) and negative (2) conductive horizontal sheets are trapezoidal.

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Fig. 6b

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SPANISH OFFICE OF THE PATENTS AND BRAND

Application no .: 201200881

SPAIN

Date of submission of the application: 11.09.2012

Priority Date:

REPORT ON THE STATE OF THE TECHNIQUE

51 Int. Cl.: See Additional Sheet

RELEVANT DOCUMENTS

Categoría Category: 56 Documentos citados Reivindicaciones afectadas 56 Documents cited Claims Affected

X X: JP 2007115759 A (TDK CORP.) 10.05.2007, 1-6 JP 2007 115759 A (TDK CORP.) 10.05.2007, 1-6

párrafos [1-9],[25-34]; figuras 16,17-23; resumen de la base de datos EPODOC, resumen de la paragraphs [1-9], [25-34]; Figures 16.17-23; summary of the EPODOC database, summary of the

base de datos WPI, AN 2007-563571. WPI database, AN 2007-563571.

Y Y: 7 7

Y Y: US 2004207971 A1 (PRYMAK et al.) 21.10.2004, 7 US 2004207971 A1 (PRYMAK et al.) 21.10.2004, 7

párrafos [24-33]; figuras 1-5. paragraphs [24-33]; Figures 1-5.

X X: US 2004150941 A1 (KURODA et al.) 05.08.2004, 1-6 US 2004 150941 A1 (KURODA et al.) 05.08.2004, 1-6

resumen; párrafos [1-14],[95-106]; figuras 7-11. summary; paragraphs [1-14], [95-106]; Figures 7-11.

Y Y: 7 7

Categoría de los documentos citados X: de particular relevancia Y: de particular relevancia combinado con otro/s de la misma categoría A: refleja el estado de la técnica O: referido a divulgación no escrita P: publicado entre la fecha de prioridad y la de presentación de la solicitud E: documento anterior, pero publicado después de la fecha de presentación de la solicitud Category of the documents cited X: of particular relevance Y: of particular relevance combined with other / s of the same category A: reflects the state of the art O: refers to unwritten disclosure P: published between the priority date and the date of priority submission of the application E: previous document, but published after the date of submission of the application

El presente informe ha sido realizado • para todas las reivindicaciones • para las reivindicaciones nº: This report has been prepared • for all claims • for claims no:

Fecha de realización del informe 26.12.2013 Date of completion of the report 12.26.2013: Examinador A. Figuera González Página 1/5 Examiner A. Figuera González Page 1/5

REPORT OF THE STATE OF THE TECHNIQUE

Application number: 201200881

CLASSIFICATION OBJECT OF THE APPLICATION H01G4 / 232 (2006.01)

H01G4 / 30 (2006.01) H01G4 / 38 (2006.01) Minimum documentation sought (classification system followed by classification symbols)

H01G

Electronic databases consulted during the search (name of the database and, if possible, terms of search used) INVENES, EPODOC, WPI, TXTEN

State of the Art Report Page 2/5

WRITTEN OPINION

Application number: 201200881

Date of Completion of Written Opinion: 12.26.2013

Statement

Novedad (Art. 6.1 LP 11/1986) Novelty (Art. 6.1 LP 11/1986): Reivindicaciones Reivindicaciones 2-7 1 SI NO Claims Claims 2-7 1 IF NOT

Actividad inventiva (Art. 8.1 LP11/1986) Inventive activity (Art. 8.1 LP11 / 1986): Reivindicaciones Reivindicaciones 1-7 SI NO Claims Claims 1-7 IF NOT

The application is considered to comply with the industrial application requirement. This requirement was evaluated during the formal and technical examination phase of the application (Article 31.2 Law 11/1986).

Opinion Base.-

This opinion has been made on the basis of the patent application as published.

State of the Art Report Page 3/5

WRITTEN OPINION

Application number: 201200881

1. Documents considered.-

The documents belonging to the state of the art taken into consideration for the realization of this opinion are listed below.

Documento Document: Número Publicación o Identificación Fecha Publicación Publication or Identification Number publication date

D01 D01: JP 2007115759 A (TDK CORP.) 10.05.2007 JP 2007115759 A (TDK CORP.) 05.10.2007

D02 D02: US 2004207971 A1 (PRYMAK et al.) 21.10.2004 US 2004207971 A1 (PRYMAK et al.) 21.10.2004

D03 D03: US 2004150941 A1 (KURODA et al.) 05.08.2004 US 2004 150941 A1 (KURODA et al.) 05.08.2004

2. Statement motivated according to articles 29.6 and 29.7 of the Regulations for the execution of Law 11/1986, of March 20, on Patents on novelty and inventive activity; quotes and explanations in support of this statement

CLAIM 1

Document D01 describes a capacitor consisting of two adjacent capacitor blocks (1A, 1B) whose positive lateral end electrodes (13, 23) are arranged in front of the negative lateral end electrodes (14, 24) and are kept isolated from each other . It is thus achieved that the magnetic field that occurs in the positive terminal electrodes (13,23) and the magnetic field that occurs in the negative terminal electrodes (14, 24) cancel each other thereby reducing the equivalent series inductance ( ESL -equivalent serial inductance). See D01, summary of the WPI database, summary of the EPODOC database and D01, page 16, figures 2 and 3.

The part of claim 1 corresponding to elements also described in document D01 is shown in italics, indicating in brackets and underlining the expressions and references used to designate said elements in D01.

Device for storing high-speed electricity for loading and unloading, characterized in that it comprises:

--: dos condensadores (10,10’) (dos bloques de condensadores 1A y 1B, véase D01, resumen WPI y D01, párrafo 25 y página 16, figuras 2 y 3) formados por láminas horizontales conductoras positivas (1) (láminas 11 y 21, véase D01, página 16, figuras 2,3) y negativas (2) (láminas 12 y 22, véase D01, página 16, figuras 2,3) con una pluralidad de pestañas (4,4’)(pestañas 15 y 16, véase D01, páginas 16 y 17, figuras 3 y 4) y conectadas respectivamente a electrodos verticales positivos (5) (electrodos terminales positivos 13 y 23, véase D01, página 16, figuras 2 y 3) y negativos (6) (electrodos terminales negativos 14 y 24, véase D01, página 16, figuras 2 y 3), estando ambos condensadores dispuestos de modo que los electrodos verticales positivos (5) de un condensador se enfrentan con los electrodos verticales negativos (6) del otro condensador (Entre los bloques de condensadores 1A y 1B los electrodos terminales con diferentes polaridades se disponen de tal forma que estén el uno enfrente del otro, véase D01, resumen de WPI y D01, página 16, figuras 2 y 3); y two capacitors (10,10 ') (two blocks of capacitors 1A and 1B, see D01, summary WPI and D01, paragraph 25 and page 16, figures 2 and 3) formed by positive conductive horizontal sheets (1) (sheets 11 and 21 , see D01, page 16, figures 2,3) and negative (2) (sheets 12 and 22, see D01, page 16, figures 2,3) with a plurality of tabs (4,4 ') (tabs 15 and 16 , see D01, pages 16 and 17, figures 3 and 4) and connected respectively to positive vertical electrodes (5) (positive terminal electrodes 13 and 23, see D01, page 16, figures 2 and 3) and negative (6) (electrodes negative terminals 14 and 24, see D01, page 16, figures 2 and 3), both capacitors being arranged so that the positive vertical electrodes (5) of one capacitor face the negative vertical electrodes (6) of the other capacitor (Between the capacitor blocks 1A and 1B the terminal electrodes with different polarities are arranged so that they are n the facing each other, see D01, D01 and WPI abstract, page 16, figures 2 and 3); Y

--: una lámina de dieléctrico (11) entre ambas filas de electrodos (los bloques de condensadores 1A y 1B están aislados el uno del otro por un elemento aislante 31, véase D01, resumen de WPI, D01, párrafo 30 y D01, página 16, figuras 2 y 3 y página 17, figura 5) a dielectric sheet (11) between both rows of electrodes (capacitor blocks 1A and 1B are isolated from each other by an insulating element 31, see D01, WPI summary, D01, paragraph 30 and D01, page 16, figures 2 and 3 and page 17, figure 5)

Thus, document D01 discloses all the elements of claim 1.

In conclusion, claim 1 is not new according to article 6 of Patent Law 11/1986.

Alternatively, document D03 could be considered as the state of the art document closest to the object of claim 1.

In D03 a device is described which has all the characteristics of the device object of claim 1 unless it is not explicitly mentioned that the opposite electrodes are separated by a dielectric sheet.

However, it is obvious to the person skilled in the art that said electrodes must be isolated from each other to avoid arc leaks and that the air is in this case acting as a dielectric. It would also have been evident to the person skilled in the art that if it were desired to bring the opposing electrodes closer together, it would have been necessary to separate them by a dielectric material with greater insulating capacity than air.

Therefore, and in an alternative way to the motivation for lack of novelty based on document D01, it is also considered that claim 1 lacks inventive activity in accordance with article 8 of Patent Law 11/1986 according to the reasoning set forth which is based on document D03.

In the following the motivation is continued based on document D01, but the same reasoning could be made for the following claims using document D03 alternatively.

State of the Art Report Page 4/5

WRITTEN OPINION

Application number: 201200881

CLAIMS 2 TO 6

In document D01 an embodiment is shown in which the multiple capacitor 1 composed of the two capacitor blocks 1A and 1B has a mounting card 40 that allows the positive electrodes 13, 23 to be connected indirectly to a connection layer 41 a through holes 45 while the negative electrodes 14 and 24 are connected directly to a connection layer 42. The mounting card 40 is formed by the two connection layers 41 and 42 separated by an insulating layer 43.

It is considered that the differences between the way of connecting the positive electrodes and the negative electrodes to each other of document D01 and the forms of connection object of claims 2 to 6, do not respond to the resolution of any different technical problem in the case of mere alternatives of design.

In conclusion, it is considered that claims 2 to 6, depending on claim 1 that has no novelty or previous claims that has no inventive activity, in turn lack inventive activity in accordance with article 8 of Patent Law 11 / 1986

CLAIM 7

In document D02 a multilayer capacitor with a flat electrode 2 with tabs 3 is described. The tabs 3 have a contact face 4 and two opposite divergent edges 6. The tabs have a trapezoidal shape. See D02, paragraphs 26 and 27 and figures 1 and 2.

The purpose of giving the eyelashes a divergent shape from the contact face is to achieve a lower equivalent inductance in ESL series. See D02, paragraphs 32 and 33.

For the person skilled in the art, it is considered that it would have been obvious, in order to reduce the ESL in the device of document D01, to incorporate the teachings of document D02 using trapezoidal tabs.

Therefore it is considered that claim 7, dependent on claim 1 lacking novelty or other previous claims that have no inventive activity, also has no inventive activity.

State of the Art Report Page 5/5