ES2143866T3 - Microprocesador multicadenas de mensajes conectados configurado para ejecutar rutinas de servicio de interruptor como una cadena de mensajes conectados. - Google Patents

Microprocesador multicadenas de mensajes conectados configurado para ejecutar rutinas de servicio de interruptor como una cadena de mensajes conectados.

Info

Publication number
ES2143866T3
ES2143866T3 ES97924753T ES97924753T ES2143866T3 ES 2143866 T3 ES2143866 T3 ES 2143866T3 ES 97924753 T ES97924753 T ES 97924753T ES 97924753 T ES97924753 T ES 97924753T ES 2143866 T3 ES2143866 T3 ES 2143866T3
Authority
ES
Spain
Prior art keywords
context
microprocessor
chain
routines
contexts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES97924753T
Other languages
English (en)
Inventor
Drew J Dutton
David S Christie
Brian C Barnes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2143866T3 publication Critical patent/ES2143866T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

SE SUMINISTRA UN MICROPROCESADOR QUE INCLUYE UN ARCHIVO DE CONTEXTO CONFIGURADO PARA ALMACENAR MULTIPLES CONTEXTOS. EL MICROPROCESADOR PUEDE EJECUTAR MULTIPLES PROGRAMAS, TENIENDO CADA PROGRAMA SU PROPIO CONTEXTO DENTRO DEL MICROPROCESADOR. EN UNA REALIZACION, EL PRESENTA MICROPROCESADOR ES CAPAZ DE EJECUTAR AL MENOS DOS PROGRAMAS CONCURRENTEMENTE: UNA TAREA Y UNA RUTINA DE SERVICIO DE INTERRUPCION. LAS RUTINAS DE SERVICIO DE INTERRUPCIONES PUEDE EJECUTARSE SIN PERTURBAR UN CONTEXTO DE TAREA Y SIN REALIZAR UNA OPERACION DE GRABACION DE CONTEXTO. EN VEZ DE ELLO, LA RUTINA DE SERVICIO DE INTERRUPCION ACCEDE A UN CONTEXTO QUE ES INDEPENDIENTE DEL CONTEXTO DE LA TAREA. EN OTRA REALIZACION, EL ARCHIVO DE CONTEXTO INCLUYE MULTIPLES CONTEXTOS DE RUTINAS DE SERVICIO DE INTERRUPCIONES. MULTIPLES ALMACENAMIENTO DE CONTEXTOS DE ISR PERMITEN QUE SE REALICEN INTERRUPCIONES ANIDADAS DE FORMA CONCURRENTE. EN OTRA REALIZACION, EL MICROPROCESADOR ESTA CONFIGURADO PARA EJECUTAR MULTIPLES TAREAS Y MULTIPLES RUTINAS DE SERVICIO DE INTERRUPCIONES CONCURRENTEMENTE. PUEDEN EJECUTARSE MULTIPLES TAREAS CONCURRENTEMENTE POR EL MICROPROCESADOR ADEMAS DE EJECUTAR MULTIPLES RUTINAS DE SERVICIO DE INTERRUPCIONES DE FORMA CONCURRENTE. EN OTRA REALIZACION ADICIONAL, EL MICROPROCESADOR INCLUYE UN CONTEXTO PRIMARIO Y ALMACENAMIENTOS MULTIPLES DE CONTEXTOS LOCALES ACOPLADOS A CADA UNA DE SUS UNIDADES DE EJECUCION. UNA UNIDAD DE EJECUCION DADA PUEDE EJECUTAR INSTRUCCIONES QUE SE REFIEREN AL CONTEXTO PRIMARIO O AL CONTEXTO LOCAL CONECTADO AL MISMO.
ES97924753T 1996-05-17 1997-05-16 Microprocesador multicadenas de mensajes conectados configurado para ejecutar rutinas de servicio de interruptor como una cadena de mensajes conectados. Expired - Lifetime ES2143866T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/649,809 US5944816A (en) 1996-05-17 1996-05-17 Microprocessor configured to execute multiple threads including interrupt service routines

Publications (1)

Publication Number Publication Date
ES2143866T3 true ES2143866T3 (es) 2000-05-16

Family

ID=24606316

Family Applications (1)

Application Number Title Priority Date Filing Date
ES97924753T Expired - Lifetime ES2143866T3 (es) 1996-05-17 1997-05-16 Microprocesador multicadenas de mensajes conectados configurado para ejecutar rutinas de servicio de interruptor como una cadena de mensajes conectados.

Country Status (5)

Country Link
US (1) US5944816A (es)
EP (1) EP0898743B1 (es)
DE (1) DE69701141T2 (es)
ES (1) ES2143866T3 (es)
WO (1) WO1997044732A1 (es)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6405234B2 (en) * 1997-09-11 2002-06-11 International Business Machines Corporation Full time operating system
US6061710A (en) * 1997-10-29 2000-05-09 International Business Machines Corporation Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
US6161166A (en) * 1997-11-10 2000-12-12 International Business Machines Corporation Instruction cache for multithreaded processor
US6330584B1 (en) * 1998-04-03 2001-12-11 Mmc Networks, Inc. Systems and methods for multi-tasking, resource sharing and execution of computer instructions
US6163839A (en) * 1998-09-30 2000-12-19 Intel Corporation Non-stalling circular counterflow pipeline processor with reorder buffer
US6401155B1 (en) * 1998-12-22 2002-06-04 Philips Electronics North America Corporation Interrupt/software-controlled thread processing
JP3778246B2 (ja) * 1999-03-23 2006-05-24 セイコーエプソン株式会社 割り込みコントローラ、ａｓｉｃ、及び電子機器
US6493781B1 (en) 1999-08-19 2002-12-10 Koninklijke Philips Electronics N.V. Servicing of interrupts with stored and restored flags
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
US7318090B1 (en) * 1999-10-20 2008-01-08 Sony Corporation Method for utilizing concurrent context switching to support isochronous processes
DE19955776C1 (de) * 1999-11-19 2001-07-19 Infineon Technologies Ag Multitasking-Prozessorsystem
US7308686B1 (en) 1999-12-22 2007-12-11 Ubicom Inc. Software input/output using hard real time threads
US7120783B2 (en) * 1999-12-22 2006-10-10 Ubicom, Inc. System and method for reading and writing a thread state in a multithreaded central processing unit
AU2597401A (en) * 1999-12-22 2001-07-03 Ubicom, Inc. System and method for instruction level multithreading in an embedded processor using zero-time context switching
DE10000960C1 (de) * 2000-01-12 2001-12-20 Infineon Technologies Ag Datenverarbeitungsvorrichtung
US6931641B1 (en) 2000-04-04 2005-08-16 International Business Machines Corporation Controller for multiple instruction thread processors
US7093109B1 (en) 2000-04-04 2006-08-15 International Business Machines Corporation Network processor which makes thread execution control decisions based on latency event lengths
US6676044B2 (en) * 2000-04-07 2004-01-13 Siemens Automotive Corporation Modular fuel injector and method of assembling the modular fuel injector
US6848043B1 (en) * 2000-04-27 2005-01-25 Intel Corporation Optimal redundant arithmetic for microprocessors design
US6684342B1 (en) 2000-06-22 2004-01-27 Ubicom, Inc. Apparatus and method of dynamic and deterministic changes in clock frequency for lower power consumption while maintaining fast interrupt handling
US7047396B1 (en) 2000-06-22 2006-05-16 Ubicom, Inc. Fixed length memory to memory arithmetic and architecture for a communications embedded processor system
US7010612B1 (en) 2000-06-22 2006-03-07 Ubicom, Inc. Universal serializer/deserializer
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US6829719B2 (en) * 2001-03-30 2004-12-07 Transmeta Corporation Method and apparatus for handling nested faults
US7320065B2 (en) 2001-04-26 2008-01-15 Eleven Engineering Incorporated Multithread embedded processor with input/output capability
US6845959B2 (en) * 2001-05-04 2005-01-25 Hydril Company, L.P. Quick release blowout preventer bonnet
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US20030065855A1 (en) * 2001-07-12 2003-04-03 Webster Steve R. Imbedded interrupt
US7011288B1 (en) 2001-12-05 2006-03-14 Microstar Technologies Llc Microelectromechanical device with perpendicular motion
US6856953B1 (en) 2001-12-19 2005-02-15 Globespanvirata, Inc. Method and system for testing algorithm compliancy
JP2004102324A (ja) * 2002-09-04 2004-04-02 Oki Electric Ind Co Ltd 割り込みプログラムモジュール、該モジュールを記録した記録媒体およびモニタのための割り込み処理が可能のコンピュータ
US20050033889A1 (en) * 2002-10-08 2005-02-10 Hass David T. Advanced processor with interrupt delivery mechanism for multi-threaded multi-CPU system on a chip
US20060149927A1 (en) * 2002-11-26 2006-07-06 Eran Dagan Processor capable of multi-threaded execution of a plurality of instruction-sets
US7822950B1 (en) 2003-01-22 2010-10-26 Ubicom, Inc. Thread cancellation and recirculation in a computer processor for avoiding pipeline stalls
US20040215937A1 (en) * 2003-04-23 2004-10-28 International Business Machines Corporation Dynamically share interrupt handling logic among multiple threads
US7496915B2 (en) * 2003-04-24 2009-02-24 International Business Machines Corporation Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes
US8266379B2 (en) * 2003-06-02 2012-09-11 Infineon Technologies Ag Multithreaded processor with multiple caches
US7870553B2 (en) * 2003-08-28 2011-01-11 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US20050050305A1 (en) * 2003-08-28 2005-03-03 Kissell Kevin D. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US7836450B2 (en) 2003-08-28 2010-11-16 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7610473B2 (en) * 2003-08-28 2009-10-27 Mips Technologies, Inc. Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor
US7849297B2 (en) * 2003-08-28 2010-12-07 Mips Technologies, Inc. Software emulation of directed exceptions in a multithreading processor
US7376954B2 (en) * 2003-08-28 2008-05-20 Mips Technologies, Inc. Mechanisms for assuring quality of service for programs executing on a multithreaded processor
US7711931B2 (en) * 2003-08-28 2010-05-04 Mips Technologies, Inc. Synchronized storage providing multiple synchronization semantics
US9032404B2 (en) 2003-08-28 2015-05-12 Mips Technologies, Inc. Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor
US7594089B2 (en) * 2003-08-28 2009-09-22 Mips Technologies, Inc. Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
US7418585B2 (en) * 2003-08-28 2008-08-26 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
JP4204522B2 (ja) * 2004-07-07 2009-01-07 株式会社東芝 マイクロプロセッサ
US7487503B2 (en) 2004-08-12 2009-02-03 International Business Machines Corporation Scheduling threads in a multiprocessor computer
JP2006172316A (ja) * 2004-12-17 2006-06-29 Nec Corp コンテキスト維持方法、情報処理装置及び割り込み発生装置
US7398371B2 (en) * 2005-06-23 2008-07-08 Qualcomm Incorporated Shared translation look-aside buffer and method
US7676604B2 (en) * 2005-11-22 2010-03-09 Intel Corporation Task context direct indexing in a protocol engine
US7971205B2 (en) * 2005-12-01 2011-06-28 International Business Machines Corporation Handling of user mode thread using no context switch attribute to designate near interrupt disabled priority status
US7734897B2 (en) * 2005-12-21 2010-06-08 Arm Limited Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads
US8884972B2 (en) 2006-05-25 2014-11-11 Qualcomm Incorporated Graphics processor with arithmetic and elementary function units
US8869147B2 (en) * 2006-05-31 2014-10-21 Qualcomm Incorporated Multi-threaded processor with deferred thread output control
US7870372B2 (en) 2006-08-14 2011-01-11 Marvell World Trade Ltd. Interrupt handling
US8219789B2 (en) * 2007-03-14 2012-07-10 XMOS Ltd. Interface processor
DE102008010943A1 (de) * 2008-02-25 2009-09-03 Fujitsu Siemens Computers Gmbh Verfahren zur Behandlung von Unterbrechungsaufforderungen bei einem Prozessor
US9880842B2 (en) * 2013-03-15 2018-01-30 Intel Corporation Using control flow data structures to direct and track instruction execution
US10031773B2 (en) 2014-02-20 2018-07-24 Nxp Usa, Inc. Method to communicate task context information and device therefor
WO2015145834A1 (ja) * 2014-03-24 2015-10-01 株式会社スクウェア・エニックス インタラクティブシステム、端末装置、サーバ装置、制御方法、プログラム、及び記録媒体
US10942748B2 (en) * 2015-07-16 2021-03-09 Nxp B.V. Method and system for processing interrupts with shadow units in a microcontroller
KR20170065845A (ko) * 2015-12-04 2017-06-14 삼성전자주식회사 프로세서 및 제어 방법
US9703603B1 (en) 2016-04-25 2017-07-11 Nxp Usa, Inc. System and method for executing accelerator call
US10761970B2 (en) * 2017-10-20 2020-09-01 International Business Machines Corporation Computerized method and systems for performing deferred safety check operations
US11188340B2 (en) * 2018-12-20 2021-11-30 International Business Machines Corporation Multiple streams execution for hard-to-predict branches in a microprocessor
US11169812B2 (en) 2019-09-26 2021-11-09 Advanced Micro Devices, Inc. Throttling while managing upstream resources

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6349945A (ja) * 1986-08-20 1988-03-02 Nec Corp デ−タ処理装置のプロセス・ロ−ルイン方式
US5421014A (en) * 1990-07-13 1995-05-30 I-Tech Corporation Method for controlling multi-thread operations issued by an initiator-type device to one or more target-type peripheral devices
KR970008523B1 (ko) * 1991-10-21 1997-05-24 가부시키가이샤 도시바 프로세서
US5546593A (en) * 1992-05-18 1996-08-13 Matsushita Electric Industrial Co., Ltd. Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream
US5515538A (en) * 1992-05-29 1996-05-07 Sun Microsystems, Inc. Apparatus and method for interrupt handling in a multi-threaded operating system kernel
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
JP3569014B2 (ja) * 1994-11-25 2004-09-22 富士通株式会社 マルチコンテキストをサポートするプロセッサおよび処理方法
US5724565A (en) * 1995-02-03 1998-03-03 International Business Machines Corporation Method and system for processing first and second sets of instructions by first and second types of processing systems

Also Published As

Publication number Publication date
DE69701141T2 (de) 2000-09-21
EP0898743B1 (en) 2000-01-12
DE69701141D1 (de) 2000-02-17
WO1997044732A1 (en) 1997-11-27
US5944816A (en) 1999-08-31
EP0898743A1 (en) 1999-03-03

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