ES2143490T3 - Decodificador de instrucciones. - Google Patents

Decodificador de instrucciones.

Info

Publication number
ES2143490T3
ES2143490T3 ES93305676T ES93305676T ES2143490T3 ES 2143490 T3 ES2143490 T3 ES 2143490T3 ES 93305676 T ES93305676 T ES 93305676T ES 93305676 T ES93305676 T ES 93305676T ES 2143490 T3 ES2143490 T3 ES 2143490T3
Authority
ES
Spain
Prior art keywords
instructions
instruction
instruction decoder
shipping
search
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93305676T
Other languages
English (en)
Inventor
David B Witt
William M Johnson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2143490T3 publication Critical patent/ES2143490T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

UN MICROPROCESADOR SUPERESCALAR QUE LLEVA A CABO OPERACIONES EN BASE A UNA PLURALIDAD DE INSTRUCCIONES EN CADA UNA DE SUS ETAPAS DE BUSQUEDA, DECODIFICACION, EJECUCION Y REESCRITURA. PARA SOPORTAR TALES OPERACIONES, EL MICROPROCESADOR SUPERESCALAR INCLUYE UN EQUIPO DE ENVIO QUE INCLUYE UNA CACHE DE INSTRUCCIONES PARA LA BUSQUEDA DE BLOQUES DE INSTRUCCIONES QUE INCLUYEN UNA PLURALIDAD DE INSTRUCCIONES Y UN DECODIFICADOR DE INSTRUCCIONES QUE DECODIFICA Y ENVIA LAS INSTRUCCIONES A UNAS UNIDADES FUNCIONALES PARA SU EJECUCION. EL DECODIFICADOR DE INSTRUCCIONES APLICA CRITERIOS DE ENVIO A LAS INSTRUCCIONES SELECCIONADAS DE CADA UNO DE LOS BLOQUES DE INSTRUCCIONES Y ENVIA LAS INSTRUCCIONES SELECCIONADAS QUE SATISFAGAN LOS CRITERIOS DE ENVIO. LOS CRITERIOS DE ENVIO INCLUYEN EL REQUISITO DE QUE LAS INSTRUCCIONES SE ENVIEN ESPECULATIVAMENTE POR ORDEN, DE QUE HAYA OPERANDOS DE SOPORTE PARA LA EJECUCION DE LAS INSTRUCCIONES, O QUE HAYA VALORES ETIQUETADOS SUSTITUIDOS SE ENCUENTREN DISPONIBLES MAS TARDE, Y QUE SE ENCUENTREN DISPONIBLES LAS UNIDADES FUNCIONALES REQUERIDAS PARA LA EJECUCION DE LAS INSTRUCCIONES. EL FUNCIONAMIENTO DEL DECODIFICADOR DE INSTRUCCIONES Y DE LA CACHE DE INSTRUCCIONES SE COORDINA MEDIANTE UN PROTOCOLO PREDEFINIDO QUE ASEGURA QUE LAS INSTRUCCIONES SON ENVIADAS EN ORDEN CONSECUTIVO ASCENDENTE Y QUE LOS BLOQUES DE INSTRUCCIONES SON BUSCADOS DE MANERA EFICIENTE PARA QUE EL DECODIFICADOR DE INSTRUCCIONES LAS DECODIFIQUE Y ENVIE.
ES93305676T 1992-08-12 1993-07-20 Decodificador de instrucciones. Expired - Lifetime ES2143490T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US92977092A 1992-08-12 1992-08-12

Publications (1)

Publication Number Publication Date
ES2143490T3 true ES2143490T3 (es) 2000-05-16

Family

ID=25458426

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93305676T Expired - Lifetime ES2143490T3 (es) 1992-08-12 1993-07-20 Decodificador de instrucciones.

Country Status (5)

Country Link
US (1) US6279101B1 (es)
EP (1) EP0583089B1 (es)
JP (1) JPH06161753A (es)
DE (1) DE69327688T2 (es)
ES (1) ES2143490T3 (es)

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US5546599A (en) * 1994-03-31 1996-08-13 International Business Machines Corporation Processing system and method of operation for processing dispatched instructions with detected exceptions
US5625789A (en) * 1994-10-24 1997-04-29 International Business Machines Corporation Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle
US5867726A (en) * 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
US5835747A (en) * 1996-01-26 1998-11-10 Advanced Micro Devices, Inc. Hierarchical scan logic for out-of-order load/store execution control
US6044453A (en) * 1997-09-18 2000-03-28 Lg Semicon Co., Ltd. User programmable circuit and method for data processing apparatus using a self-timed asynchronous control structure
US6055620A (en) * 1997-09-18 2000-04-25 Lg Semicon Co., Ltd. Apparatus and method for system control using a self-timed asynchronous control structure
US6370637B1 (en) * 1999-08-05 2002-04-09 Advanced Micro Devices, Inc. Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria
US6763421B2 (en) * 2001-10-11 2004-07-13 International Business Machines Corporation Instruction pair detection and pseudo ports for cache array
US7275149B1 (en) * 2003-03-25 2007-09-25 Verisilicon Holdings (Cayman Islands) Co. Ltd. System and method for evaluating and efficiently executing conditional instructions
US7437532B1 (en) 2003-05-07 2008-10-14 Marvell International Ltd. Memory mapped register file
US7096345B1 (en) 2003-09-26 2006-08-22 Marvell International Ltd. Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof
US7937557B2 (en) 2004-03-16 2011-05-03 Vns Portfolio Llc System and method for intercommunication between computers in an array
US7293160B2 (en) * 2004-06-14 2007-11-06 Sun Microsystems, Inc. Mechanism for eliminating the restart penalty when reissuing deferred instructions
US8225034B1 (en) * 2004-06-30 2012-07-17 Oracle America, Inc. Hybrid instruction buffer
US7966481B2 (en) 2006-02-16 2011-06-21 Vns Portfolio Llc Computer system and method for executing port communications without interrupting the receiving computer
US7913069B2 (en) * 2006-02-16 2011-03-22 Vns Portfolio Llc Processor and method for executing a program loop within an instruction word
US7617383B2 (en) * 2006-02-16 2009-11-10 Vns Portfolio Llc Circular register arrays of a computer
US7904615B2 (en) 2006-02-16 2011-03-08 Vns Portfolio Llc Asynchronous computer communication
US7630777B2 (en) * 2006-07-06 2009-12-08 Honeywell International Inc. Apparatus and method for configurable process automation in a process control system
US7555637B2 (en) * 2007-04-27 2009-06-30 Vns Portfolio Llc Multi-port read/write operations based on register bits set for indicating select ports and transfer directions
GB2457265B (en) 2008-02-07 2010-06-09 Imagination Tech Ltd Prioritising of instruction fetching in microprocessor systems
US20100023730A1 (en) * 2008-07-24 2010-01-28 Vns Portfolio Llc Circular Register Arrays of a Computer
GB2469822B (en) * 2009-04-28 2011-04-20 Imagination Tech Ltd Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
JP5565228B2 (ja) 2010-09-13 2014-08-06 ソニー株式会社 プロセッサ
US9239574B2 (en) 2011-06-30 2016-01-19 Honeywell International Inc. Apparatus for automating field device operations by capturing device method execution steps for later use and related method
US8718807B2 (en) 2012-03-23 2014-05-06 Honeywell International Inc. System and method for robust real-time control of regular automated production using master recipe
CN103377085B (zh) * 2012-04-12 2017-04-19 无锡江南计算技术研究所 指令管理方法及装置、指令管理系统、运算核心
US9612587B2 (en) 2014-02-11 2017-04-04 Honeywell International Inc. Mobile extension for industrial operator consoles
US9875106B2 (en) * 2014-11-12 2018-01-23 Mill Computing, Inc. Computer processor employing instruction block exit prediction
US10387158B2 (en) 2014-12-24 2019-08-20 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10061589B2 (en) * 2014-12-24 2018-08-28 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10303525B2 (en) 2014-12-24 2019-05-28 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10387156B2 (en) 2014-12-24 2019-08-20 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10061583B2 (en) 2014-12-24 2018-08-28 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10942744B2 (en) 2014-12-24 2021-03-09 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US9785442B2 (en) 2014-12-24 2017-10-10 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US9940136B2 (en) 2015-06-26 2018-04-10 Microsoft Technology Licensing, Llc Reuse of decoded instructions
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10346168B2 (en) * 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US20160378488A1 (en) * 2015-06-26 2016-12-29 Microsoft Technology Licensing, Llc Access to target address
US10678544B2 (en) 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
US10871967B2 (en) 2015-09-19 2020-12-22 Microsoft Technology Licensing, Llc Register read/write ordering
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10095519B2 (en) 2015-09-19 2018-10-09 Microsoft Technology Licensing, Llc Instruction block address register
WO2017048645A1 (en) * 2015-09-19 2017-03-23 Microsoft Technology Licensing, Llc Multimodal targets in a block-based processor
US11977891B2 (en) 2015-09-19 2024-05-07 Microsoft Technology Licensing, Llc Implicit program order
US10936316B2 (en) 2015-09-19 2021-03-02 Microsoft Technology Licensing, Llc Dense read encoding for dataflow ISA
US11531552B2 (en) * 2017-02-06 2022-12-20 Microsoft Technology Licensing, Llc Executing multiple programs simultaneously on a processor core

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US4807115A (en) 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
US5031096A (en) * 1988-06-30 1991-07-09 International Business Machines Corporation Method and apparatus for compressing the execution time of an instruction stream executing in a pipelined processor
US5051885A (en) 1988-10-07 1991-09-24 Hewlett-Packard Company Data processing system for concurrent dispatch of instructions to multiple functional units
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5129067A (en) 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
GB9027853D0 (en) * 1990-12-21 1991-02-13 Inmos Ltd Multiple instruction issue
JP2779557B2 (ja) * 1991-07-09 1998-07-23 三菱電機株式会社 並列演算処理装置

Also Published As

Publication number Publication date
DE69327688D1 (de) 2000-03-02
EP0583089A2 (en) 1994-02-16
DE69327688T2 (de) 2000-09-07
JPH06161753A (ja) 1994-06-10
EP0583089B1 (en) 2000-01-26
US6279101B1 (en) 2001-08-21
EP0583089A3 (es) 1994-08-03

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