ES2134263T3 - Arquitectura de memoria intermedia visual en cuadro. - Google Patents

Arquitectura de memoria intermedia visual en cuadro.

Info

Publication number
ES2134263T3
ES2134263T3 ES93912078T ES93912078T ES2134263T3 ES 2134263 T3 ES2134263 T3 ES 2134263T3 ES 93912078 T ES93912078 T ES 93912078T ES 93912078 T ES93912078 T ES 93912078T ES 2134263 T3 ES2134263 T3 ES 2134263T3
Authority
ES
Spain
Prior art keywords
storage media
visual data
bus
format
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93912078T
Other languages
English (en)
Inventor
Louis A Lippincott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ES2134263T3 publication Critical patent/ES2134263T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/44504—Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
    • G09G2340/125—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels wherein one of the images is motion video
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Digital Computer Display Output (AREA)

Abstract

SE PRESENTA UN APARATO PARA PROCESAR DATOS VISUALES DOTADO DE UN PRIMER MEDIO DE ALMACENAMIENTO PARA ALMACENAR UN PRIMER PLANO DE BITS DE DATOS VISUALES EN UN PRIMER FORMATO. UN PRIMER GRAFICO SE ACOPLA AL MEDIO DE ALMACENAMIENTO POR UN BUS DE DATOS Y A TRAVES DE UN BUS DE ALMACENAMIENTO. TAMBIEN SE PREVE UN MEDIOS PARA RECIBIR UN SEGUNDO MEDIO DE ALMACENAMIENTO PARA ALMACENAR UN SEGUNDO PLANO DE BITS DE DATOS VISUALES EN UN SEGUNDO FORMATO DIFERENTE DEL PRIMER FORMATO.EL MEDIO DE RECEPCION SE ADAPTA PARA ACOPLAR UN MEDIO DE DATOS VISUALES AL CONTROLADOR GRAFICO POR UN BUS DE DATOS Y A TRAVES DE UN BUS DE ALMACENAMIENTO. TAMBIEN SE INCLUYEN MEDIOS PARA FORMAR UNA CORRIENTE DE PIXELS FUSIONADOS A PARTIR DE DATOS VISUALES ALMACENADOS SOBRE EL PRIMER Y SEGUNDO MEDIOS DE ALMACENAMIENTO. SE PREVEN MEDIOS, ACOPLADOS AL CONTROLADOR GRAFICO PARA VISUALIZAR LA CORRIENTE DE PIXELS FUSIONADOS. EN UNA REALIZACION AIDICIONAL, ESTA COMPRENDIDO UN APARATO PARA PROCESAR DATOS VISUALES DE UN PRIMER MEDIO DEALMACENAMIENTO PARA ALMACENAR UN PRIMER LADO DE BITS DE DATOS VISUALES EN UN PRIMER FORMATO. UN CONTROLADO GRAFICO SE ACOPLA AL PRIMER MEDIO DE ALMACENAMIENTO POR UN BUS DE DATOS Y A TRAVES DE UN BUS DE ALMACENAMIENTO. SE PREVE UN SEGUNDO MEDIO DE ALMACENAMIENTO ACOPLADO AL CONTROLADOR GRAFICO POR UN BUS DE DATOS Y A TRAVES DE UN BUS DE ALMACENAMIENTO PARA ALMACENAR UN SEGUNDO PLANO DE BITS DE DATOS VISUALES EN UN SEGUNDO FORMATO DISTINTO DEL PRIMER FORMATO. TAMBIEN SE INCLUYE UN MEDIO PARA FORMAR UNA CORRIENTE DE PIXELS FUSIONADOS DE DATOS VISUALES ALMACENADOS SOBRE EL PRIMER Y EL SEGUNDO MEDIO DE ALMACENAMIENTO. SE PREVEN MEDIOS, ACOPLADOS AL CONTROLADOR GRAFICO PARA VISUALIZAR LA CORRIENTE DE PIXELS FUSIONADOS.
ES93912078T 1992-04-17 1993-03-24 Arquitectura de memoria intermedia visual en cuadro. Expired - Lifetime ES2134263T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87056492A 1992-04-17 1992-04-17

Publications (1)

Publication Number Publication Date
ES2134263T3 true ES2134263T3 (es) 1999-10-01

Family

ID=25355665

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93912078T Expired - Lifetime ES2134263T3 (es) 1992-04-17 1993-03-24 Arquitectura de memoria intermedia visual en cuadro.

Country Status (8)

Country Link
US (2) US5546531A (es)
EP (1) EP0656142B1 (es)
JP (1) JPH08502150A (es)
AU (1) AU4276493A (es)
CA (1) CA2118131C (es)
DE (1) DE69325377T2 (es)
ES (1) ES2134263T3 (es)
WO (1) WO1993021623A1 (es)

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US5345554A (en) * 1992-04-17 1994-09-06 Intel Corporation Visual frame buffer architecture
US6417859B1 (en) * 1992-06-30 2002-07-09 Discovision Associates Method and apparatus for displaying video data
US5890190A (en) * 1992-12-31 1999-03-30 Intel Corporation Frame buffer for storing graphics and video data
US5534942A (en) * 1994-06-17 1996-07-09 Thomson Consumer Electronics, Inc. On screen display arrangement for digital video signal processing system
US5489947A (en) * 1994-06-17 1996-02-06 Thomson Consumer Electronics, Inc. On screen display arrangement for a digital video signal processing system
US5598525A (en) 1995-01-23 1997-01-28 Cirrus Logic, Inc. Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems
JP3558648B2 (ja) * 1995-08-22 2004-08-25 トムソン コンシユーマ エレクトロニクス インコーポレイテツド オンスクリーン表示システム
US6812930B1 (en) * 1996-05-10 2004-11-02 Apple Computer, Inc. Transparent compatibility and adaptation to differing format implementations in a computer system
US6195078B1 (en) 1996-08-21 2001-02-27 Thomson Licensing S.A. Parallel mode on-screen display system
US6011538A (en) * 1997-06-18 2000-01-04 Paradise Electronics, Inc. Method and apparatus for displaying images when an analog-to-digital converter in a digital display unit is unable to sample an analog display signal at a desired high sampling frequency
US6618048B1 (en) 1999-10-28 2003-09-09 Nintendo Co., Ltd. 3D graphics rendering system for performing Z value clamping in near-Z range to maximize scene resolution of visually important Z components
US6717577B1 (en) 1999-10-28 2004-04-06 Nintendo Co., Ltd. Vertex cache for 3D computer graphics
US7538772B1 (en) 2000-08-23 2009-05-26 Nintendo Co., Ltd. Graphics processing system with enhanced memory controller
US6707458B1 (en) 2000-08-23 2004-03-16 Nintendo Co., Ltd. Method and apparatus for texture tiling in a graphics system
US6811489B1 (en) 2000-08-23 2004-11-02 Nintendo Co., Ltd. Controller interface for a graphics system
US7196710B1 (en) 2000-08-23 2007-03-27 Nintendo Co., Ltd. Method and apparatus for buffering graphics data in a graphics system
US6636214B1 (en) 2000-08-23 2003-10-21 Nintendo Co., Ltd. Method and apparatus for dynamically reconfiguring the order of hidden surface processing based on rendering mode
US6700586B1 (en) 2000-08-23 2004-03-02 Nintendo Co., Ltd. Low cost graphics with stitching processing hardware support for skeletal animation
US6937245B1 (en) 2000-08-23 2005-08-30 Nintendo Co., Ltd. Graphics system with embedded frame buffer having reconfigurable pixel formats
US7576748B2 (en) * 2000-11-28 2009-08-18 Nintendo Co. Ltd. Graphics system with embedded frame butter having reconfigurable pixel formats
US7551323B2 (en) * 2003-04-16 2009-06-23 Lexmark International, Inc. Systems and methods for error diffusion
GB2418095B (en) * 2003-05-13 2006-10-25 Electronic Arts Inc Representing colors in stored images using color tinting

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US4494144A (en) * 1982-06-28 1985-01-15 At&T Bell Laboratories Reduced bandwidth video transmission
JPH0690596B2 (ja) * 1985-04-30 1994-11-14 日本電装株式会社 電子地図表示装置
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Also Published As

Publication number Publication date
JPH08502150A (ja) 1996-03-05
US5546531A (en) 1996-08-13
CA2118131A1 (en) 1993-10-28
WO1993021623A1 (en) 1993-10-28
CA2118131C (en) 1999-03-23
US5914729A (en) 1999-06-22
DE69325377T2 (de) 1999-11-18
EP0656142B1 (en) 1999-06-16
EP0656142A1 (en) 1995-06-07
DE69325377D1 (de) 1999-07-22
AU4276493A (en) 1993-11-18

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