ES2111523T3 - Sistema y circuito para calcular una transformacion discreta bidimensional. - Google Patents
Sistema y circuito para calcular una transformacion discreta bidimensional.Info
- Publication number
- ES2111523T3 ES2111523T3 ES90110138T ES90110138T ES2111523T3 ES 2111523 T3 ES2111523 T3 ES 2111523T3 ES 90110138 T ES90110138 T ES 90110138T ES 90110138 T ES90110138 T ES 90110138T ES 2111523 T3 ES2111523 T3 ES 2111523T3
- Authority
- ES
- Spain
- Prior art keywords
- words
- input
- output
- represented
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
Abstract
EL INVENTO ACTUAL SE REFIERE A UN SISTEMA PARA CALCULAR LA DCT DE LA DIMENSION M*M CON LA PROPIEDAD DE SER ORTOGONAL Y SEPARABLE BAJO LA FORMA DE DOS TRANSFORMADAS MONODIMENSIONALES CALCULADAS MEDIANTE UN ALGORITMO RAPIDO, POR LA OPERACION SOBRE LAS PALABRAS DE ENTRADA Y SALIDA, QUE ESTAN DISPUESTAS EN FORMA DE BITS PARALELOS, Y POR OPERACION SOBRE LOS DATOS INTERNOS AL SISTEMA SOBRE LAS PALABRAS REPRESENTADAS POR MEDIO DE 2 MBITS. DE ACUERDO A UNA CARACTERISTICA DEL INVENTO, LAS OPERACIONES DE SUMA Y RESTA ENTRE DATOS VARIABLES Y LAS OPERACIONES DE MULTIPLICACION MEDIANTE LOS DATOS VARIABLES QUE USAN COEFICIENTES FIJOS SE REALIZAN SOBRE LOS DATOS REPRESENTADOS EN LA FORMA DE PAREJAS M DE BITS SERIALIZADOS, DE FORMA QUE LA VELOCIDAD DE LAS PALABRAS DE ENTRADA Y SALIDA, EN FORMA DE PALABRAS POR BITS PARALELOS, SEA IGUAL A LA VELOCIDAD DE LAS PAREJAS DE BIT QUE REPRESENTAN LOS DATOS INTERNOS. UN CIRCUITO PUESTO EN EJECUCION SOBRE BASES DE SILICIO PARA LA EJECUCION DE ESTE SISTEMA INCLUYE AL MENOS: RA PALABRAS DE ENTRADA PARA LA CONVERSION DESDE LA FORMA DE BITS PARALELOS A LA FORMA DE PALABRAS REPRESENTADAS POR MEDIO DE PAREJAS DE BIT EN SERIE PARA LAS PALABRAS DE ENTRADA Y VICEVERSA PARA LAS PALABRAS DE SALIDA ANSFORMADA MONODIMENSIONAL DCT OLUMNAS. AL - UN DISPOSITIVO DE ESCALAMIENTO PARA PALABRAS DE SALIDA.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT8921420U IT8921420V0 (it) | 1989-07-13 | 1989-07-13 | Sistema e circuito per il calcolo di trasformata discreta bidimensionale. |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2111523T3 true ES2111523T3 (es) | 1998-03-16 |
Family
ID=11181511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES90110138T Expired - Lifetime ES2111523T3 (es) | 1989-07-13 | 1990-05-29 | Sistema y circuito para calcular una transformacion discreta bidimensional. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5197021A (es) |
EP (1) | EP0412252B1 (es) |
JP (1) | JPH03165192A (es) |
DE (1) | DE69031674T2 (es) |
ES (1) | ES2111523T3 (es) |
IT (1) | IT8921420V0 (es) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6336180B1 (en) | 1997-04-30 | 2002-01-01 | Canon Kabushiki Kaisha | Method, apparatus and system for managing virtual memory with virtual-physical mapping |
US5664028A (en) * | 1990-04-19 | 1997-09-02 | Ricoh Corporation | Apparatus and method for compressing still images |
US5319724A (en) * | 1990-04-19 | 1994-06-07 | Ricoh Corporation | Apparatus and method for compressing still images |
FR2680259A1 (fr) * | 1991-10-09 | 1993-02-12 | Ricoh Kk | Appareil et procede de compression d'image. |
US5410500A (en) * | 1992-02-21 | 1995-04-25 | Sony Corporation | Discrete cosine transform apparatus and inverse discrete cosine transform apparatus |
US5313579A (en) * | 1992-06-04 | 1994-05-17 | Bell Communications Research, Inc. | B-ISDN sequencer chip device |
US5654910A (en) * | 1992-08-26 | 1997-08-05 | Sony Corporation | Processing method and apparatus for performing 4 ×4 discrete cosine transformation or inverse discrete cosing transformation |
US5420811A (en) * | 1992-08-26 | 1995-05-30 | Sony Corporation | Simple quick image processing apparatus for performing a discrete cosine transformation or an inverse discrete cosine transformation |
JPH06103301A (ja) * | 1992-09-17 | 1994-04-15 | Sony Corp | 8x8離散コサイン変換回路および8x8離散コサイン逆変換回路 |
JPH06149862A (ja) * | 1992-11-13 | 1994-05-31 | Sony Corp | 行列データ乗算方法及び行列データ乗算装置 |
US5345408A (en) * | 1993-04-19 | 1994-09-06 | Gi Corporation | Inverse discrete cosine transform processor |
GB2302421B (en) * | 1995-03-18 | 1999-11-03 | United Microelectronics Corp | Apparatus for two-dimensional inverse discrete cosine transform |
US5671169A (en) * | 1995-06-23 | 1997-09-23 | United Microelectronics Corporation | Apparatus for two-dimensional inverse discrete cosine transform |
US5867601A (en) * | 1995-10-20 | 1999-02-02 | Matsushita Electric Corporation Of America | Inverse discrete cosine transform processor using parallel processing |
US5805482A (en) * | 1995-10-20 | 1998-09-08 | Matsushita Electric Corporation Of America | Inverse discrete cosine transform processor having optimum input structure |
US5801979A (en) * | 1995-10-20 | 1998-09-01 | Matsushita Electric Corporation Of America | Carry logic that produces a carry value from NLSBs for a ROM accumulator in an inverse discrete cosine transform processor |
AUPO648397A0 (en) | 1997-04-30 | 1997-05-22 | Canon Information Systems Research Australia Pty Ltd | Improvements in multiprocessor architecture operation |
US6707463B1 (en) | 1997-04-30 | 2004-03-16 | Canon Kabushiki Kaisha | Data normalization technique |
US6414687B1 (en) | 1997-04-30 | 2002-07-02 | Canon Kabushiki Kaisha | Register setting-micro programming system |
AUPO647997A0 (en) * | 1997-04-30 | 1997-05-22 | Canon Information Systems Research Australia Pty Ltd | Memory controller architecture |
US6272257B1 (en) | 1997-04-30 | 2001-08-07 | Canon Kabushiki Kaisha | Decoder of variable length codes |
US6289138B1 (en) | 1997-04-30 | 2001-09-11 | Canon Kabushiki Kaisha | General image processor |
US6061749A (en) * | 1997-04-30 | 2000-05-09 | Canon Kabushiki Kaisha | Transformation of a first dataword received from a FIFO into an input register and subsequent dataword from the FIFO into a normalized output dataword |
US6499045B1 (en) * | 1999-10-21 | 2002-12-24 | Xilinx, Inc. | Implementation of a two-dimensional wavelet transform |
US6684235B1 (en) | 2000-11-28 | 2004-01-27 | Xilinx, Inc. | One-dimensional wavelet system and method |
JP3830497B2 (ja) | 2004-06-11 | 2006-10-04 | シャープ株式会社 | 半導体ウエハの製造方法及び半導体装置の製造方法 |
GB2452103B (en) * | 2007-01-05 | 2011-08-31 | Arthrocare Corp | Electrosurgical system with suction control apparatus and system |
US8654833B2 (en) * | 2007-09-26 | 2014-02-18 | Qualcomm Incorporated | Efficient transformation techniques for video coding |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4196448A (en) * | 1978-05-15 | 1980-04-01 | The United States Of America As Represented By The Secretary Of The Navy | TV bandwidth reduction system using a hybrid discrete cosine DPCM |
US4385363A (en) * | 1978-12-15 | 1983-05-24 | Compression Labs, Inc. | Discrete cosine transformer |
US4293920A (en) * | 1979-09-04 | 1981-10-06 | Merola Pasquale A | Two-dimensional transform processor |
US4449194A (en) * | 1981-09-25 | 1984-05-15 | Motorola Inc. | Multiple point, discrete cosine processor |
FR2561011B1 (fr) * | 1984-03-09 | 1986-09-12 | Cit Alcatel | Processeur de calcul d'une transformee discrete inverse du cosinus |
IT1207346B (it) * | 1987-01-20 | 1989-05-17 | Cselt Centro Studi Lab Telecom | Sformata coseno discreta a coeffi circuito per il calcolo della tra cienti quantizzati di campioni di segnale numerico |
US4791598A (en) * | 1987-03-24 | 1988-12-13 | Bell Communications Research, Inc. | Two-dimensional discrete cosine transform processor |
-
1989
- 1989-07-13 IT IT8921420U patent/IT8921420V0/it unknown
-
1990
- 1990-05-29 DE DE69031674T patent/DE69031674T2/de not_active Expired - Fee Related
- 1990-05-29 ES ES90110138T patent/ES2111523T3/es not_active Expired - Lifetime
- 1990-05-29 EP EP90110138A patent/EP0412252B1/en not_active Expired - Lifetime
- 1990-07-11 US US07/551,628 patent/US5197021A/en not_active Expired - Fee Related
- 1990-07-13 JP JP2184397A patent/JPH03165192A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH03165192A (ja) | 1991-07-17 |
IT8921420V0 (it) | 1989-07-13 |
DE69031674T2 (de) | 1998-06-10 |
EP0412252A3 (en) | 1991-07-31 |
DE69031674D1 (de) | 1997-12-11 |
EP0412252B1 (en) | 1997-11-05 |
US5197021A (en) | 1993-03-23 |
EP0412252A2 (en) | 1991-02-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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