ES2037054T3 - Circuito para evitar el bloqueo de solicitudes de alta prioridad dirigidas a un controlador de sistema de tratamiento de datos. - Google Patents

Circuito para evitar el bloqueo de solicitudes de alta prioridad dirigidas a un controlador de sistema de tratamiento de datos.

Info

Publication number
ES2037054T3
ES2037054T3 ES198787115018T ES87115018T ES2037054T3 ES 2037054 T3 ES2037054 T3 ES 2037054T3 ES 198787115018 T ES198787115018 T ES 198787115018T ES 87115018 T ES87115018 T ES 87115018T ES 2037054 T3 ES2037054 T3 ES 2037054T3
Authority
ES
Spain
Prior art keywords
high priority
circuit
system controller
access
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198787115018T
Other languages
English (en)
Inventor
Robert Jerome Koegel
Leonard Rabins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Application granted granted Critical
Publication of ES2037054T3 publication Critical patent/ES2037054T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)

Abstract

EL BLOQUEO QUE DEPENDE DE LAS PETICIONES DE UNA MAYOR ALTA PRIORIDAD A UN CONTROLADOR DE SISTEMA SE EVITA MEDIANTE UN CIRCUITO QUE COMPRENDE UN ELEMENTO CONTADOR PARA CONTAR EL NUMERO DE VECES QUE LA PETICION DE MAYOR PRIORIDAD NO HA CONSEGUIDO EL ACCESO. LA CUENTA DA LUGAR A UN VALOR DE CUENTA QUE SE ALMACENA TEMPORALMENTE EN EL ELEMENTO CONTADOR. UN ELEMENTO DE COMPARACION COMPARA EL VALOR DE CUENTA CON UN PREDETERMINADO VALOR, DICHO VALOR PREDETERMINADO ES UN NUMERO PREDETERMINADO DE VECES QUE EL SISTEMA DE PROCESAMIENTO DE DATOS PERMITIRA DESPRECIAR LA PETICION DE ALTA PRIORIDAD MAYOR. UNA SEÑAL DE CONTROL SE EMITE DESDE EL ELEMENTO DE COMPARACION CUANDO EL VALOR DE LA CUENTA ES IGUAL AL VALOR PREDETERMINADO Y DICHA SEÑAL SE ACOPLA A CADA PUERTO PARA IMPEDIR QUE CUALQUIER OTRA PETICION DE ACCESO DEL EQUIPO SEA ACEPTADA POR EL CONTROLADOR DEL SISTEMA. EL CIRCUITO TAMBIEN INCLUYE UN ELEMENTO DE BARRERA PARA MANTENER LA SEÑAL DE CONTROL CUANDO SE DETERMINA QUE UNA PETICION DE ALTA PRIORIDAD SUBSECUENTE QUE HAYA CONSEGUIDO ACCESO NO ES LA PETICION DE ALTA PRIORIDAD MAYOR, LA SEÑAL DE CONTROL SE MANTIENE HASTA QUE TODAS LAS PETICIONES DE ALTA PRIORIDAD PENDIENTES HAN CONSEGUDIO EL ACCESO.
ES198787115018T 1986-09-02 1987-10-14 Circuito para evitar el bloqueo de solicitudes de alta prioridad dirigidas a un controlador de sistema de tratamiento de datos. Expired - Lifetime ES2037054T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/902,545 US4821177A (en) 1986-09-02 1986-09-02 Apparatus for controlling system accesses having multiple command level conditional rotational multiple port servicing priority hierarchy

Publications (1)

Publication Number Publication Date
ES2037054T3 true ES2037054T3 (es) 1993-06-16

Family

ID=25416004

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198787115018T Expired - Lifetime ES2037054T3 (es) 1986-09-02 1987-10-14 Circuito para evitar el bloqueo de solicitudes de alta prioridad dirigidas a un controlador de sistema de tratamiento de datos.

Country Status (4)

Country Link
US (1) US4821177A (es)
EP (1) EP0311704B1 (es)
DE (1) DE3783370T2 (es)
ES (1) ES2037054T3 (es)

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US5051946A (en) * 1986-07-03 1991-09-24 Unisys Corporation Integrated scannable rotational priority network apparatus
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US5095460A (en) * 1989-04-25 1992-03-10 Digital Equipment Corporation Rotating priority encoder operating by selectively masking input signals to a fixed priority encoder
US5247671A (en) * 1990-02-14 1993-09-21 International Business Machines Corporation Scalable schedules for serial communications controller in data processing systems
CA2080608A1 (en) * 1992-01-02 1993-07-03 Nader Amini Bus control logic for computer system having dual bus architecture
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
JPH06161873A (ja) * 1992-11-27 1994-06-10 Fujitsu Ltd 主記憶に対する複数のアクセスポイントのハングアップ処理方式
US5673415A (en) * 1993-12-03 1997-09-30 Unisys Corporation High speed two-port interface unit where read commands suspend partially executed write commands
US5781927A (en) * 1996-01-30 1998-07-14 United Microelectronics Corporation Main memory arbitration with priority scheduling capability including multiple priorty signal connections
US5860082A (en) * 1996-03-28 1999-01-12 Datalight, Inc. Method and apparatus for allocating storage in a flash memory
US8819744B1 (en) * 1998-03-11 2014-08-26 The Directv Group, Inc. Miniature wireless audio/video/data distribution and access system
JPH11272560A (ja) * 1998-03-19 1999-10-08 Sony Corp 集積回路
US20050132145A1 (en) * 2003-12-15 2005-06-16 Finisar Corporation Contingent processor time division multiple access of memory in a multi-processor system to allow supplemental memory consumer access
JP4830379B2 (ja) * 2005-07-13 2011-12-07 ソニー株式会社 情報処理装置、情報処理方法、およびプログラム
WO2007045051A1 (en) 2005-10-21 2007-04-26 Honeywell Limited An authorisation system and a method of authorisation
WO2008144804A1 (en) * 2007-05-28 2008-12-04 Honeywell International Inc Systems and methods for commissioning access control devices
US8351350B2 (en) * 2007-05-28 2013-01-08 Honeywell International Inc. Systems and methods for configuring access control devices
WO2009094731A1 (en) * 2008-01-30 2009-08-06 Honeywell International Inc. Systems and methods for managing building services
WO2009158582A2 (en) * 2008-06-27 2009-12-30 Greatpoint Energy, Inc. Four-train catalytic gasification systems
WO2010039598A2 (en) 2008-09-30 2010-04-08 Honeywell International Inc. Systems and methods for interacting with access control devices
US8878931B2 (en) 2009-03-04 2014-11-04 Honeywell International Inc. Systems and methods for managing video data
EP2408984B1 (en) 2009-03-19 2019-11-27 Honeywell International Inc. Systems and methods for managing access control devices
US9280365B2 (en) * 2009-12-17 2016-03-08 Honeywell International Inc. Systems and methods for managing configuration data at disconnected remote devices
US8707414B2 (en) * 2010-01-07 2014-04-22 Honeywell International Inc. Systems and methods for location aware access control management
US8787725B2 (en) 2010-11-11 2014-07-22 Honeywell International Inc. Systems and methods for managing video data
US9927788B2 (en) * 2011-05-19 2018-03-27 Fisher-Rosemount Systems, Inc. Software lockout coordination between a process control system and an asset management system
US9894261B2 (en) 2011-06-24 2018-02-13 Honeywell International Inc. Systems and methods for presenting digital video management system information via a user-customizable hierarchical tree interface
WO2013020165A2 (en) 2011-08-05 2013-02-14 HONEYWELL INTERNATIONAL INC. Attn: Patent Services Systems and methods for managing video data
US10362273B2 (en) 2011-08-05 2019-07-23 Honeywell International Inc. Systems and methods for managing video data
US9344684B2 (en) 2011-08-05 2016-05-17 Honeywell International Inc. Systems and methods configured to enable content sharing between client terminals of a digital video management system
US10523903B2 (en) 2013-10-30 2019-12-31 Honeywell International Inc. Computer implemented systems frameworks and methods configured for enabling review of incident data

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
GB1248681A (en) * 1969-01-08 1971-10-06 Int Computers Ltd Improvements in or relating to digital electrical information processing apparatus
US4400771A (en) * 1975-12-04 1983-08-23 Tokyo Shibaura Electric Co., Ltd. Multi-processor system with programmable memory-access priority control
US4035780A (en) * 1976-05-21 1977-07-12 Honeywell Information Systems, Inc. Priority interrupt logic circuits
US4130864A (en) * 1976-10-29 1978-12-19 Westinghouse Electric Corp. Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
US4080649A (en) * 1976-12-16 1978-03-21 Honeywell Information Systems Inc. Balancing the utilization of I/O system processors
US4228500A (en) * 1978-03-27 1980-10-14 Honeywell Information Systems Inc. Command stacking apparatus for use in a memory controller
US4470111A (en) * 1979-10-01 1984-09-04 Ncr Corporation Priority interrupt controller
US4363096A (en) * 1980-06-26 1982-12-07 Gte Automatic Electric Labs Inc. Arbitration controller providing for access of a common resource by a duplex plurality of central processing units
US4385382A (en) * 1980-09-29 1983-05-24 Honeywell Information Systems Inc. Communication multiplexer having a variable priority scheme using a read only memory
US4480314A (en) * 1982-05-17 1984-10-30 International Business Machines Corporation Method for optimizing printer response time for a key to print operation
US4675812A (en) * 1983-02-14 1987-06-23 International Business Machines Corp. Priority circuit for channel subsystem having components with diverse and changing requirement for system resources
US4682282A (en) * 1984-10-25 1987-07-21 Unisys Corp. Minimum latency tie-breaking arbitration logic circuitry

Also Published As

Publication number Publication date
EP0311704A1 (en) 1989-04-19
EP0311704B1 (en) 1992-12-30
DE3783370T2 (de) 1993-04-15
US4821177A (en) 1989-04-11
DE3783370D1 (de) 1993-02-11

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