ES2036453B1 - TEST STRUCTURE FOR THE CHARACTERIZATION OF THE LATCH-UP IN CMO5 CIRCUITS. - Google Patents

TEST STRUCTURE FOR THE CHARACTERIZATION OF THE LATCH-UP IN CMO5 CIRCUITS.

Info

Publication number
ES2036453B1
ES2036453B1 ES9101476A ES9101476A ES2036453B1 ES 2036453 B1 ES2036453 B1 ES 2036453B1 ES 9101476 A ES9101476 A ES 9101476A ES 9101476 A ES9101476 A ES 9101476A ES 2036453 B1 ES2036453 B1 ES 2036453B1
Authority
ES
Spain
Prior art keywords
characterization
latch
cmos
circuits
test structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
ES9101476A
Other languages
Spanish (es)
Other versions
ES2036453R (en
ES2036453A2 (en
Inventor
C Cane
M Lozano
I Gracia
C Perello
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Consejo Superior de Investigaciones Cientificas CSIC
Original Assignee
Consejo Superior de Investigaciones Cientificas CSIC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consejo Superior de Investigaciones Cientificas CSIC filed Critical Consejo Superior de Investigaciones Cientificas CSIC
Priority to ES9101476A priority Critical patent/ES2036453B1/en
Publication of ES2036453A2 publication Critical patent/ES2036453A2/en
Publication of ES2036453R publication Critical patent/ES2036453R/es
Application granted granted Critical
Publication of ES2036453B1 publication Critical patent/ES2036453B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

LA ESTRUCTURA DE TEST PARA LA CARACTERIZACION DEL LASTCH-UP EN CIRCUITOS CMOS EN UN DISPOSITIVO QUE PERMITE LA DETERMINACION EN LA SENSIBILIDAD DE DISTINTAS GEOMETRIAS Y PROCESOS TECNOLOGICOS AL FENOMENO INDESEADO CONOCIDO POR LATCH-UP. MEDIANTE LA COMBINACION DE UN DISPOSITICO P-N-P-N SENSIBLE, UNA CAPACIDAD CMOS Y UNA RESISTENCIA INTEGRADA SE CONSIGUE IMPLEMENTAR UN OSCILADOR ASTABLE CUYA SEÑAL DE SALIDA PERMITE OBTENER DIRECTAMENTE LOS PARAMETROS CARACTERISTICOS LATCH-UP SIMPLEMENTE VISUALIZANDOLA MEDIANTE UN OSCILOSCOPIO ANALOGICO O DIGITAL. LA ESTRUCTURA PUEDE IMPLEMENTARSE EN CUALQUIER TECNOLOGIA CMOS LSI O VLSI, POR SUPERPOSICION DE UN MINIMO DE NUEVE NIVELES DE MASCARA CON UN DISEÑO TIPICO COMO EL PRESENTADO. LA APLICACION ES DENTRO DEL MUNDO DE LA INDUSTRIA MICROELECTRONICA.THE TEST STRUCTURE FOR THE CHARACTERIZATION OF LASTCH-UP IN CMOS CIRCUITS IN A DEVICE THAT ALLOWS THE DETERMINATION IN THE SENSITIVITY OF DIFFERENT GEOMETRIES AND TECHNOLOGICAL PROCESSES KNOWN BY LATCH-UP. THROUGH THE COMBINATION OF A SENSITIVE P-N-P-N DEVICE, A CMOS CAPACITY AND AN INTEGRATED RESISTANCE, IT IS POSSIBLE TO IMPLEMENT AN ASTABLE OSCILLATOR WHOSE OUTPUT SIGNAL ALLOWS ANY SINGLE-SIZED, SIMILAR, LOWCH-UP, SIMULAR PARAMETERS. THE STRUCTURE CAN BE IMPLEMENTED IN ANY CMOS LSI OR VLSI TECHNOLOGY, BY OVERLAPPING A MINIMUM OF NINE LEVELS OF MASK WITH A TYPICAL DESIGN AS PRESENTED. THE APPLICATION IS WITHIN THE WORLD OF THE MICROELECTRONIC INDUSTRY.

ES9101476A 1991-06-21 1991-06-21 TEST STRUCTURE FOR THE CHARACTERIZATION OF THE LATCH-UP IN CMO5 CIRCUITS. Expired - Fee Related ES2036453B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES9101476A ES2036453B1 (en) 1991-06-21 1991-06-21 TEST STRUCTURE FOR THE CHARACTERIZATION OF THE LATCH-UP IN CMO5 CIRCUITS.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9101476A ES2036453B1 (en) 1991-06-21 1991-06-21 TEST STRUCTURE FOR THE CHARACTERIZATION OF THE LATCH-UP IN CMO5 CIRCUITS.

Publications (3)

Publication Number Publication Date
ES2036453A2 ES2036453A2 (en) 1993-05-16
ES2036453R ES2036453R (en) 1995-05-16
ES2036453B1 true ES2036453B1 (en) 1995-12-16

Family

ID=8272762

Family Applications (1)

Application Number Title Priority Date Filing Date
ES9101476A Expired - Fee Related ES2036453B1 (en) 1991-06-21 1991-06-21 TEST STRUCTURE FOR THE CHARACTERIZATION OF THE LATCH-UP IN CMO5 CIRCUITS.

Country Status (1)

Country Link
ES (1) ES2036453B1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030829A (en) * 1988-06-08 1991-07-09 Siemens Aktiengesellschaft Method and apparatus for investigating latch-up propagation in complementary-metal-oxide-semiconductor (CMOS) circuits
US5012100A (en) * 1988-06-08 1991-04-30 Siemens Aktiengesellschaft Method and apparatus for investigating the latch-up propagation in complementary-metal-oxide semiconductor (CMOS) circuits
EP0382865A1 (en) * 1989-02-14 1990-08-22 Siemens Aktiengesellschaft Arrangement to reduce latch-up sensitivity in CMOS semiconductor circuits

Also Published As

Publication number Publication date
ES2036453R (en) 1995-05-16
ES2036453A2 (en) 1993-05-16

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20000707