EP4632719A1

EP4632719A1 - Timing controller for minimizing power consumption during blank period

Info

Publication number: EP4632719A1
Application number: EP23901045.7A
Authority: EP
Inventors: Sang Dae Choi
Original assignee: LX Semicon Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2022-12-07
Filing date: 2023-12-05
Publication date: 2025-10-15
Also published as: CN120359561A; WO2024123026A1; TW202431226A; KR20240085160A

Abstract

The present invention proposes a timing controller capable of minimizing power consumption during a blank period by disabling the operation of a corresponding functional block or a memory device included in the corresponding block during the blank period. The timing controller comprises: a blank period detection circuit for generating a blank period detection signal by using a clock signal and a gate drive signal; and a functional block group comprising a plurality of functional blocks carrying out operations in accordance with a display period and a blank period in response to the gate driving signal, a data driving signal, and the blank period detection signal.

Description

[Technical field]

The present invention relates to a timing controller, and more particularly, to a timing control circuit capable of minimizing power consumption during blank period by deactivating the operation of a functional block included in the timing controller or a memory device included in the corresponding functional block during blank period.

[Background art]

A display device includes a display panel for reproducing an image, a driving unit for driving the display panel, and a timing controller for controlling the operation of the driving unit. Here, the driving unit includes a gate driver for driving a gate line and a data driver formed on the display panel.
The timing controller receives a plurality of control signals and image data from an external driving system (not shown) and generates a main clock signal and a plurality of control signals for controlling the driving unit.
The driving unit processes the image data into a source signal in response to the control signal received from the timing controller and then outputs it to the display panel. At this time, the image data is transmitted from the external driving system and transmitted to the driving unit via the timing controller.
The display panel operates alternately in an active period or display period where the source signal is input and a blank period where the source signal is not input between each active period. During the blank period, the driving unit prevents leakage current of the display panel by supplying a single voltage to the display panel.
Among the multiple function blocks installed in the timing controller, there are function blocks that operate normally during the active period, i.e., the display period, but do not need to operate during the blank period. Among these function blocks, function blocks that have a storage means, i.e., a memory, always operate in an activated state even during the blank period when the function block does not need to operate, which causes unnecessary power consumption.

[Detailed Description of the Invention]

[Technical Problem]

The technical problem that the present invention seeks to solve is to provide a timing controller capable of minimizing power consumption during a blank period by disabling the operation of an internal functional block or a memory device included in the corresponding functional block during a blank period.
Another technical problem that the present invention seeks to solve is to provide a display device including a timing controller capable of minimizing power consumption during a blank period by disabling the operation of an internal functional block or a memory device included in the corresponding functional block during a blank period.

[Technical Solution]

According to one aspect of the present invention for achieving the above technical problem, a timing controller of recovering a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and minimizing power consumption during a blank period, may include: a blank period detection circuit configured to generate a blank period detection signal using the clock signal and the gate driving signal; and a function block group including a plurality of function blocks configured to perform operations in accordance with a display period and the blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal.
According to another aspect of the present invention for achieving the above technical problem, a timing controller of recovering a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and minimizing power consumption during a blank period, may include: a blank period detection circuit that generates a blank period detection signal using the clock signal and the gate driving signal; a power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal; and a function block group including a plurality of function blocks configured to perform operations in response to the gate driving signal, the data driving signal, and the blank period detection signal in accordance with a display period and the blank period.
According to one aspect of the present invention for achieving the above other technical problem, a display device of minimizing power consumption during a blank period, may include: a display panel; a driving unit configured to drive the display panel; and a timing controller including a blank period detection circuit configured to recover a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and generate a blank period detection signal using the clock signal and the gate driving signal, and a function block group including a plurality of function blocks configured to perform operations in accordance with a display period and the blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal, and configured to control an operation of the driving unit.
According to another aspect of the present invention for achieving the above-described other technical problem, a display device may include: a display panel; a driving unit that drives the display panel; and a timing controller including a blank period detection circuit configured to recover a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system, and generate a blank period detection signal using the clock signal and the gate driving signal, a power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal, and, and a functional block group including a plurality of functional blocks configured to perform operations in accordance with a display period and the blank period in response to the gate driving signal, the data driving signal and the power-down control signal, and configured to control an operation of the driving unit.

[Effect of the invention]

The display device according to the present invention, which minimizes power consumption during a blank period as described above, has the advantage of minimizing the power required to drive the display panel by operating the functional block itself and/or the storage means (memory cell) related to the functional block, which normally consumes power during the display period but does not require operation during the blank period, in a power-down mode.

[Brief description of the drawings]

FIG. 1 is an embodiment of a timing controller that minimizes power consumption during a blank period according to the present invention.
FIG. 2 is a time diagram of the operation mode of a display panel according to the type of the display panel.
FIG. 3 illustrates the waveforms of a plurality of power-down control signals applied to a display panel that does not provide a touch panel function.
FIG. 4 illustrates the waveforms of a plurality of power-down control signals applied to an AIT (VBS) display panel.
FIG. 5 illustrates the waveforms of a plurality of power-down control signals applied to an AIT (LHB) display panel.
FIG. 6 illustrates the waveforms of the operation control signal and the power-down control signal of the CABC unit constituting the driving unit driving the display panel that does not provide the touch panel function.

[Best Mode]

FIG. 1 is an example of a timing controller that minimizes power consumption during a blank period according to the present invention.
Referring to FIG. 1, the timing controller 100 that minimizes power consumption during a blank period according to the present invention includes a blank period detection circuit 110, a power-down control signal generation circuit 120, and a function block group 130 including a plurality of function blocks.
The timing controller 100 uses a control signal (CON) received from an external system (not shown) by using a clock signal recovery circuit (not shown) to recover the clock signal (CLK), the gate drive signal (Gate _D), and the data drive signal (DATA_D).
The blank period detection circuit 110 generates a blank period detection signal (BLANK _Dur) using a clock signal (CLK) and a gate drive signal (Gate _D). If the display period is a period in which the source signal is transmitted to the display, the blank period is a period in which the source signal does not transmit the source signal to the display, and this will be described in detail later.
The blank period detection signal (BLANK _Dur) is a signal that is inactive during the display period and activated during the blank period. Here, the activation of the blank period detection signal (BLANK_Dur) means that the blank period detection signal (BLANK_Dur) maintains a voltage level indicating an inactive state and transitions to a voltage level indicating an activated state. For example, when the blank period detection signal (BLANK _Dur) has a logic low value, it is determined to be a display period, and when it transitions to a logic high value, it is determined to be a blank period.
The blank period detection circuit 110 according to the present invention precisely generates the blank period detection signal (BLANK _Dur) so that it is synchronized with the clock signal (CLK) by using the clock signal (CLK) and the gate drive signal (Gate_D). For example, by using a logic circuit such as a NAND gate, it will be possible to generate the blank period detection signal (BLANK_Dur) that is synchronized with the clock signal (CLK) by using the clock signal (CLK) and the gate drive signal (Gate_D).
The power-down control signal generation circuit 120 generates a plurality of power-down control signals (BIST mem_pd, CABC mem_pd, Block1 mem_pd) in response to the blank period detection signal (BLANK_Dur) to cause each of the plurality of function blocks included in the function block group 130 to operate in one of the normal operation mode and the power-down mode, or to cause the memory devices included in the plurality of function blocks to operate in one of the normal operation mode and the power-down mode.
It is preferable to generate the plurality of power-down control signals (BIST mem_pd, CABC mem_pd, Block1 mem_pd) for each of the plurality of function blocks included in the function block group 130. For example, the power-down control signal BIST mem_pd indicates whether the memory device (not shown) included in the BIST execution unit 131 described below operates in the power-down mode.
The function block group 130 includes a plurality of function blocks, and may include, for example, a BIST execution unit 131, a CABC 132, a DGA 133, a DITHER 134, a image quality IP 135, and a plurality of other function blocks 136 to 138.
When operating in a display mode, the gate drive signal (Gate_D) must be activated, and when operating in a blank mode, the gate drive signal (Gate_D) must be deactivated. The present invention proposes to generate a blank period detection signal (BLANK_Dur) that is activated and deactivated in response to the display mode and the blank mode, respectively, from the state of the gate drive signal (Gate_D) using a blank period detection circuit 110.
Here, the normal operation mode means a state in which multiple function blocks included in the function block group 130 and the memory device included in the function block perform their assigned functions while consuming a certain amount of power, and the power-down mode means an operation state in which power consumption is minimized by preventing a specific function block from performing an operation.
The normal operation mode may be an operation state in an active section or a display section, and the power-down mode may be an operation state in a blank section. That is, in the display section operating in the normal operation mode, multiple function blocks constituting the function block group 130 perform normal functions according to the state of the blank section detection signal (BLANK_Dur), or operate at least one function block 131 to 138 in an idle state, or minimize the power consumption of the storage means included in the corresponding function block.
There are various methods for consuming minimum power in power-down mode. For example, power supply to all or part of the relevant function block is cut off, or a circuit is configured to shift the output voltage level of a specific circuit stage constituting the function block to a power-down mode voltage level so that the circuit of a subsequent stage electrically connected to the stage outputting the power-down mode voltage level does not operate. The same applies to a memory device included in the relevant function block so that the memory device included in the relevant function block consumes minimum power.
The function blocks included in the function block group 130 illustrated in FIG. 1 are explained as examples, and the technology of the present invention is not limited thereto. However, to help understanding the technology, the functions of the function blocks illustrated in FIG. 1 are explained as follows.
The BIST execution unit 131 is a function block that can perform a function of testing defects between memory cells using a Built In Self Test (BIST) circuit.
The CABC 132 performs a content-based adaptive control (CABC: Content-based Adaptive Brightness Control) function, which analyzes the original image data to adjust the set gamma curve value and adjusts the brightness of the backlight (LED) to increase the efficiency of power consumption.
The digital gamma control unit 133 generates positive and negative gamma voltages with different values through multiple gamma blocks (not shown), and the gamma voltages are generated according to 256 gray levels.
The DITHER unit 134 performs dithering on image data played on the display (not shown).
The image quality IP 135 is an image processing processor (Image processor) used to improve the image quality of the display panel (not shown).
Other function blocks 136-138 are examples of function blocks that the designer of the timing controller 100 can add as needed.
The above-described multiple function blocks 131-138 have their own storage means necessary for performing the corresponding function or utilize separate storage means, and the test in the BIST execution unit 131 tests for defects between the storage means associated with the multiple function blocks 132-135, i.e., memory cells.
In addition to the simple function of playing back images, the operation of the display panel can provide a means of receiving user touch information. The operation of the display panel can be distinguished as described below, depending on the case where the display panel only plays back images and the case where it performs the function of receiving touch information in parallel.
The display touch panel can be classified into an add-on mode touch panel, an on-cell touch panel, and an in-cell touch panel depending on the configuration. In particular, the in-cell touch panel has the advantage of allowing the thickness of the display module to be thinner and greatly reducing the production cost of the touch panel as the touch electrode of the touch panel is embedded inside the display panel.
Each of the function blocks included in the function block group 130 illustrated in FIG. 1 may be a semiconductor IP capable of circuit or chip layout design that has an independent function and can be reused. When designing System on Chip (SoC) and Field Programmable Gate Array (FPGA) circuits, microprocessors, memories, digital signal processors, analog signal processors, and various input/output circuits may be examples of semiconductor IPs.
FIG. 2 is a time diagram of the operation mode of a display panel according to the type of the display panel.
The display panel can be divided into a display panel that only plays images (Non-AIT) and an Advanced In-cell Touch (AIT) panel (AIT (VBS), and AIT (LHB)). Here, VBS is an abbreviation for Vertical Blank Stretch, and LHB is an abbreviation for Long Horizontal Blank.
Referring to FIG. 2, in the case of a display panel (Non-AIT) that does not provide a touch panel function, the blank period (Blank) per frame is less than 5%, whereas in the case of an AIT display panel (AIT (VBS), AIT (LHB)), the display period: blank period ratio is about 5:5 to 8:2.
Since the power consumption of the timing controller in the blank period of the present invention is minimized, the effect of the present invention will be greater when applied to an AIT display panel (AIT (VBS), AIT (LHB)) than to a display panel (Non-AIT) that does not provide a touch panel function.
The present invention describes a plurality of power-down control signals (BIST mem_pd, CABC mem_pd, Block1 mem_pd) that adaptively correspond to each of the three types of display modes illustrated in FIG. 2, as described below.
FIG. 3 illustrates waveforms of a plurality of power-down control signals applied to a display panel that does not provide a touch panel function.
FIG. 4 illustrates waveforms of a plurality of power-down control signals applied to an AIT (VBS) display panel.
FIG. 5 illustrates waveforms of a plurality of power-down control signals applied to an AIT (LHB) display panel.
Referring to FIGS. 3 to 5, it can be seen that the timing controller 100 according to the present invention operates in the same manner as a conventional display device during the display period (Display), but operates the memory device of a functional block that does not need to operate among a plurality of functional blocks included in the functional block group 130 in a power-down mode during the blank period (Blank), thereby minimizing power consumption during the blank period (Blank).
The technology of the present invention described above minimizes power consumption during the blank period (Blank) by deactivating the memory device included in the functional block that does not need to operate during the blank period (Blank), but depending on the embodiment, it is also possible to further reduce power consumption during the blank period (Blank) by deactivating the operation of the circuit included in the corresponding functional block.
For example, in order to operate the circuit of a functional block including a memory device determined to operate in power-down mode, it is possible to implement it by cutting off the power supplied to the relevant functional block, or, when the relevant functional block is divided into multiple stages, shifting the voltage of the output of the frontmost stage to restrict the operation of the subsequent stages.
In addition, the clock signal provided to the relevant functional block is deactivated during the blank period. For example, it is possible to implement it by maintaining a specific voltage level during the blank period of a clock signal that operates at a certain cycle so that it operates like a DC voltage rather than a clock signal during the blank period.
FIG. 6 illustrates the waveforms of the operation control signal and the power-down control signal of the CABC constituting the driving unit that drives the display panel that does not provide a touch panel function.
The first waveform (Clock_CABC(no)) from above is a clock signal supplied to the internal circuit of a conventional CABC 132 when the present invention is not applied, the second waveform (Clock_CABC(yes)) from above is a clock signal supplied to the internal circuit of a CABC 132 when the present invention is applied, and the third waveform (CABC mem_pd) from above represents a power-down control signal that determines the operation of the internal memory device of the CABC 132 when the present invention is applied.
Referring to FIG. 6, a conventional display device to which the present invention is not applied supplies a clock signal (Clock_CABC) both in the display period (Display) and the blank period (Blank). However, the timing controller 100 to which the present invention is applied supplies a clock signal (Clock_CABC) in the display period (Display) in the same way as a conventional display device, but is different in that it deactivates the clock signal in the blank period (Blank).
In particular, it can be seen that the timing controller 100 applying the present invention allows the memory device included in the CABC 132 to perform the normal function of the storage device during the display period (Display), but causes the memory device included in the CABC 132 to operate in a power-down mode during the blank period (Blank).
For simplicity of explanation, among the multiple display playback modes, a display panel that does not provide a touch panel function is used as an example in FIG. 6, but this can also be applied to the AIT display panel.
In particular, multiple clock signals supplied to each functional block, for example, the clock signal (Clock_CABC(yes)) supplied to CABC 132 is related to the power-down control signal (CABC mem_pd) output from the power-down control signal generation circuit 120, so it can be generated by using a logical combination of the existing clock signal (Clock_CABC(no)) and multiple power-down control signals (BIST mem_pd, CABC mem_pd, Block1 mem_pd).
The clock signal (Clock_CABC(yes)) supplied to CABC 132 can be generated by the power-down control signal generation circuit 120, or it can be generated using a separate functional block.
In particular, the power-down control signal generation circuit 120 can generate the power-down control signal and the clock signal simultaneously, but it is also possible to generate them separately.
For example, only a power-down control signal can be generated to operate only the memory cell in the power-down mode, only a clock signal can be generated to operate only the corresponding function block in the power-down mode, and the power-down control signal and the clock signal can be generated simultaneously to operate both the function block and the corresponding memory cell in the power-down mode.

[Industrial Applicability]

The display device according to the present invention, which minimizes power consumption during a blank period, operates the function block itself, which normally consumes power during the display period but does not require operation during the blank period, and/or the storage means (memory cell) related to the corresponding function block in the power-down mode, thereby minimizing the power required to drive the display panel, and thus has industrial applicability in the field of display technology, particularly in the field of timing controllers.

Claims

A timing controller of recovering a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and minimizing power consumption during a blank period, comprising:
a blank period detection circuit configured to generate a blank period detection signal using the clock signal and the gate driving signal; and

a function block group including a plurality of function blocks configured to perform operations in accordance with a display period and a blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal.
The timing controller according to claim 1, wherein the blank period detection signal is maintained as an inactive state during the display period and transited to an active state during the blank period.
The timing controller according to claim 1, wherein the plurality of function block groups are at least one of:
a Built In Self Test, BIST, execution unit performing a function of testing a defect between memory cells using a BIST circuit;

a content-based adaptive brightness control, CABC, performing a CABC function;

a digital gamma control unit configured to generate positive and negative gamma voltages having different values through a plurality of gamma blocks;

a DITHER unit configured to perform dithering on image data reproduced on a display panel; and

an image quality IP being an image processor used to improve a quality of the display panel.
The timing controller according to claim 3, wherein each of the plurality of functional blocks included in the functional block group includes a memory cell used for signal processing,
wherein the memory cell included in at least one functional block among the plurality of functional blocks operates in a power-down mode during the blank period.
The timing controller according to claim 4, wherein the memory cells have the BIST execution unit, the CABC, the digital gamma control unit, the DITHER unit, and the image quality IP itself or as a separate storage means.
A timing controller of recovering a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and minimizing power consumption during a blank period, comprising:
a blank period detection circuit that generates a blank period detection signal using the clock signal and the gate driving signal;

a power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal; and

a function block group including a plurality of function blocks configured to perform operations in response to the gate driving signal, the data driving signal, and the blank period detection signal in accordance with a display period and the blank period.
The timing controller according to claim 6, wherein the blank period detection signal includes information on minimizing power consumption during the blank period that is synchronized with the display period and the clock signal.
The timing controller according to claim 7, wherein the power-down control signal is maintained as an inactive state during the display period and transited to an active state during the blank period.
A display device of minimizing power consumption during a blank period, comprising:
a display panel;

a driving unit configured to drive the display panel; and

a timing controller configured to control an operation of the driving unit and including

a blank period detection circuit configured to recover a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and generate a blank period detection signal using the clock signal and the gate driving signal, and

a function block group including a plurality of function blocks configured to perform operations in accordance with a display period and the blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal.
A display device comprising:
a display panel;

a driving unit that drives the display panel; and

a timing controller configured to control an operation of the driving unit and including

a blank period detection circuit configured to recover a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system, and generate a blank period detection signal using the clock signal and the gate driving signal,

a power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal, and

a functional block group including a plurality of functional blocks configured to perform operations in accordance with a display period and the blank period in response to the gate driving signal, the data driving signal and the power-down control signal.