EP4616533A1

EP4616533A1 - Apparatus for phase and frequency detection and representation

Info

Publication number: EP4616533A1
Application number: EP22814080.2A
Authority: EP
Inventors: Mohammed ABDULAZIZ
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2022-11-09
Filing date: 2022-11-09
Publication date: 2025-09-17
Also published as: WO2024099557A1

Abstract

An apparatus for processing first and second input signals is disclosed.The apparatus comprises first and second phase frequency detectors (PFDs), each configured to provide leading and subsequent intermediate signals based on two received signals, wherein a combination of pulse lengths of the leading and subsequent intermediate signals indicates phase difference between the two received signals.The first PFD is configured to receive the first input signal and the second input signal as the two received signals, and to provide a first leading intermediate signal and a first subsequent intermediate signal.The second PFD is configured to receive the first input signal and an inverse of the second input signal as the two received signals, and to provide a second leading intermediate signal and a second subsequent intermediate signal.The apparatus also comprises logic circuitry configured to receive the intermediate signals and provide at least two output signals, wherein each output signal is based on exclusive OR, or inverse exclusive OR, between two of the intermediate signals, and wherein the two intermediate signals for at least one of the output signals are from different ones of the first and second PFDs.Corresponding arrangements, digital phase-locked loop (DPLL), integrated circuit, and electronic device are also disclosed.

Description

APPARATUS FOR PHASE AND FREQUENCY DETECTION AND REPRESENTATION

TECHNICAL FIELD

The present disclosure relates generally to detection and representation of signal frequencies and phase differences between signals.

BACKGROUND

There are many scenarios where it is desirable to detect and represent a phase difference between first and second input signals. One example is digital phase-locked loops (DPLLs), wherein an arrangement that converts a phase difference into a digital representation may be a building block. As described in WO 2022/128049 Al, such an arrangement for converting a phase difference into a digital representation may comprise a phase frequency detector and pulse shrinking time-to-digital converters (TDCs).

The in-band phase noise L_tdc of a digital phase-locked loop is typically dominated by quantization noise due to limited resolution in a time-to-digital converter TDC of the DPLL. In a typical example, the in-band phase noise may be expressed as L_tdc = where

F_REF is the reference frequency, T_CKV is the output signal period of the phase-locked loop, and At_(-nv is the time resolution of the TDC.

Thus, it is typically desirable to improve (e.g., increase) the resolution of the detection and representation. However, increased resolution typically entails increased power consumption and/or increased complexity. Furthermore, for DPLL applications, the performance requirements on a divider of the DPLL feedback path become more challenging with increased resolution and/or increased reference frequency.

Therefore, there is a need for alternative approaches to detection and representation of frequencies and phase differences. Preferably, such approaches address the performance requirements for DPLL division. It should be noted that, even though the background and some embodiments describe use of an apparatus in the context of DPLL, this is merely intended as an illustrative and non-limiting example of how such an apparatus may be used.

SUMMARY

It should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Generally, when an arrangement is referred to herein, it is to be understood as a physical product; e.g., an apparatus. The physical product may comprise one or more parts, such as controlling circuitry in the form of one or more controllers, one or more processors, or the like.

It is an object of some embodiments to solve or mitigate, alleviate, or eliminate at least some of the above or other disadvantages.

A first aspect is an apparatus for processing first and second input signals. The apparatus comprises first and second phase frequency detectors (PFDs), each configured to provide leading and subsequent intermediate signals based on two received signals, wherein a combination of pulse lengths of the leading and subsequent intermediate signals indicates phase difference between the two received signals. The first PFD is configured to receive the first input signal and the second input signal as the two received signals, and to provide a first leading intermediate signal and a first subsequent intermediate signal. The second PFD is configured to receive the first input signal and an inverse of the second input signal as the two received signals, and to provide a second leading intermediate signal and a second subsequent intermediate signal. The apparatus also comprises logic circuitry configured to receive the intermediate signals and provide at least two output signals, wherein each output signal is based on exclusive OR, or inverse exclusive OR, between two of the intermediate signals, and wherein the two intermediate signals for at least one of the output signals are from different ones of the first and second PFDs. In some embodiments, a pulse length of the output signal that is based on intermediate signals from different PFDs is indicative of one half-period of the second input signal.

In some embodiments, one of the output signals is a first type output signal which is based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals.

In some embodiments, the first type output signal comprises exclusive OR, or inverse exclusive OR, between the two of the intermediate signals.

In some embodiments, a pulse length of the first type output signal corresponds to one halfperiod of the second input signal.

In some embodiments, one of the output signals is a second type output signal which is based on one leading intermediate signal and one subsequent intermediate signal.

In some embodiments, the second type output signal is based on one leading intermediate signal and one subsequent intermediate signal from different ones of the first and second PFDs.

In some embodiments, the second type output signal comprises inverse exclusive OR, or exclusive OR, between one leading intermediate signal and one subsequent intermediate signal.

In some embodiments, a pulse length of the second type output signal corresponds to one halfperiod of the second input signal, or a multiple thereof, plus phase difference between the first and second input signals.

In some embodiments, the at least two output signals comprise one output signal based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals, and one output signal based on one leading intermediate signal and one subsequent intermediate signal.

In some embodiments, the at least two output signals comprise one output signal based on the first leading intermediate signal and one subsequent intermediate signal, and one output signal based on the second leading intermediate signal and one different subsequent intermediate signal. A second aspect is an exclusive OR gate comprising first and second circuits, wherein each of the first and second circuits implements an exclusive OR function between first and second circuitry inputs to provide a circuitry output, and wherein the first and second circuits have the same circuit structure. The first and second circuitry inputs are switched for the second circuit compared to the first circuit, and an output of the exclusive OR gate is connected to the circuitry output of both first and second circuits.

In some embodiments, exclusive OR of the first aspect is implemented by an exclusive OR gate according to the second aspect.

A third aspect is an arrangement comprising the apparatus of the first aspect. The arrangement also comprises two or more time-to-digital converters (TDCs), each configured to receive one of the output signals provided by the apparatus and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC. The arrangement also comprises processing circuitry configured to indicate phase difference between the first and second input signals based on the digital pulse length representations provided by the TDCs.

In some embodiments, pulse length modification comprises pulse length shrinking or pulse length extension.

In some embodiments, the phase difference is provided as a division between first and second digital pulse length representations. The first pulse length representation corresponds to an output signal from the apparatus based on one leading intermediate signal and one subsequent intermediate signal. The second pulse length representation corresponds to an output signal based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals.

In some embodiments, the phase difference is provided by biasing an average of two or more digital pulse length representations, each digital pulse length representation corresponding to an output signal from the apparatus based on one leading intermediate signal and one subsequent intermediate signal, wherein the biasing is associated with one half-period of the second input signal.

In some embodiments, the processing circuitry is further configured to indicate period of the second input signal based on the digital pulse length representations provided by the TDCs. In some embodiments, the period of the second input signal is provided as a pulse length representation corresponding to an output signal based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals.

In some embodiments, the period of the second input signal is provided as twice of a difference between two digital pulse length representations, each corresponding to an output signal from the apparatus based on one leading intermediate signal and one subsequent intermediate signal.

In some embodiments, the arrangement further comprises calibration circuitry fortuning of the arrangement. The calibration circuitry is configured to set a TDC resolution based on a digital control signal associated with an integer N for representing the period digitally as 2^W.

In some embodiments, the calibration circuitry is configured to vary the TDC resolution until a period average of the second input signal is representable by a digital word where only an /V^th bit is set.

In some embodiments, the digital control signal is provided as a difference between the digital word where only the /V^th bit is set, and the period average of the second input signal.

In some embodiments, the calibration circuitry is further configured to implement a division operation by shifting the digital pulse length representation by a number N of bits that corresponds to the integer for representing the period digitally.

A fourth aspect is a digital phase-locked loop (DPLL) comprising the apparatus of the first aspect, and/or the arrangement of the third aspect.

A fifth aspect is an integrated circuit comprising the apparatus of the first aspect, and/or the arrangement of the third aspect, and/or the DPLL of the fourth aspect.

A sixth aspect is an electronic device comprising the apparatus of the first aspect, and/or the arrangement of any of the third aspect, and/or the DPLL of the fourth aspect, and/or the integrated circuit of the fifth aspect.

In some embodiments, any of the above aspects may additionally have features identical with or corresponding to any of the various features as explained above for any of the other aspects. An advantage of some embodiments is that alternative approaches are provided for detection and representation of frequencies and/or phase difference of two signals.

An advantage of some embodiments is that power consumption is decreased compared to other approaches.

An advantage of some embodiments is that complexity is decreased compared to other approaches.

An advantage of some embodiments is that no complicated divider is required for DPLL. For example, the variable clock signal (CKV) can be fed back directly and used as the second input signal. Alternatively or additionally, a division operation is reduced to a digital shift operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the example embodiments.

Figure 1 is a schematic block diagram illustrating an example apparatus according to some embodiments;

Figure 2 is a schematic block diagram illustrating a more detailed example apparatus according to some embodiments;

Figure 3 illustrates an example phase frequency detector (PFD), a corresponding example state diagram, and a signal timing diagram;

Figure 4 is a schematic block diagram illustrating an example exclusive OR gate according to some embodiments;

Figure 5 is a schematic block diagram illustrating a more detailed example exclusive OR gate according to some embodiments;

Figure 6 is a plot illustrating example results achievable according to some embodiments;

Figure 7 is a plot illustrating example results achievable according to some embodiments; Figure 8 is a pair of schematic block diagrams, each illustrating an example arrangement according to some embodiments;

Figure 9 is a pair of schematic block diagrams, each illustrating an example calibration approach according to some embodiments;

Figure 10 is a schematic block diagram illustrating an example electronic device according to some embodiments;

Figure 11 is a schematic block diagram illustrating an example digital phase-locked loop (DPLL) according to some embodiments; and

Figure 12 is a schematic block diagram illustrating an example digital phase-locked loop (DPLL) according to some embodiments.

DETAILED DESCRIPTION

As already mentioned above, it should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Embodiments of the present disclosure will be described and exemplified more fully hereinafter with reference to the accompanying drawings. The solutions disclosed herein can, however, be realized in many different forms and should not be construed as being limited to the embodiments set forth herein.

Generally, a pulse length may be equivalently termed as a pulse width.

In the following, embodiments will be described where approaches are provided for detection and representation of frequencies and/or phase differences.

Some embodiment may be particularly suitable for use in fractional DPLLs.

Fractional DPLLs may be based on pulse length modifying (e.g., pulse shrinking, PS) TDCs. A signal (CKV) from a digitally controlled oscillator (DCO) is typically divided in frequency to provide a feedback signal (DIV) that has a frequency which is relatively close to that of the reference signal (REF). The phase difference between DIV and REF is measured and represented in the form of a pulse length, which is converted to a digital representation using the PS-TDC.

With the increasing need for DPLLs configured to handle high frequencies, the REF frequency typically also needs to be increased to avoid problems caused by the division ratio (e.g., deterioration of the in-band noise). However, increasing the REF frequency may be problematic.

For example, the digital signal processing of the phase error is cumbersome, and current CMOS technologies typically cannot support excessively high REF frequencies. Furthermore, even when CMOS technology can support the REF frequency, power consumption typically increases with the REF frequency.

Some embodiments are very suitable to address such problems.

Thus, some problems with conventional approaches include that a digital-to-time converter or a multi-modular divider is typically needed to have fractional functionality of a DPLL, that use of a high frequency REF in DPLLs is limited by the circuitry required for calculation of the fractional phase error, and that the TDC range needs to cover the divided signal.

Some embodiments address this by directly providing the fractional phase error, reducing the necessary TDC range, and rendering the division operation unnecessary or at least simplified.

By application of some embodiments, the phase error calculation becomes trivial. Furthermore, the phase error may be generated at the REF rate, which entails decreased power consumption compared to other approaches. For example, according to approaches of the prior art, the TDC typically operates at CKV rate (or a clock gating system may be needed to save power), which entails relatively high power consumption.

Figure 1 schematically illustrates an example apparatus 100 according to some embodiments. The apparatus 100 may be seen as a PFD apparatus.

The apparatus 100 is configured to process a first input signal 101 and a second input signal 102. Typically, the first input signal 101 has lower frequency that the second input signal 102.

When used in the context of a digital phase-locked loop (DPLL), the first input signal may be a reference signal (REF) and the second input signal may be a feedback signal of the DPLL. For example, the second input signal may be a variable clock signal (CKV) fed back in a DPLL without any frequency division. Alternatively, the second input signal may be a frequency divided feedback signal (DIV) of the DPLL.

The apparatus 100 comprises a first phase frequency detector (PFD) 110, and a second phase frequency detector (PFD) 120. The PFDs may be any suitable PFDs (e.g., as described in connection with Figure 3). Phase frequency detectors are - conceptually - well known and their general functionality and known implementation variants will not be elaborated on in length herein.

Each PFD 110, 120 is configured to provide a leading intermediate signal 111, 121 and subsequent intermediate signal 112, 122 based on two received signals. For example, the leading intermediate signal 111, 121 may correspond to an UP signal of the PFD and the subsequent intermediate signal 112, 122 may correspond to a DOWN signal of the PFD.

A combination of pulse lengths of the leading and subsequent intermediate signals of a PFD indicates phase difference between the two received signals of the PFD. The combination may be any suitable combination (e.g., addition, accumulation, time duration from start of the leading signal pulse to end of the subsequent signal pulse, difference, etc.).

The first PFD 110 is configured to receive the first input signal 101 and the second input signal 102 as the two received signals, and to provide a first leading intermediate signal 111 and a first subsequent intermediate signal 112.

The second PFD 120 is configured to receive the first input signal 101 and an inverse 102' of the second input signal 102 as the two received signals, and to provide a second leading intermediate signal 121 and a second subsequent intermediate signal 122.

As will be further exemplified in this description, using two PFDs with different versions 102, 102' of the second signal enables detection and representation of the period of the second input signal 102, along with detection and representation of the phase difference between the first and second input signals 101, 102. In some embodiments, this simplifies DPLL implementation by making a feedback path divider unnecessary and/or reducing the division operation to a digital shifting operation. The inverse 102' of the second input signal 102 may be provided in any suitable way. For example, the second input signal 102 and its inverse 102' may be provided as differential signals. When the apparatus 100 is used in a context with differential signaling, the second input signal 102 and its inverse 102' may be directly available for provision to the PFDs. When the apparatus 100 is used in a context with single ended signaling, the second input signal 102 and its inverse 102' may be provided by conversion to differential form (e.g., by application of circuitry for single ended to differential conversion before provision to the PFDs). Alternatively, the inverse 102' of the second input signal 102 may be provided by inversion of the second input signal 102. Any delay caused by the inversion may be compensated by correspondingly delaying the other input signals of the PFDs.

The apparatus 100 also comprises logic circuitry (LC) 130 configured to receive the intermediate signals 111, 112, 121, 122 and provide at least two (e.g., two, three, or more) output signals 141, 143.

Each output signal 141, 143 is based on exclusive OR (binary logic, XOR), or inverse exclusive OR (binary logic, XNOR), between two of the intermediate signals 111, 112, 121, 122.

For at least one of the output signals 141, 143, the two intermediate signals used are from different ones of the first and second PFDs 110, 120.

Thus, there is at least one "cross-coupling" within the logic circuitry 130, using one intermediate signal 111, 112 output by the first PFD 110 and one intermediate signal 121, 122 output by the second PFD 120 to provide an output signal 141, 143. Such cross-coupling enables the corresponding output signal to represent the period of the second input signal 102.

One way of representing the period of the second input signal 102 is to configure the pulse length of an output signal 141, 143 that is based on intermediate signals from different PFDs to be indicative of one half-period of the second input signal. For example, the pulse length of such an output signal 141, 143 may be equal to one half-period of the second input signal 102, or may be equal to a phase difference between the first and second input signals 101, 102 plus one half-period (or an integer multiple - e.g., 2, 3, 4, etc. - of one half-period) of the second input signal 102. The addition of the half-period of the second input signal 102 is due to that the second input signal 102 and its inverse 102' (i.e., the second input signal 102 in the form of differential signals) are used, respectively, for the PFDs.

A first type output signal 141, 143 is based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals. Thus, the first type output signal uses one intermediate signal from each PFD 110, 120, wherein the used intermediate signals are either both leading intermediate signals, or both subsequent intermediate signals.

The first type output signal may be provided by an exclusive OR (XOR), or inverse exclusive OR (XNOR), operation between the two used intermediate signals. Hence, the first type output signal may comprise (e.g., consist of) an exclusive OR, or inverse exclusive OR, between the two intermediate signals.

The pulse length of an output signal of the first type may be equal to (or otherwise correspond to) one half-period of the second input signal 102. Alternatively or additionally, the pulsing period of an output signal of the first type may be equal to (or otherwise correspond to) one period of the first input signal 101.

A second type output signal 141, 143 is based on one leading intermediate signal and one subsequent intermediate signal.

The second type output signal may be provided by an inverse exclusive OR (XNOR), or exclusive OR (XOR), operation between the two used intermediate signals. Hence, the first type output signal may comprise (e.g., consist of) an inverse exclusive OR (XNOR), or exclusive OR (XOR), between the two intermediate signals.

The pulse length of an output signal of the second type may be equal to (or otherwise correspond to) a phase difference between the first and second input signals 101, 102.

In some embodiments, the second type output signal is based on one leading intermediate signal and one subsequent intermediate signal from different ones of the first and second PFDs (i.e., a "cross-coupling" implementation). The pulse length of such an output signal of the second type may be equal to a phase difference between the first and second input signals 101, 102 plus one half-period (or an integer multiple of one half-period) of the second input signal In some embodiments, the second type output signal is based on one leading intermediate signal and one subsequent intermediate signal from the same one of the first and second PFDs (i.e., an implementation without "cross-coupling"). The pulse length of such an output signal of the second type may be equal to a phase difference between the first and second input signals 101, 102.

According to some approaches, a first type output signal is based on exclusive OR (XNOR) and a second type output signal or inverse exclusive OR (NXOR); or vice versa.

In some embodiments, the at least two output signals comprise one first type output signal (i.e., one output signal based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals) and one second type output signal (i.e., one output signal based on one leading intermediate signal and one subsequent intermediate signal; from the same or different PFD). For example, there may be exactly two output signals; one of each of the first and second type.

In some embodiments, the at least two output signals comprise two second type output signals (i.e., output signals, each of which is based on one leading intermediate signal and one subsequent intermediate signal). For example, there may be exactly two output signals; both of the second type.

In some embodiments, the at least two output signals comprise one first type output signal (i.e., one output signal based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals) and two second type output signal (i.e., two output signals, each based on one leading intermediate signal and one subsequent intermediate signal; from the same or different PFD). For example, there may be exactly three output signals; one of the first and two of the second type.

Generally, when there are two second type output signals, they typically use opposite ones of the intermediate signals. Thus, a first one of the second type output signal may be based on the first leading intermediate signal and the second subsequent intermediate signal, and a second one of the second type output signal may be based on the second leading intermediate signal and the first subsequent intermediate signal (i.e., "cross-coupling"). Alternatively, a first one of the second type output signal may be based on the first leading intermediate signal and the first subsequent intermediate signal, and a second one of the second type output signal may be based on the second leading intermediate signal and the second subsequent intermediate signal (i.e., no "cross-coupling").

Figure 2 schematically illustrates an example apparatus 200 according to some embodiments. The apparatus 200 may be seen as an exemplification of the apparatus 100 of Figure 1.

The apparatus 200 is configured to process a first input signal 201 (compare with 101) and a second input signal 202 (compare with 102).

As explained in relation to Figure 1, the apparatus 200 may be used in the context of a DPLL, and the first input signal 201 may be a reference signal (REF) and the second input signal 202 may be a feedback signal of the DPLL (e.g., a variable clock signal - CKV).

The apparatus 200 comprises a first PFD 210 (compare with 110), and a second PFD 220 (compare with 120).

The first PFD 210 is configured to receive the first input signal 201 and the second input signal 202, and to provide a first leading intermediate signal 211 (compare with 111) and a first subsequent intermediate signal 212 (compare with 112).

The second PFD 220 is configured to receive the first input signal 201 and an inverse 202' of the second input signal 202, and to provide a second leading intermediate signal 221 (compare with 121) and a second subsequent intermediate signal 222 (compare with 122).

The apparatus 200 also comprises logic circuitry 230 (LC; compare with 130) configured to receive the intermediate signals 211, 212, 221, 222 and provide at least two (in this case: three) output signals 241, 242, 243 (compare with 141, 143).

Each output signal 241, 242, 243 is based on exclusive OR (XOR), or inverse exclusive OR (XNOR), between two of the intermediate signals 211, 212, 221, 222. To this end, the logic circuitry 230 comprises two XNOR gates 231, 233 and one XOR gate 232.

The XOR gate 232 is configured to provide a first type output signal 242 based on the first and second subsequent intermediate signals 212, 222. Another possibility is to let the XOR gate 232 be configured to provide the first type output signal 242 based on the first and second leading intermediate signals 211, 221. The pulse length of the output signal 242 is equal to one half- period of the second input signal 202, and the pulsing period of the output signal 242 is typically equal to one period of the first input signal 201. Thus, the output signal 242 provides a representation of the period of the second input signal 202.

The XNOR gate 231 is configured to provide a second type output signal 241 based on the first leading intermediate signal 211 and the second subsequent intermediate signal 222, and the XNOR gate 233 is configured to provide a second type output signal 243 based on the second leading intermediate signal 221 and the first subsequent intermediate signal 212. The pulse length of the output signals 241, 243 of the first type are equal to the phase difference between the first and second input signals 201, 202 plus one half-period (or an integer multiple of one half-period) of the second input signal 202.

Another possibility is to let the XNOR gate 231 be configured to provide a second type output signal 241 based on the first leading intermediate signal 211 and the first subsequent intermediate signal 212, and the XNOR gate 233 be configured to provide a second type output signal 243 based on the second leading intermediate signal 221 and the second subsequent intermediate signal 222. Then, the pulse length of the output signals 241, 243 of the first type are equal to the phase difference between the first and second input signals 201, 202.

It should be noted that an alternative implementation applies XOR gates instead of the XNOR gates 231, 233, and/or an XNOR gate instead of the XOR gate 232.

All three of the output signals 241, 242, 243 may be used (e.g., as inputs to pulse length modifying TDCs), or only two of the output signals (e.g., 241 and 242, or 241 and 243) may be used; as will be exemplified later herein.

Figure 3 illustrates an example PFD 300 (upper left), a corresponding example state diagram (upper right), and a signal timing diagram (lower). The example PFD 300 may be used as one or more of the PFDs 110, 120, 210, 220 of Figures 1 and 2.

The PFD 300 comprises an AND gate 313, two - first and second - digital flip flops (DFFs), and a delay component 314. The first DFF is fed a first input signal 301 (compare with 101, 201) and the second DFF is fed a second input signal 302 (compare with 102, 202). First and second signals 311, 312 are provided by the first and second DFFs, respectively. The first signal 311 is a leading signal (e.g., an UP signal; compare with 111, 121, 211, 221) and the second signal is a subsequent signal (e.g., a DOWN signal; compare with 112, 122, 212, 222).

The AND gate 313 combines the first and second signals 311, 312, and the result is delayed by the delay component 314 to provide a reset signal 315 for the DFFs.

Turing to the state diagram, if it is assumed that the first and second signals 311, 312 are initially low (i.e., UP=0, DOWN=0; state 392), the PFD 300 moves to another state when a rising edge is detected. If the detected rising edge is in the first input signal 301, the PFD 300 moves to state 393 as illustrated by transition 397. If the detected rising edge is in the second input signal 302, the PFD 300 moves to state 391 as illustrated by transition 396. Then, a rising edge on the other signal brings the PFD 300 back to the state 392 as illustrated by transitions 395 and 394, respectively.

A pulse of either of the signals 311, 312 will have a pulse duration that relates to the phase difference between the input signals 301, 302 (with a pulse periodicity relating to the lowest frequency of the input signals 301, 302).

Using the PFD 300 in the context of Figure 2, a representation of the phase error is generated by detection of the rising edge of FREF followed by the rising edge of CKV (i.e., DIV in Figure 3), and when the edge of CKV is detected the state does not change until a rising edge of FREF is detected. This means that the state 391 (UP=0, DOWN=1) may be seen as an initial state; rather than state 392 (UP=0, DOWN=0) as is conventionally assumed when PFDs are operated with DIV and FREF at similar frequencies.

Referring back to Figure 2, it can be realized that when the phase error (i.e., the phase difference) is captured using a signal 202 with relatively high frequency (e.g., a non-divided feedback signal, CKV, of a DPLL), a PFD 300 will - after rising edges of REF and CKV - remain in the initial state 391 until the rising edge of REF.

Thus, starting in the state UP=0 and DOWN=1, a rising edge of FREF will make the PFD move to the state UP=0 and DOWN=0. Then, the PFD will move to the state UP=1 and DOWN=0 due to feedback delay, and a short pulse is produced in the UP signal before a subsequent rising edge of CKV will make the PFD move back to the state UP=0 and DOWN=1 via the state UP=0 and DOWN=0.

By using two PFDs 210, 220 with a 180° shift of the CKV signal, corresponding outputs of the two PFDs may differ by a half-period of the CKV signal.

The lower part of Figure 3 illustrates the timing of an FREF signal 380 (compare with 201 of Figure 2) in relation to a CKV signal 381 (compare with 202 of Figure 2) and its inverse 382 (compare with 202' of Figure 2). The outputs of a PFD 300 that receives 380 and 381 is represented by 383, 384 (UP and DOWN, respectively) and the outputs of a PFD 300 that receives 380 and 382 is represented by 385, 386 (DOWN and UP, respectively). It can be seen that the DOWN signals 384, 385 differ by a half-period 387 of the CKV signal in pulse length.

Application of an XOR operation on such signals from different PFDs enables the half-period of the CKV signal to be captured, as illustrated by 242, when the XORed signals are of the same type (both DOWN or both UP).

Application of an XNOR operation on such signals from different PFDs enables the phase difference plus a half-period (or a multiple thereof) of the CKV signal to be captured, as illustrated by 241, 243, when the XNORed signals are of different types (one DOWN and one UP). The addition of the half-period to the phase difference pulse (i.e., a longer pulse) can be beneficial to ease timing constraints. For example, timing constraints on the PFD apparatus 100, 200 may be eased when the minimum pulse length is a half-period of the CKV signal. Furthermore, the PFD apparatus 100, 200 can typically operate at relatively high frequencies.

To enable preservation of the timing information for the pulse 242, a high speed XOR design may be beneficial. Particularly, the relation between rise and fall times of the XOR inputs need to be adequately preserved to provide an accurate width of the pulse 242.

Figures 4 and 5 provide an XOR design suitable for these purposes. The XOR gate of these Figures enables the two inputs to be loaded symmetrically, and therefore has similar profiles for rise and fall times. An XNOR design may be achieved by adding an inverter at the output of an XOR gate (e.g., the XOR gate of any of Figures 4 and 5). Figure 4 schematically illustrates an example exclusive OR (XOR) gate 400 according to some embodiments. The example XOR gate 400 may be used to implement one or more XOR/XNOR gate as mentioned in connection with Figures 1 and 2 (e.g., one or more of 231, 232, 233).

The exclusive OR gate 400 comprises first and second circuits 410, 420. The first and second circuits 410, 420 have the same circuit structure, and each of the first and second circuits 410,

420 implements an exclusive OR (XOR) function between first and second circuitry inputs 411, 412, 421, 422 to provide a circuitry output 413, 423.

The first and second circuitry inputs are switched for the second circuit compared to the first circuit. Thus, a first input 401 is connected to the first circuitry input 411 of the first circuit 410 and to the second circuitry input 422 of the second circuit 420, while a second input 402 is connected to the second circuitry input 412 of the first circuit 410 and to the first circuitry input

421 of the second circuit 420.

The output 403 of the exclusive OR gate 400 is connected to the circuitry output 413, 423 of both first and second circuits 410, 420.

Using the XOR gate 400 typically yields higher timing accuracy than using any one of the constituent XOR circuits 410, 420 alone. One reason is that process variation of the components is mitigated through averaging of result over the two constituent XOR circuits 410, 420 and/or through the asymmetric use of the circuitry inputs.

Figure 5 schematically illustrates an example exclusive OR (XOR) gate 500 according to some embodiments. The example XOR gate 500 may be used to implement one or more XOR/XNOR gate as mentioned in connection with Figures 1 and 2 (e.g., one or more of 231, 232, 233). The XOR gate 500 may be seen as an exemplification of the XOR gate 400 of Figure 4.

The exclusive OR gate 500 comprises first and second circuits 510, 520. The first and second circuits 510, 520 have the same circuit structure (realized by mirroring the circuit 510 horizontally as well as vertically to acquire the circuit 520), and each of the first and second circuits 510, 520 implements an exclusive OR (XOR) function between first and second circuitry inputs to provide a circuitry output.

The first and second circuitry inputs are switched for the second circuit compared to the first circuit. Thus, a first input 501 is connected to the first circuitry input of the first circuit 510 and to the second circuitry input of the second circuit 520, while a second input 502 is connected to the second circuitry input of the first circuit 510 and to the first circuitry input of the second circuit 520.

The output 503 of the exclusive OR gate 500 is connected to the circuitry output of both first and second circuits 510, 520.

The first circuit 510 comprises a first transistor 511 (e.g., a P-channel transistor), a second transistor 512 (e.g., an N-channel transistor), a third transistor 513 (e.g., a P-channel transistor), and a fourth transistor 514 (e.g., an N-channel transistor).

The first and second transistors 511, 512 have their gates connected to each other and their drains connected to each other. The source of the first transistor 511 is connected to a first voltage reference (e.g., a supply voltage) and the source of the second transistor 512 is connected to a second voltage reference (e.g., ground).

The third and fourth transistors 513, 514 have their gates connected to each other and their drains connected to each other. The drains of the first and second transistors 511, 512 are connected to the source of the fourth transistor 514.

The first input 501 is connected to the gates of the first and second transistors 511, 512, and to the source of the third transistor 513. The second input 502 is connected to the gates of the third and fourth transistors 513, 514. The drains of the third and fourth transistors 513, 514 are connected to the output 503.

The second circuit 520 comprises a first transistor 521 (e.g., a P-channel transistor), a second transistor 522 (e.g., an N-channel transistor), a third transistor 523 (e.g., a P-channel transistor), and a fourth transistor 524 (e.g., an N-channel transistor).

The first and second transistors 521, 522 have their gates connected to each other and their drains connected to each other. The source of the first transistor 521 is connected to a first voltage reference (e.g., a supply voltage) and the source of the second transistor 522 is connected to a second voltage reference (e.g., ground). The third and fourth transistors 523, 524 have their gates connected to each other and their drains connected to each other. The drains of the first and second transistors 521, 522 are connected to the source of the fourth transistor 524.

The second input 502 is connected to the gates of the first and second transistors 521, 522, and to the source of the third transistor 523. The first input 501 is connected to the gates of the third and fourth transistors 523, 524. The drains of the third and fourth transistors 523, 524 are connected to the output 503.

Figures 6 and 7 illustrate some example results achievable according to some embodiments. Particularly, a low-power design of the apparatus 200 of Figure 2 (with the XOR gate implementation of Figure 5) was used with a first input signal (REF) frequency of 500 MHz and a second input signal (CKV) frequency of 4997.5 MHz to test a tough fractional case where period estimation is one prominent cause of spurs.

Figure 6 shows the half-period error averaged over time on the y-axis (ranging from -1.9 ps to 0.6 ps, with 0 ps indicated by 600). Some different corner cases (NMOS speed - PMOS speed) are shown; fast-fast (FF) 611, fast-slow (FS) 612, slow-slow (SS) 613, typical-typical (TT) 614, and a nominal case 615. It may be seen that the estimation 601, 602, 603, 604, 605 of the period of the second input signal is rather accurate; even for the corner cases FF, FS, and SS. Thus, the apparatus may be considered as robust across process corners.

Figure 7 shows pulse width of the phase error signals 241, 243 normalized to CKV period on the y-axis (i.e., the value of the y-axis corresponds to the pulse width of the phase error signal divided by the CKV period), and time on the x-axis (ranging over 1 ps). Phase error signal 241 is represented by 701 and phase error signal 242 is represented by 702. The simulation concerns a scenario where CKV is slowly drifting in relation to REF. As expected, the difference between the phase error signals is as shifted by 180° (half-period).

Figure 8 schematically illustrates two example arrangements 800a, 800b according to some embodiments. Each of the arrangements comprises an apparatus as described and exemplified in connection to Figures 1 and 2.

The arrangement 800a is configured to process a first input signal 801 (compare with 101, 201) and a second input signal 802 (compare with 102, 202). As explained in relation to Figure 1, the arrangement 800a may be used in the context of a DPLL, and the first input signal 801 may be a reference signal (REF) and the second input signal 802 may be a feedback signal of the DPLL (e.g., a variable clock signal - CKV).

The arrangement 800a comprises a first PFD 810 (compare with 110, 210), and a second PFD 820 (compare with 120, 220). The first PFD 810 is configured to receive the first input signal 801 and the second input signal 802, and the second PFD 820 is configured to receive the first input signal 801 and an inverse 802' of the second input signal 802.

The arrangement also comprises two XNOR gates 831, 833 (compare with 231, 233) configured to provide two signals 841, 843 (compare with 241, 243) based on outputs from the PFDs 810, 820. Each of the XNOR gates 831, 833 is configured to provide a second type output signal based on a leading intermediate signal and a subsequent intermediate signal, output from different ones of the PFDs 810, 820.

The pulse length of the signals 841, 843 are equal to the phase difference between the first and second input signals 801, 802 plus one half-period (or an integer multiple of one half-period) of the second input signal 802.

The signals 841, 843 are fed to respective pulse length modifying time-to-digital converters (TDC) 851, 853, followed by respective digital encoders (ENC) 861, 863. Each of the encoders is configured to interpret the corresponding TDC output and provide a digital representation 871, 873 of it. Thus, each of the encoders provide a digital representation 871, 873 of the pulse length of the signals 841, 843 (i.e., a digital representation of the phase difference between the first and second input signals 801, 802 plus one half-period - or an integer multiple of one halfperiod - of the second input signal 802). Thus, each TDC is configured to receive a signal and provide a corresponding digital pulse length representation.

The encoders associated with the TDCs are followed by processing circuitry 890 configured to provide an output 898 to indicate period of the second input signal 802, and an output 899 to indicate phase difference between the first and second input signals 801, 802 based on the digital pulse length representations provided by the TDCs.

For example, the output 898 may be provided by multiplying the difference between 871 and

873 with two. The output 899 may be provided by dividing the sum of 871 and 873 with two and removing an associated offset. The offset removal may be based on a correction factor 883a, which is determined by an offset calculator (OC) 880a based on the digital pulse length representations 871, 873. As exemplified in Figure 8, the sum of the pulse lengths represented by 871, 873 may be determined (as illustrated by 894), as well as the difference between them (as illustrated by 895).

The difference of the pulse lengths may be multiplied by two (as illustrated by 896) to provide a representation 898 of the period of the second input signal 802. In some embodiments, the period representation undergoes accumulation and/or averaging (as illustrated by 891). Thus, the period of the second input signal 802 may be indicated based on the digital pulse length representations 871, 873, wherein the period of the second input signal is provided as twice of a difference between the two digital pulse length representations 871, 873.

The period of the second input signal 802 as provided by the representation 898 may be removed from the sum of the pulse lengths and the result be divided by two (as illustrated by 897). The offset may be removed (as illustrated by 892) to provide an estimation 899 of the phase difference between the first and second input signals 801, 802. The estimation 899 is typically offset by an amount that can be compensated for. Thus, the phase difference may be provided by biasing (removing period and/or offset from) an average of the two digital pulse length representations 871, 873, wherein the biasing is - typically - associated with one halfperiod of the second input signal (or an integer multiple thereof).

An advantage of the arrangement 800a is that the error mismatch effect is scaled by a factor of two. Furthermore, estimating the period by taking the difference 895 proves to be useful. When averaging 891 the period over time, mismatch is inverted in sign when wrap around occurs. This means that when accumulating the period together with the mismatch, then the period sign changes as the phase wrap occurs and the mismatch magnitude is also inverted and accumulated with opposite sign, which results in error cancellation.

The arrangement 800b is configured to process a first input signal 801 (compare with 101, 201) and a second input signal 802 (compare with 102, 202). As explained in relation to Figure 1, the arrangement 800b may be used in the context of a DPLL, and the first input signal 801 may be a reference signal (REF) and the second input signal 802 may be a feedback signal of the DPLL (e.g., a variable clock signal - CKV). The arrangement 800b comprises a first PFD 810 (compare with 110, 210), and a second PFD 820 (compare with 120, 220). The first PFD 810 is configured to receive the first input signal 801 and the second input signal 802, and the second PFD 820 is configured to receive the first input signal 801 and an inverse 802' of the second input signal 802.

The arrangement also comprises one XNOR gate 831, and one XOR gate 832 (compare with 231, 232) configured to provide two signals 841, 842 (compare with 241, 242) based on outputs from the PFDs 810, 820. The XNOR gate 831 is configured to provide a second type output signal based on a leading intermediate signal and a subsequent intermediate signal, output from different ones of the PFDs 810, 820. The XOR gate 832 is configured to provide a first type output signal 842 based on the subsequent intermediate signals (or the leading intermediate signals) output from different ones of the PFDs 810, 820.

The pulse length of the signal 841 is equal to the phase difference between the first and second input signals 801, 802 plus one half-period (or an integer multiple of one half-period) of the second input signal 802. The pulse length of the signal 842 is equal to one half-period of the second input signal 802.

The signals 841, 842 are fed to respective pulse length modifying time-to-digital converters (TDC) 851, 852, followed by respective digital encoders (ENC) 861, 862. Each of the encoders is configured to interpret the corresponding TDC output and provide a digital representation 871, 872 of it. Thus, each of the encoders provide a digital representation 871, 872 of the pulse length of the signals 841, 842 (i.e., a digital representation 871 of the phase difference between the first and second input signals 801, 802 plus one half-period - or an integer multiple of one halfperiod - of the second input signal 802, and a digital representation 872 of one half-period of the second input signal 802). Thus, each TDC is configured to receive a signal and provide a corresponding digital pulse length representation. The period of the second input signal 802 is indicated based on the digital pulse length representations 871, 872, wherein the period of the second input signal is provided as twice the digital pulse length representations 872.

The encoders associated with the TDCs are followed by processing circuitry configured to indicate phase difference between the first and second input signals 801, 802 based on the digital pulse length representations provided by the TDCs. The pulse length represented by 871 is divided by the half-period of the second input signal 802 as provided by the representation 872 (as illustrated by 881). The result may undergo an offset removal (as illustrated by 882); e.g., to compensate for an offset of the pulse length represented by 871. The offset removal is based on a correction factor 883b, which is determined by an offset calculator (OC) 880b based on the digital pulse length representations 871, 872. Thereby, an estimation 889 of the phase difference between the first and second input signals 801, 802 is provided. Thus, the phase difference is provided as a difference between first and second digital pulse length representations 871, 872.

An advantage of the arrangement 800b is that the period and the error are estimated with relatively high accuracy. High accuracy typically results in a relatively low level of fractional spurs.

Generally, the offset calculator 880a may be similar to, or different from, the offset calculator 880b.

In some embodiments, the offset calculated by 880a and/or 800b may depend on how an integer error is corrected for in the context where the arrangement 800a, 800b is used (e.g., a DPLL). Using a counter for integer error correction in a frequency locking loop, phase wraparound situations are addressed automatically and need not be handled by the offset calculator 880a, 880b. In other types of frequency locking loops, phase wrap-around situations need to be handled (e.g., calculated and corrected) by the offset calculator 880a, 880b.

In some embodiments, the offset calculator 880a, 880b may be configured to add phase shifts (e.g., for multi-antenna systems).

In some embodiments, the arrangements 800a and 800b may be combined so that Three TDCs are used (corresponding to 851, 852, 853). Such an approach might improve the estimation of the period of the second input signal 802 by combining the estimation 898 with the estimation 872. Improved period estimation might be beneficial for reduction of spurious tones at the output.

As already mentioned, pulse length modification may comprise pulse length shrinking or pulse length extension. Thus, examples of pulse length modifying TDCs include pulse shrinking TDCs and pulse extending TDCs. Pulse shrinking TDCs will be used as non-limiting exemplification. Pulse extending TDCs are -conceptually -well known and their general functionality and known implementation variants will not be elaborated on in length herein.

Generally, a pulse length modifying TDC is configured to provide a digital representation of the pulse length of a signal input to it (a received signal) by successively modifying the pulse length of the received signal and detect when the pulse length has reached a threshold value.

For example, a pulse shrinking TDC is configured to provide a digital representation of the pulse length of the received signal by successively shrinking the pulse length of the received signal and detect when the pulse length has reached zero (i.e., when the pulse has vanished).

A pulse shrinking TDC may be based on a chain of stages in similarity to a conventional TDC. However, in a pulse shrinking TDC, the cell corresponding to each stage is typically not a pure delay cell as in a conventional TDC, but a pulse shrinking cell. A pulse shrinking cell causes the pulse length of the processed signal to decrease. For example, the pulse length of a received signal processed by a pulse shrinking TDC may decrease by one least significant bit (LSB) for each stage it passes in the chain. Eventually (provided the chain is long enough), the pulse length of the processed signal reaches a threshold value (e.g., zero; in which case there is no pulse in the processed signal for the rest of the chain).

The pulse shrinking TDC may include (or be followed by as in the examples of Figure 8) an encoder for outputting a digital representation of the pulse length of the received signal (e.g., a quantized pulse length; digitally represented). Counting the number of stages that has a pulse provides one indication of the pulse length of the received signal. A flip-flop element may be used for each stage to detect whether or not there is a pulse (e.g., outputting a "1" when there is a pulse and "0" for at least the first stage where there is no pulse).

Thus, Figure 8 provides two example overall architectures for a phase detection system. A first step provides an estimation 841, 842, 843 of phase error (phase difference) in combination with second input signal half-period.

In the arrangement 800a, the signals 841, 843 are shifted by 0.5 and 1 periods of the second input signal 802 (which one is shifted with which amount depends on if the second input signal 802 is leading or lagging). Assuming that 841 is offset by 0.5 periods and 843 is offset by 1 period, the output of 894 becomes the phase difference times two plus 1.5 periods, and the output of 895 becomes 0.5 periods. Either of the signals 871, 873 may be used directly for phase error calculation (taking account of the corresponding offset 0.5 or 1 period) or the sum may be used as suggested in Figure 8 (taking account of the duplication of the phase error and the corresponding offset 1.5 period). Thus, an estimation of the period 898 is readily available as well as an indirect estimation of the phase error 899, and subsequent calculations to obtain the phase error are trivial.

In the arrangement 800b, the signals 841, 842 are used to generate values for the phase error 871 and the half-period 872. These values are divided as illustrated by 881, to produce an estimation of the phase error 889. Thus, an estimation of the half-period 872 is readily available as well as an estimation of the phase error 889, and subsequent calculations to obtain the phase error are trivial.

When high frequency is required for the first input signal and the digital divider becomes a critical component for performance, the PFD apparatus 100, 200 offers an opportunity to simplify the division operation since the half-period is accurately available. Using a representation of the period, the resolution of the TDCs can be tuned to so that their measurement of the half-period is a power of two. Then, the digital division operation will become a shift right, and high frequencies may be allowed for the first input signal. This is exemplified in Figure 9.

Figure 9 schematically illustrates example calibration approaches according to some embodiments. More particularly, Figure 9 illustrates that calibration of the TDC range may be achieved so that complicated division of the phase error by the period of the second input signal (e.g., CKV) is not required.

Figure 9 is presented in the context of the arrangements of Figure 8 (upper part of Figure 9 relating to the arrangement 800a and lower part of Figure 9 relating to the arrangement 800b). It should be noted, however, that the calibration approaches may be generalized to other contexts as well.

The calibration approaches are based on the notion that a division operation can be replaced by a shift operation having an offset (in number of bits) of N, which enables high frequency operation. When a digital representation 898, 872 of the period of the second input signal 802 is available, the shift operation can be made equivalent to the division operation by letting calibration tuning be based on a difference between 2^W and (an average of) the digital representation 898, 872 of the period, wherein N is an integer for representing the period digitally as 2^W. For example, a number of stages of the used TDC(s) may be set to 2^W plus some margin (which may be zero or positive; e.g., to accommodate process variation).

The TDC calibration can be performed when the TDCs are tunable (e.g., with tunable delay cells). For example, tunability may be implemented using current starvation, tuneable resistors, tunable capacitors, or any other suitable approach.

To exemplify the concept, it may be supposed that the average estimated period is represented by 69. Then, the closest power of 2 is 64, and the TDC resolution may be tuned to be slightly large (e.g., by decreasing current consumption in a pulse modifying stage) until the average estimated period becomes represented by 64.

The upper part of Figure 9 illustrates calibration circuitry 900 for tuning of the TDCs of any of the arrangements 800a, 800b. The calibration circuitry 900 is configured to set a TDC resolution for any one or more of the TDCs 851, 852, 853 (represented by 851 in the Figure) based on a digital control signal 905 associated with N. The association with N is manifested by 903, wherein an average (AVG) 902 of the period representation 898 is subtracted from 2^W (as represented by 904). Thus, the digital control signal 905 is provided by removal of a period average of the second input signal from a digital word 904 where only a bit representing the ratio is set.

The calibration circuitry 900 is also configured to (right) shift the digital pulse length representation by a number of bits N that corresponds to the integer for representing the period digitally, thereby matching a division corresponding to the half-period being 2^W.

The output 906 of the shifting circuitry (SH) 901 corresponds to a phase error signal (e.g., for feedback in a DPLL).

The lower part of Figure 9 illustrates calibration circuitry 910 for tuning of the arrangement 800b.

The calibration circuitry 910 is configured to set a TDC resolution for the TDCs 851, 852 based on a digital control signal 915 associated with N. The association with N is manifested by 913, wherein an average (AVG) 912 of the period representation 872 is subtracted from 2^W (as represented by 914). The period representation 872 may be for a half-period or a full period. Thus, the digital control signal 915 is provided by removal of a period average of the second input signal from a digital word 914 where only a bit representing the ratio is set. Optionally, a gain factor can be used for the control signal 915 to stabilize the loop as needed.

The calibration circuitry 910 is also configured to (right) shift the digital pulse length representation by a number of bits N that corresponds to the integer for representing the period digitally, thereby matching a division corresponding to the half-period being 2^W.

Offset is removed from the output 916 of the shifting circuitry (SH) 911 by addition of a correction factor 883' which is determined by an offset calculator (OC) 880' based on the phase difference representation 889. For example, the offset calculation may be similar as described before, while only the error signal 889 needs to be observed for the calibration situation, since the period is known as 2^W.

Figure 10 schematically illustrates an example electronic device 1010 according to some embodiments.

The electronic device 1010 may, for example, be a (e.g., wireless) communication device (e.g., a user equipment - UE, or a radio access node). Alternatively or additionally, the electronic device 1010 may, for example, be an integrated circuit, which may - in turn - be comprised (or comprisable) in a communication device.

The electronic device 1010 comprises an apparatus (APP) 1000 as described herein (e.g., one of the apparatuses 100, 200 of Figures 1 and 2). Within the electronic device 1010, the apparatus 1000 may be comprised in an arrangement (ARR) 1001 (e.g., one of the arrangements 800a, 800b of Figure 8) and/or in a DPLL 1002 (e.g., the DPLL 1100 of Figure 11).

Figure 11 schematically illustrates an example digital phase-locked loop (DPLL) 1100 according to some embodiments. The DPLL 1100 is merely intended as a schematic illustration. Thus, it should be understood that other DPLL structure may be equally applicable, and that the DPLL 1100 may further comprise one or more other functional blocks that those shown in Figure 11.

The DPLL 1100 uses a PFD-TDC arrangement (ARR) 1110. For example, the arrangement 1110 may be one of the arrangements 800a, 800b of Figure 8, or any other suitable arrangement where one of the PFD apparatuses 100, 200 of Figures 1 and 2 is combined with a suitable collection of TDCs.

The PFD-TDC arrangement 1110 receives a first input signal 1101 (compare with 101, 201, 801) and a second input signal 1104 (compare with 102, 202, 802), and outputs a digital representation 1105 of the phase difference between the first input signal 1101 and the second input signal 1104.

After passing through a phase error calculator (PEC) 1140 and a digital low-pass filter (DLF) 1150, the phase difference representation is used to control a digitally controlled oscillator (DCO) 1160. The output 1103 of the oscillator is fed back through a pre-scaler (PS) 1170 and provided as the second input signal 1104.

As already mentioned, using a PFD-TDC arrangement 1110 as described and exemplified herein, no divider is required in the feedback path according to some embodiments. The variable clock signal (CKV) can be fed back directly and used as the second input signal 1104.

Figure 12 schematically illustrates an example digital phase-locked loop (DPLL) 1200 according to some embodiments. For example, the DPLL 1200 may be seen as an exemplification of the DPLL 1100 of Figure 11.

The DPLL 1200 uses a PFD-TDC arrangement (ARR) 1210. For example, the arrangement 1210 may be one of the arrangements 800a, 800b of Figure 8, or any other suitable arrangement where one of the PFD apparatuses 100, 200 of Figures 1 and 2 is combined with a suitable collection of TDCs.

The PFD-TDC arrangement 1210 receives a first input signal 1201 (compare with 101, 201, 801) and a second input signal 1204 (compare with 102, 202, 802), and outputs a digital representation 1205 of the phase difference between the first input signal 1201 and the second input signal 1204.

After passing through a first phase error calculator (PEC) 1240', a fractional portion 1206 of a frequency control word (FCW) signal is subtracted from the phase difference in a first adder (ADD) 1280. The FCW signal is provided by an accumulator (ACC) 1230 based on the first input signal 1201 and a control signal 1202 representing integer and fractional FCW. Then, after passing through a second phase error calculator (PEC) 1240” and a digital low-pass filter (DLF) 1250, the phase difference representation is used to control a digitally controlled oscillator (DCO) 1260. The output 1203 of the oscillator is fed back through a pre-scaler (PS) 1270 and provided as the second input signal 1204.

In some embodiments, a frequency-locked loop (FLL) is also included. In the FLL, a counter (CNT) 1220 provides an integer number 1208 based on the feedback signal 1204, and the integer number 1208 is subtracted from an integer portion 1207 of the FCW signal in a second adder (ADD) 1290. The result 1209 is added to the phase difference in the first adder 1280.

The described embodiments and their equivalents may be realized in hardware. The embodiments may be performed by specialized circuitry. The specialized circuitry may, for example, be associated with or comprised in a device such as a wireless communication device (e.g., a user equipment, UE) or a radio access point (e.g., a base station).

Embodiments may appear within an electronic device (such as a wireless communication device or a radio access point) comprising one or more apparatuses, arrangements, circuitry, and/or logic according to any of the embodiments described herein.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used.

Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims.

For example, in the description of embodiments, the partition of functional blocks into particular units is by no means intended as limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. Furthermore, functional blocks described herein as being implemented as two or more units may be merged into fewer (e.g. a single) unit.

Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever suitable. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Hence, it should be understood that the details of the described embodiments are merely examples brought forward for illustrative purposes, and that all variations that fall within the scope of the claims are intended to be embraced therein.

Claims

1. An apparatus (100, 200) for processing first and second input signals (101, 102, 201, 202), the apparatus comprising: first and second phase frequency detectors, PFDs, (110, 120, 210, 220) each configured to provide leading and subsequent intermediate signals based on two received signals, wherein a combination of pulse lengths of the leading and subsequent intermediate signals indicates phase difference between the two received signals, wherein the first PFD (110, 210) is configured to receive the first input signal (101, 201) and the second input signal (102, 202) as the two received signals, and to provide a first leading intermediate signal (111, 211) and a first subsequent intermediate signal (112, 212), and wherein the second PFD (120, 220) is configured to receive the first input signal (101, 201) and an inverse (102', 202') of the second input signal (102, 202) as the two received signals, and to provide a second leading intermediate signal (121, 221) and a second subsequent intermediate signal (122, 222); and logic circuitry (130, 230) configured to receive the intermediate signals (111, 112, 121, 122, 211, 212, 221, 222) and provide at least two output signals (141, 143, 241, 242, 243), wherein each output signal is based on exclusive OR (232), or inverse exclusive OR (231, 233), between two of the intermediate signals (111, 112, 121, 122, 211, 212, 221, 222), and wherein the two intermediate signals for at least one of the output signals are from different ones of the first and second PFDs (110, 120, 210, 222).

2. The apparatus of claim 1, wherein a pulse length of the output signal that is based on intermediate signals from different PFDs is indicative of one half-period of the second input signal.

3. The apparatus of any of claims 1 through 2, wherein one of the output signals (242) is a first type output signal which is based on the first and second leading intermediate signals (211, 221), or on the first and second subsequent intermediate signals (212, 222). 4. The apparatus of claim 3, wherein the first type output signal comprises exclusive OR, or inverse exclusive OR, between the two of the intermediate signals.

5. The method of any of claims 3 through 4, wherein a pulse length of the first type output signal corresponds to one half-period of the second input signal.

6. The apparatus of any of claims 1 through 5, wherein one of the output signals (241, 243) is a second type output signal which is based on one leading intermediate signal (211, 221) and one subsequent intermediate signal (212, 222).

7. The apparatus of claim 6, wherein the second type output signal is based on one leading intermediate signal and one subsequent intermediate signal from different ones of the first and second PFDs (210, 220).

8. The apparatus of any of claims 6 through 7, wherein the second type output signal comprises inverse exclusive OR, or exclusive OR, between one leading intermediate signal and one subsequent intermediate signal.

9. The apparatus of any of claims 6 through 8, wherein a pulse length of the second type output signal corresponds to one half-period of the second input signal, or a multiple thereof, plus phase difference between the first and second input signals.

10. The apparatus of any of claims 1 through 9, wherein the at least two output signals comprise: one output signal (242) based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals; and one output signal (241, 243) based on one leading intermediate signal and one subsequent intermediate signal.

11. The apparatus of any of claims 1 through 10, wherein the at least two output signals comprise: one output signal (241) based on the first leading intermediate signal and one subsequent intermediate signal; and one output signal (243) based on the second leading intermediate signal and one different subsequent intermediate signal. e apparatus of any of claims 1 through 11, wherein exclusive OR (231, 232, 233) is implemented by an exclusive OR gate (400, 500) comprising first and second circuits (410, 420, 510, 520), wherein each of the first and second circuits implements an exclusive OR function between first and second circuitry inputs to provide a circuitry output, wherein the first and second circuits have the same circuit structure, wherein the first and second circuitry inputs are switched for the second circuit compared to the first circuit, and wherein an output (403, 503) of the exclusive OR gate is connected to the circuitry output of both first and second circuits. exclusive OR gate (400, 500) comprising first and second circuits (410, 420, 510, 520), wherein each of the first and second circuits implements an exclusive OR function between first and second circuitry inputs to provide a circuitry output, wherein the first and second circuits have the same circuit structure, wherein the first and second circuitry inputs are switched for the second circuit compared to the first circuit, and wherein an output (403, 503) of the exclusive OR gate is connected to the circuitry output of both first and second circuits. arrangement (800a, 800b) comprising: the apparatus (100, 200) of any of claims 1 through 12; two or more time-to-digital converters (851, 852, 853), TDCs, each configured to receive one of the output signals (841, 842, 843) provided by the apparatus and to provide a corresponding digital pulse length representation, wherein each of the TDCs is a pulse length modifying TDC; and processing circuitry configured to indicate phase difference between the first and second input signals based on the digital pulse length representations provided by the TDCs. e arrangement of claim 14, wherein pulse length modification comprises pulse length shrinking or pulse length extension. e arrangement (800b) of any of claims 14 through 15, wherein the phase difference is provided as a division between first and second digital pulse length representations, wherein the first pulse length representation corresponds to an output signal (841) from the apparatus based on one leading intermediate signal and one subsequent intermediate signal, and the second pulse length representation corresponds to an output signal (842) based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals.

17. The arrangement (800a) of any of claims 14 through 15, wherein the phase difference is provided by biasing an average of two or more digital pulse length representations (871, 873), each digital pulse length representation corresponding to an output signal (841, 843) from the apparatus based on one leading intermediate signal and one subsequent intermediate signal, wherein the biasing is associated with one half-period of the second input signal.

18. The arrangement of any of claims 14 through 17, wherein the processing circuitry is further configured to indicate period of the second input signal based on the digital pulse length representations provided by the TDCs.

19. The arrangement (800b) of claim 18, wherein the period of the second input signal is provided as a pulse length representation (872) corresponding to an output signal (842) based on the first and second leading intermediate signals, or on the first and second subsequent intermediate signals.

20. The arrangement (800a) of claim 18, wherein the period of the second input signal is provided (898) as twice of a difference between two digital pulse length representations (871, 873), each corresponding to an output signal (841, 843) from the apparatus based on one leading intermediate signal and one subsequent intermediate signal.

21. The arrangement of any of claims 14 through 20 further comprising calibration circuitry (900,

910) for tuning of the arrangement, wherein the calibration circuitry is configured to set a TDC resolution based on a digital control signal associated with an integer N for representing the period digitally as 2^W.

22. The arrangement claim 21, wherein the calibration circuitry is configured to vary the TDC resolution until a period average of the second input signal is representable by a digital word where only an /V^th bit is set.

23. The arrangement of claim 22, wherein the digital control signal is provided as a difference between the digital word where only the /V^th bit is set, and the period average of the second input signal.

24. The arrangement of any of claims 21 through 23, wherein the calibration circuitry is further configured to implement a division operation by shifting the digital pulse length representation by a number N of bits that corresponds to the integer for representing the period digitally.

25. A digital phase-locked loop (1002, 1100), DPLL, comprising the apparatus of any of claims 1 through 12, and/or the arrangement of any of claims 14 through 23. 26. An integrated circuit comprising the apparatus of any of claims 1 through 12, and/or the arrangement of any of claims 14 through 24, and/or the DPLL of claim 25.

27. An electronic device (1010) comprising the apparatus of any of claims 1 through 12, and/or the arrangement of any of claims 14 through 24, and/or the DPLL of claim 25, and/or the integrated circuit of claim 26. 28. The electronic device of claim 27, wherein the electronic device is a communication device.