EP4581663A1 - Procédé de production d'un composant semi-conducteur et composant semi-conducteur - Google Patents

Procédé de production d'un composant semi-conducteur et composant semi-conducteur

Info

Publication number
EP4581663A1
EP4581663A1 EP23764303.6A EP23764303A EP4581663A1 EP 4581663 A1 EP4581663 A1 EP 4581663A1 EP 23764303 A EP23764303 A EP 23764303A EP 4581663 A1 EP4581663 A1 EP 4581663A1
Authority
EP
European Patent Office
Prior art keywords
layer
silicon
doping
compound semiconductor
iii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP23764303.6A
Other languages
German (de)
English (en)
Inventor
Frank Dietz
Michael MENSING
Heiko ZÜGE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Publication of EP4581663A1 publication Critical patent/EP4581663A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0116—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 

Definitions

  • III-V compound semiconductors for example gallium nitride, GaN
  • a functional basis i.e. as an active layer, of semiconductor components, for example in field effect transistors, in particular in high electron mobility transistors (HEMT), or in PN diodes.
  • An ohmic contact for contacting an active layer made of a III-V compound semiconductor has so far been produced by means of a metallization stack, i.e. a layer stack made of a combination of different metals and its alloy.
  • a metallization stack i.e. a layer stack made of a combination of different metals and its alloy.
  • the application and alloying of the metals can limit compatibility with other manufacturing methods, especially CMOS technology.
  • the metals can cause undesirable contamination.
  • US 2022/1 15525 A1 and US 2019/0115448 A1 each describe a HEMT in which metal or doped poly-silicon is used for contacting.
  • a HEMT in which metal or doped poly-silicon is used for contacting.
  • the article “Novel Poly-Si/GaN Vertical Heterojunction Diode,” Emori et al., Materials Science Forum Vols. 821 -823 (2015) pp 1015-1018 a transition between n(+)-type poly-silicon and n(-)-type GaN with a doping of 2x10 16 cm -3 is also described.
  • the method according to the invention can be particularly suitable for integration into CMOS processes.
  • the use of doped silicon instead of metals can simplify the manufacturing process, since the structuring of silicon can be implemented more easily, for example by etching processes, compared to metals, which are usually structured using lift-off processes.
  • FIG. 5 illustrates a vertical diode according to an embodiment.
  • Embodiments of the present disclosure are described in detail below using the accompanying descriptions. In the following description, many details are described to provide a more thorough explanation of embodiments of the disclosure. However, it will be apparent to those skilled in the art that other embodiments may be implemented without these specific details.
  • Features of the different exemplary embodiments described can be combined with one another, unless features of a corresponding combination are mutually exclusive or such a combination is expressly excluded.
  • FIG. 1 shows a flow chart of a method 100 for producing a semiconductor component according to an exemplary embodiment.
  • 2A shows a schematic representation of a semiconductor component 1 produced using the method 100 according to an exemplary embodiment.
  • the method 100 according to FIG. 1 is explained below with reference to the semiconductor component 1 illustrated in FIG. 2.
  • the method 100 has a step 110.
  • step 110 a layer structure of the semiconductor component is provided, which has a first layer 10.
  • the layer structure can have further layers.
  • the first layer 10 comprises a III-V compound semiconductor material.
  • the first layer may consist of the III-V compound semiconductor material. This means that, apart from impurities, ie unintentional impurities, the first layer can consist of the III-V compound semiconductor material, in which case the III-V compound semiconductor material can optionally contain a doping material. That is, in examples, the first layer may consist of an III-V compound semiconductor material doped with a doping material.
  • the method 100 further includes a step 120. In step 120, a second layer 20 is applied to a major surface region 12 of the first layer 10.
  • the method 100 has a step 130.
  • the second layer 20 is activated to form an ohmic contact between the first layer and the second layer.
  • activation 130 may include annealing the silicon with the dopant material.
  • the second layer 130 can be heated or tempered.
  • an ohmic contact can form between the first layer and the second layer. After step 130, an ohmic contact can therefore exist between the first layer 10 and the second layer 20.
  • the first layer 10 can be, for example, a functional basis of the semiconductor component.
  • the first layer 10 may be an active layer of the semiconductor device.
  • the first layer 10 can be designed in such a way that it provides a conduction channel in at least one operational state of the semiconductor component, i.e. that it is electrically conductive.
  • the first layer can be electrically connected or contacted by electrically contacting the second layer 20.
  • the production of an ohmic contact to doped silicon is again possible with a metal layer, although in contrast to direct contacting of the III-V compound semiconductor with metal, no complex metallization stacks and no alloy are necessary.
  • the method 100 can be designed to be CMOS-compatible in contrast to conventional methods for contacting III-V compound semiconductors.
  • the method 100 is CMOS compatible.
  • the method 100 is part of a CMOS process.
  • a layered structure is understood to mean, for example, a structure that has one or more layers, the layers being arranged along a stacking direction and each extending in a plane perpendicular to this stacking direction.
  • Each layer of the layer structure can, for example, have two opposing main surfaces which extend perpendicular to this stacking direction.
  • the main surfaces can be connected by secondary surfaces.
  • a main surface can be composed of several main surface regions, which are not necessarily connected. That is, a layer of the layered structure may, in examples, be formed by multiple contiguous or non-contiguous parts, the major surface regions of which may, for example, but not necessarily, lie in a common plane.
  • the stacking direction along which the multiple layers are arranged is parallel to a surface normal of a layer.
  • a direction perpendicular to the surface normal of a layer of the layered structure may be referred to, for example, as a lateral direction or as a direction parallel to the layered structure or as a direction parallel to one of the plurality of layers of the layered structure.
  • the layer structure can be characterized, for example, in that two of its layers are separated from one another by at least an interface.
  • the interface between two adjacent layers of the layer structure can therefore be formed by the main surfaces of the two layers facing each other.
  • An interface can therefore represent a transition between a material of a layer of the layer structure to a material of the adjacent layer of the layer structure.
  • the major surface region 12 of the first layer 10 to which the second layer 20 is applied includes a major surface of the first layer 10 complete.
  • the main surface region 12 comprises only a part of the main surface of the first layer 10.
  • the main surface region 12 can be formed contiguously or have several subregions.
  • FIG. 2B A further example is shown in which the main surface region 12 has two sub-regions.
  • the second layer 20 is applied to the first layer 10 in areas.
  • the second layer 20 comprises the exemplary number of two subregions 20a and 20b.
  • step 120 takes place in such a way that the doping material for the silicon of the second layer is introduced into the silicon during the application of the silicon to the first layer 10.
  • the silicon and the doping material for the silicon are simultaneously deposited on the first layer.
  • the step 120 of applying the second layer 20 can be carried out using CVD or PVD, for example using PECVD or LPCVD.
  • the silicon of the second layer 20 is amorphous or polycrystalline.
  • the III-V compound semiconductor material of the first layer 10 is doped, i.e. contains a doping material.
  • the first layer can be an active layer of the semiconductor component and, for example, can be designed to be conductive at least in an operational state of the component. This can be achieved by doping the III-V compound semiconductor material.
  • an atomic density of the doping material for the III-V compound semiconductor material in the first layer 10 is between 10 17 cm -3 and 10 23 cm' 3 or between 10 18 cm' 3 and 10 21 cm -3 .
  • a contact with an ohmic characteristic and a particularly low contact resistance between the first and second layers can be achieved by doping more than 10 17 cm' 3 (for example, in particular with p-type doping). Particularly for dopings of more than 10 18 cm' 3 (for example, especially with n-type doping), a particularly low contact resistance can be achieved.
  • the III-V compound semiconductor material is in the example of GaN with a silicon or magnesium doping.
  • silicon atoms of the second layer may diffuse into an interface region of the first layer adjacent the main surface region 12. This can result in increased doping of the III-V compound semiconductor in examples in the interface region, particularly in exemplary embodiments with silicon-doped GaN as the III-V compound semiconductor material.
  • the diffusion depth can be a few nm, e.g. less than 10 nm.
  • a layer thickness of the second layer can, for example, be in a range between 50 nm and 2000 nm, or in a range between 100 nm and 500 nm.
  • the type (n-type or p-type) of doping of the silicon of the second layer 20 and the III-V compound semiconductor material of the first layer 10 is the same.
  • both the silicon and the III-V compound semiconductor material are n-type doped; for example, the silicon can be phosphorus doped and the II IV compound semiconductor material can be GaN with silicon doping.
  • the doping material for the GaN may be germanium.
  • both the silicon and the III-V compound semiconductor material can be p-type doped.
  • step 130 of activation takes place by irradiating the layer structure, for example the second layer 20, using electromagnetic radiation.
  • energy can be introduced directly into the second layer to heat it in order to anneal the silicon with the doping material.
  • the electromagnetic radiation may be pulsed.
  • a high power density can be achieved in the pulse, which means rapid heating, i.e. a large temporal temperature gradient, can be achieved.
  • Faster heating may lead to a better result in terms of ohmic characteristics and/or a low contact resistance of the contact between the first layer and the second layer.
  • the irradiation with electromagnetic radiation is carried out using a laser scanning method.
  • a laser beam can be guided over the second layer to activate it.
  • a pulsed laser beam can be focused on a position of the second layer and the position scanned across the second layer. This can be done, for example, so that adjacent positions overlap.
  • activation 130 can take place by means of thermal heating, for example in an oven process or in an RTA process.
  • heating the second layer 20 can be done by heating the first layer 10.
  • the method 100 may optionally have a further step 140.
  • step 140 as illustrated in FIG. 3 according to an exemplary embodiment, a contact structure 30 is produced on a main surface region 22 of the second layer 20 facing away from the first layer 10.
  • One or more additional layers are applied to the main surface region 22 of the second layer.
  • a first additional layer is applied to the main surface region 22 of the second layer, and optionally one or more additional layers is applied to the first additional layer.
  • the contact structure is designed to produce an ohmic contact between the second layer 20 and the contact structure 30 (e.g., between the second layer 20 and a main surface region 32 of the contact structure 30 facing away from the second layer).
  • An ohmic contact can therefore exist between the main surface region 32 of the contact structure and the first layer 10.
  • the contact structure can then be bonded or soldered, for example.
  • Embodiments of the invention relate to semiconductor components produced using the method 100.
  • the semiconductor components 1, 4, 5 described in FIGS. 2A, 2B, and 3 and in FIGS. 4 and 5 described below also represent exemplary embodiments of the invention.
  • Examples of the semiconductor component 1 that can be produced using the method 100 are described below. However, designs and types other than those described below can also be produced using method 100.
  • the HEMT 4 shows a schematic representation of a HEMT 4, which can be produced using the method 100 according to an exemplary embodiment.
  • the HEMT 4 can optionally be an example of the semiconductor component 1.
  • the second layer 20 has two Partial areas 20a and 20b, which can each have an ohmic contact with the first layer 10.
  • the two subregions 20a, 20b of the second layer can therefore function as source and drain contacts of the HEMT.
  • the III-V compound semiconductor material of the second layer can be, for example, GaN, for example, doped GaN, or, for example, AIGaN, or, for example, doped AlN.
  • the first layer 10 can be arranged between a substrate 41 and the second layer 20.
  • the substrate can, for example, be made of silicon, Qromis Substrate Technology (QST), alternative thermal expansion coefficient-matched substrates (CTE-matched substrates) or an III-V compound semiconductor material, e.g. GaN, or have one of these materials.
  • QST Qromis Substrate Technology
  • CTE-matched substrates CTE-matched substrates
  • III-V compound semiconductor material e.g. GaN
  • a stress compensation layer 42 can be arranged between the substrate 41 and the first layer 10, which can alternatively be referred to as a lattice adjustment layer.
  • the substrate 41 and the first layer 10 may each be arranged on one of two opposing main surface regions of the stress compensation layer 42.
  • an intermediate layer 51 with or made of a III-V compound semiconductor material can be arranged between the first first layer 10i and the second first layer I O2, for example, apart from the doping, made of the same material as the layers 10i and 102.
  • the intermediate layer 51 can be undoped or not intentionally doped.

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  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de production d'un composant semi-conducteur comprenant les étapes consistant à : fournir une structure de couche du composant semi-conducteur, la structure de couche ayant une première couche, et la première couche ayant un matériau semi-conducteur de composé III-V; appliquer une seconde couche sur une région de surface principale de la première couche de telle sorte que la seconde couche ait du silicium et un matériau de dopage pour le silicium; et activer la seconde couche afin de former un contact ohmique entre la première couche et la seconde couche.
EP23764303.6A 2022-09-01 2023-08-30 Procédé de production d'un composant semi-conducteur et composant semi-conducteur Pending EP4581663A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102022209112.4A DE102022209112A1 (de) 2022-09-01 2022-09-01 Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement
PCT/EP2023/073821 WO2024047119A1 (fr) 2022-09-01 2023-08-30 Procédé de production d'un composant semi-conducteur et composant semi-conducteur

Publications (1)

Publication Number Publication Date
EP4581663A1 true EP4581663A1 (fr) 2025-07-09

Family

ID=87889797

Family Applications (1)

Application Number Title Priority Date Filing Date
EP23764303.6A Pending EP4581663A1 (fr) 2022-09-01 2023-08-30 Procédé de production d'un composant semi-conducteur et composant semi-conducteur

Country Status (4)

Country Link
US (1) US20250210359A1 (fr)
EP (1) EP4581663A1 (fr)
DE (1) DE102022209112A1 (fr)
WO (1) WO2024047119A1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666454B2 (ja) * 1985-04-23 1994-08-24 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション ▲ｉｉｉ▼―▲ｖ▼族半導体デバイス
US4833042A (en) * 1988-01-27 1989-05-23 Rockwell International Corporation Nonalloyed ohmic contacts for n type gallium arsenide
US9111905B2 (en) * 2012-03-29 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
US20190115448A1 (en) 2016-05-12 2019-04-18 The Regents Of The University Of California Iii-nitride vertical transistor with aperture region formed using ion implantation
CN110277311B (zh) * 2018-03-14 2021-07-16 上海大学 提高GaN欧姆接触性能的方法、欧姆接触结构及应用
CN114600253B (zh) 2019-11-26 2025-05-30 苏州晶湛半导体有限公司 半导体结构及其制作方法

Also Published As

Publication number Publication date
US20250210359A1 (en) 2025-06-26
DE102022209112A1 (de) 2024-03-07
WO2024047119A1 (fr) 2024-03-07

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