Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
  • H02M1/4208—Arrangements for improving power factor of AC input
  • H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0003—Details of control, feedback or regulation circuits
  • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
  • H02M1/0074—Plural converter units whose inputs are connected in series
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
  • H02M1/007—Plural converter units in cascade
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
  • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
  • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
  • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/483—Converters with outputs that each can have more than two voltages levels
  • H02M7/4833—Capacitor voltage balancing

Definitions

• the disclosure relates to the field of power conversion between direct current (DC) and alternating current (AC) power networks or power grids, in particular in light load conditions.
• the disclosure particularly relates to techniques for individual capacitor voltage balancing in light load conditions for unity power factor (UPF) solid state transformers (SST).
• UPS unity power factor
• Solid State Transformers apply Multi-Module Multi-level topologies for power conversion between AC grids and DC grids.
• Modular multilevel cascaded converters based on Unity Power Factor Rectifiers (UPFR) are a prevalent solution to achieve the SST implementation.
• UPFR Unity Power Factor Rectifiers
• control of the DC-Link voltages under light load conditions is challenging.
• PWM Pulse Width Modulation
• the Unity Power Factor Rectifier especially in the vicinity of zero-crosses.
• DCM discontinuous conduction mode
• the disclosure provides a solution for an efficient control scheme and a respective power converter for an efficient control in light load situations in order to overcome the abovedescribed problems.
• this disclosure considers the substitution of the interleaving PWM implementation by a new sorting-based algorithm in which the less charged dc-link voltages set the switching-on conditions. I.e., the branch current flows through and charges the less charged dc-links for a whole sampling period. In the case of multiple dc-links per module, it is possible to charge only the less charged submodules.
• the disclosed sorting modulation method works well in DCM, so the current total harmonic distortion (THDi) is large. Really, a large THDi is a consequence of switching operation with a very low active power handling. Nevertheless, the disclosed technique better handles the non-linearity and achieves a robust performance and full controllability, which is not the case of standard PWM with phase interleaving.
• the modules may be designed for unity power factor operation, e.g., unity power factor rectifiers.
• This kind of solution are of high commercial value for power electronics power supplies, e.g., power supplies for data centers, but they also present operational challenges, such as working in light load conditions: control becomes difficult and power quality tends to be poor.
• the novel technique presented in this disclosure drastically improves the quality of the current/voltage waveforms by adding a new sorting modulation method to work during the light load operation.
• SSTs are a power electronic based alternative to line-frequency transformers (LFTs).
• LFTs are classic elements of transmission and distribution to interface different voltage levels in AC grids.
• LFTs are cost effective, highly efficient with high loads and reliable. However, they suffer from several limitations, including voltage drop under load, sensitivity to harmonics, load imbalances and de offsets, no overload protection, and low efficiency when operating with light loads.
• SSTs are based on power electronics switches, sensors and intelligent controls, which enable advanced functionalities, such as, power flow control; reactive power, harmonics, and imbalances compensation; smart protection and ride- through capabilities.
• high switching frequency operation enables a significant reduction of the volume and weight.
• MV medium voltage in this disclosure between 1500V and 30kV, for example
• converters i.e., power converters and power electronics converters are described.
• Power converters are applied for converting electric energy from one form to another, such as converting between DC and AC or AC and DC or between DC and DC, e.g., between low voltage DC and high or medium voltage DC.
• Power converter can also change the voltage or frequency or some combination of these.
• Power electronics converters (including some type of power electronics, such as transistors, diodes, etc.) are based on power electronics switches that can be actively controlled by applying ON/OFF logic (i.e., PWM operation, usually commanded by a closed loop control algorithm).
• the disclosure relates to a power converter for power conversion between a DC power network and an AC power network, the power converter comprising a first phase branch, the first phase branch comprising a plurality of power conversion modules connected in series, wherein each power conversion module comprises: at least one coupleable conversion path for converting a DC voltage into an AC voltage of the power conversion module or for converting an AC voltage into an DC voltage of the power conversion module; and a controllable coupling network configured to couple the at least one conversion path into the power conversion module or to decouple the at least one conversion path from the power conversion module in response to a control signal, wherein the power converter further comprises: a controller configured to generate the control signals for controlling the coupling networks of the plurality of power conversion modules based on a coupling scheme, wherein the coupling scheme prioritizes the conversion paths of the plurality of power conversion modules with respect to a value of the DC voltage at the respective conversion path.
• Such power converter is advantageous in light load situations or discontinuous conduction mode.
• the nonlinearity can be better handled, and a robust performance and full controllability can be achieved which is not the case in standard PWM with phase interleaving.
• a conversion path converting a DC voltage with a lower DC value has a higher priority than a conversion path converting a DC voltage with a higher DC value.
• This prioritization provides the advantage that the low voltages are processed with priority. This results in a better performance in light load conditions due to a better resolution of the conversion paths.
• each power conversion module comprises: a first DC terminal; a second DC terminal; and a third DC terminal, wherein a first conversion path is arranged between the first DC terminal and the third DC terminal, wherein a second conversion path is arranged between the third DC terminal and the second DC terminal, wherein a third conversion path is arranged between the first DC terminal and the second DC terminal.
• This partitioning into different conversion paths provides the advantage that DC links of a higher resolution can be individually added which results in a higher resolution for selecting the different conversion paths and hence a better performance of the power converter, especially in light load situations.
• the coupling network comprises: a first bidirectional switch coupled between a first AC terminal and the third DC terminal; and a second bidirectional switch coupled between a second AC terminal and the third DC terminal.
• each power conversion module comprises a first conversion path, a second conversion path and a third conversion path, the first conversion path comprising a first DC-link capacitor, the second conversion path comprising a second DC-link capacitor, and the third conversion path comprising a series connection of the first DC-link capacitor and the second DC-link capacitor.
• the first DC-link capacitor is coupled between the first DC terminal and the third DC terminal; and the second DC-link capacitor is coupled between the third DC terminal and the second DC terminal.
• each power conversion module comprises: a first diode coupled between the first AC terminal and the first DC terminal; a second diode coupled between the second AC terminal and the first DC terminal; a third diode coupled between the second DC terminal and the first AC terminal; and a fourth diode coupled between the second DC terminal and the second AC terminal.
• the power conversion module is configured to provide an AC current which is in phase with the AC voltage of the power conversion module.
• the controller is configured to determine the value of the DC voltage converted by the respective conversion path based on a phase-angle measurement of the AC voltage, a DC-link voltage reference value and respective voltages in each of the DC-link capacitors.
• the controller is configured to sort the voltages of the first and second conversion paths of the plurality of power conversion modules assigning a priority to the first and second conversion paths.
• This prioritization of the conversion paths provides the advantage of better resolution in light load situations, thus achieving better controllability and robust behavior of the power converter.
• the controller is configured to add the DC voltages converted by the sorted conversion paths and to compare the added DC voltages against an AC voltage reference value.
• the controller is configured to determine a subset of the sorted conversion paths which added DC voltages have a minimum difference to the AC voltage reference value.
• the controller is configured to couple the conversion paths from the subset of conversion paths into the power conversion module and to decouple the remaining conversion paths from the power conversion module using the coupling scheme to determine the control signals.
• the controller is configured to receive information indicating a light load condition and to control the coupling based on the coupling scheme only when the light load condition is indicated.
• the controller is configured to disable an integration of respective voltages in each of the DC-link capacitors when the information indicating the light load condition is received.
• DC-link control implements only a proportional when working under light load conditions.
• the dc-link controller may provide a current or a power reference, depending on the implementation alternatives already covered in the prior art.
• the Integrator part may be disconnected to avoid negative power/current references that may push the UPFR to instability.
• the disclosure relates to a method for providing a control signal to a power converter according to the first aspect, the method comprising: sorting DC-link halves, i.e., values of the DC voltages at the respective conversion paths associated to the respective DC link capacitor, according to their measured voltage by using a sorting algorithm, wherein lower voltages are assigned with higher priority than higher voltages; connecting capacitors of higher priority in an order according to their priority until the sum of their measured voltages is the one that minimizes a difference with the voltage reference; and defining the control signal for each leg of IGBT switches according to a look-up table, the look-up table determining for each SST state including AC voltage v in and control signals d top and d bo ttom, the corresponding connected capacitors Ctop and Cpottom-
• Such a method shows superior performance in light load situations or discontinuous conduction mode.
• the non-linearity can be better handled, and a robust performance and full controllability can be achieved which is not the case in standard PWM with phase interleaving.
• Such a lookup table provides a better controllability and prioritization of the different conversion paths resulting in superior performance in DCM and light load conditions.
• the disclosure relates to a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the method according to the second aspect described above and below with respect to Figure 3.
• the computer program product may run on a controller or a processor for controlling the above-described power converter, e.g., a controller according to the first aspect as described above.
• the disclosure relates to a computer-readable medium, storing instructions that, when executed by a computer, cause the computer to execute the method according to the second aspect described above.
• a computer readable medium may be a non-transient readable storage medium.
• the instructions stored on the computer-readable medium may be executed by a controller or a processor for controlling the above-described power converter.
• Figure 1 shows a block diagram of a power converter 100 in a multilevel modular configuration for power conversion between a DC power network 110 and an AC power network 120 according to the disclosure
• FIG. 2 shows a block diagram of an individual power converter module 141 , i.e., SST cell of the power converter 100 shown in Figure 1 and a coupling scheme 170 for the power converter module 141 according to the disclosure;
• FIG 3 shows a block diagram of a controller 300 implementing an exemplary voltage sorting modulation method according to the disclosure for the power converter modules 141 shown in Figures 1 and 2;
• Figures 4a and 4b show performance diagrams of the DC voltage waveforms obtained from a simulation of the voltage sorting modulation method 300 shown in Figure 3, where Figure 4b shows a zoom view of the diagram of Figure 4a;
• Figure 5 shows exemplary current waveforms for the simulation of the voltage sorting modulation method 300 under light load conditions
• Figure 6 shows exemplary voltage waveforms for the simulation of the voltage sorting modulation method 300 under light load conditions.
• Solid State Transformers SST
• the Solid-State Transformer technology can be applied in datacenters and other applications, for example.
• SST technology may utilize multi-module multi-level topologies when interfacing medium voltage (MV) AC grids.
• IOP Input Series Output Parallel
• MV medium voltage
• LV Low voltage
• the DC-DC converter delivers power from the cell DC-link to the common LVDC grid (i.e., output parallel); to do so, the DC-DC topology should provide galvanic isolation.
• Series resonant converter (SRC) working in open loop (50% duty cycle) are a simple yet widely considered solution for the second power stage of ISOP SSTs.
• Modular Multilevel Cascaded Converters are a prevalent solution to achieve the SST implementation.
• Modular Multilevel Cascaded Converters may be based on cascaded-H bridge (CHB) topology, for example.
• CHB cascaded-H bridge
• a four quadrant three-phase cascaded-H bridge (CHB) topology may be connected to the grid.
• the AC output voltage can be synthesized by the sum of modules in the same branch. This can be achieved by a proper operation of the power electronics switches (e.g., IGBTs or MOSFETs) that connect/disconnect the DC-links to the AC side via the turn on/off of the devices.
• the power electronics switches e.g., IGBTs or MOSFETs
• the switching combinations for each module set the AC output voltages to be v dc , 0 or -v dc .
• the use of multiple modules has the following advantages: i) the power electronics switches are suited for a low voltage class, which in practice allows to use low voltage power electronics technologies in high/medium voltage applications; ii) the power quality of the AC output voltage waveform increases with the number of modules; more voltage levels implies less harmonics; iii) related to previous point, the output filter effort is reduced as the output harmonics are less and less significant.
• the advantages of multilevel converters are at the cost of increasing the complexity; both in terms of topology and control.
• the ISOP SST concept can be optimized for applications in which the power delivery is always in the same direction; more specifically, the SST is a power electronics-based load. In that scenario, the four- quadrant cells can be substituted by unity power factor PWM topologies.
• Unity Power Factor Rectifiers can be used as building block for Cascade H-Bridge (CHB) based SST.
• Key features of the UPFR based approach are: a) Power conversion is constrained to work with power factor equal to 1 (assuming an ideal system without harmonics, only fundamental components, the AC current and the ac voltage are in- phase); b) Simple Layout and High power density is achieved (e.g., diodes are simpler than active devices); c) High frequency PWM operation: i) reduced size of magnetics and Cost effective; ii) High power quality: low Total Harmonic Distortion THD, in output current and voltage in the point of connection are achievable; d) Vector control and PWM techniques, similar to the ones employed in Four quadrants CHB, are suitable. Especially for data center applications, these features are of high interest.
• the disclosed modulation method presented hereinafter is only dependent on the power consumption, but not on the DC-DC topology or control method. Hence, the disclosed modulation method can be applied in all of the topologies described above for controlling the power conversion.
• Figure 1 shows a block diagram of a power converter 100 in a multilevel modular configuration for power conversion between a DC power network 110 and an AC power network 120 according to the disclosure.
• the power converter 100 comprises a first phase branch 130, e.g., branch C as exemplarily detailed in Figure 1.
• the AC power network 120 can be a multi-phase power grid, e.g., a three-phase power grid as shown in Figure 1.
• the power converter 100 may be analogously designed.
• the first phase branch 130 comprises a plurality of power conversion modules 141 , 142, 143, 144, also called SST cells, wherein the inputs (left-hand side) of the power conversion modules 141 , 142, 143, 144 are connected in series while the outputs (righthand side) of the power conversion modules 141 , 142, 143, 144 are connected in parallel, as can be seen from Figure 1.
• Each power conversion module 141 comprises at least one coupleable conversion path 242, 243, 244, as shown in Figure 2, for converting an AC voltage 146 into a DC voltage 145 of the power conversion module (141) or vice versa.
• Each power conversion module 141 comprises a controllable coupling network 147, as shown in Figure 2, configured to couple the at least one conversion path 242, 243, 244 into the power conversion module 141 or to decouple the at least one conversion path 242, 243, 244 from the power conversion module 141 in response to a control signal 311 , as shown in Figure 3.
• the power converter 100 further comprises a controller 300, as shown in Figure 3, configured to generate the control signals 311 for controlling the coupling networks 147 of the plurality of power conversion modules 141 , 142, 143, 144 based on a coupling scheme 170, as shown in Figures 2 and 3 and described below with respect to Figures 2 and 3.
• the coupling scheme 170 prioritizes the conversion paths 242, 243, 244 of the plurality of power conversion modules 141 , 142, 143, 144 with respect to a value of the DC voltage 145, 145a, 145b at the respective conversion path 242, 243, 244.
• a conversion path converting a DC voltage with a lower DC value can have a higher priority than a conversion path converting a DC voltage with a higher DC value.
• FIG 2 shows a block diagram of an individual power converter module 141 , i.e., SST cell of the power converter 100 shown in Figure 1 and a coupling scheme 170 for the power converter module 141 according to the disclosure.
• Each power conversion module comprises: a first DC terminal 151 ; a second DC terminal 152; and a third DC terminal 153.
• a first conversion path 242 may be arranged between the first DC terminal 151 and the third DC terminal 153.
• a second conversion path 243 may be arranged between the third DC terminal 153 and the second DC terminal 152.
• a third conversion path 244 may be arranged between the first DC terminal 151 and the second DC terminal 152.
• the coupling network 147 may comprise: a first bidirectional switch 147a coupled between a first AC terminal 161 and the third DC terminal 153; and a second bidirectional switch 147b coupled between a second AC terminal 162 and the third DC terminal 153.
• Each power conversion module 141 may comprise a first conversion path 242, a second conversion path 243 and a third conversion path 244.
• the first conversion path 242 may comprise a first DC-link capacitor 163.
• the second conversion path 243 may comprise a second DC-link capacitor 164.
• the third conversion path 244 may comprise a series connection of the first DC-link capacitor 163 and the second DC-link capacitor 164 as shown in Figure 2.
• the first DC-link capacitor 163 may be coupled between the first DC terminal 151 and the third DC terminal 153.
• the second DC-link capacitor 164 may be coupled between the third DC terminal 153 and the second DC terminal 152.
• Each power conversion module 141 may comprise: a first diode D1 coupled between the first AC terminal 161 and the first DC terminal 151 ; a second diode D2 coupled between the second AC terminal 162 and the first DC terminal 151 ; a third diode D3 coupled between the second DC terminal 152 and the first AC terminal 161 ; and a fourth diode D4 coupled between the second DC terminal 152 and the second AC terminal 162.
• the power conversion module 141 may be configured to provide an AC current 148 (i ph ) which is in phase with the AC voltage 146 (y in ) of the power conversion module 141.
• the controller 300 may be configured to determine the value of the DC voltage 145, 145a, 145b converted by the respective conversion path 142, 143, 144 based on a phase-angle measurement of the AC voltage 146, a DC-link voltage reference value 302, as shown in Figure 3, and respective voltages 303 (shown in Figure 3) in each of the DC-link capacitors 163, 164.
• controller 300 Further functionalities of the controller 300 are described below with respect to Figure 3.
• this cell 141 includes, D1 to D4 diodes, T1 to T4 bidirectional, fully controlled switches 147a (e.g., MOSFETS) and two half DC-links capacitors 142, 143 that form a whole DC-link.
• This particular topology permits to connect two different loads per half DC-link, so independent control per half DC-link (e.g., charging the top cap but not the bottom one) is included.
• the description of the embodiment herein is applicable to all the family of UPFR based cells with same operation principle, and of course, for any number of series connected cells, ranging from 1 to infinite.
• FIG 3 shows a block diagram of a controller 300 implementing an exemplary voltage sorting modulation method according to the disclosure for the power converter modules 141 shown in Figures 1 and 2.
• the controller 300 is based on a novel voltage sorting modulation scheme 312 or algorithm as detailed in the block 320 shown at the bottom side of Figure 3.
• This voltage sorting modulation scheme 312 determines the control signals 311 for transmission to the hardware 130, i.e., the different branches of the power converter 100 shown in Figure 1.
• the voltage sorting modulation scheme 312 receives a reference power per phase ph and module m as first input: P p ⁇ m 305, a reference voltage v p r t 308 per phase ph for a number of k phases, a number of k times n voltages 309 per phase ph and module m for the top DC links shown in block 320, and a number of k times n voltages 310 per phase ph and module m for the bottom DC links shown in block 320. For these input signals, the controller 300 determines the control signals 311 for transmission to the hardware 130.
• the reference voltage v p e h f 308 per phase ph for the number of k phases are determined by a current control block 318 that performs current control based on a reference phase current i p e h f 307 and the phase current i ph 305, e.g., applying PR control and Goodwin anti-windup.
• the reference phase current i 307 is determined by a current reference calculation block 317 using the phase voltage v ph 308 phase-locked by a PLL 316, a reference value 306 for the total power reference pff 306 and the reference power P m 305 per phase ph and module m.
• Both reference power values pff 306 and P m 305 are determined by a DC Squared Control block 315 implementing PI control and Goodwin anti-windup.
• This DC Squared Control block 315 evaluates DC voltage reference vff 302, DC phase voltages v dc ph m 303, power sharing 314 and light load condition 301. Under light load condition 301 , integral control and anti-windup of this block 315 can be inactive.
• DC-link control 315 implements only a proportional control (P) when working under light load conditions 301.
• the DC-link controller 315 may provide a current or a power reference, depending on the implementation alternatives.
• the Integrator part (I) may be disconnected to avoid negative power/current references that may push the UPFR to instability.
• the controller 300 may be configured to sort 327 the voltages of the first and second conversion paths 242, 243 of the plurality of power conversion modules 141 , 142, 143, 144 assigning a priority 325, 326 to the first and second conversion paths 242, 243.
• the controller 300 may be configured to add the DC voltages 304 converted by the sorted conversion paths 242, 243 and to compare the added DC voltages 332 against an AC voltage reference value 308.
• the controller 300 may be configured to determine a subset 331 of the sorted conversion paths 242, 243 which added DC voltages 332 have a minimum difference 329 to the AC voltage reference value 308.
• the controller 300 may be configured to couple the conversion paths 242, 243, 244 from the subset 331 of conversion paths into the power conversion module and to decouple the remaining conversion paths from the power conversion module using the coupling scheme 170 to determine the control signals 311 .
• the controller 300 may be configured to receive information indicating a light load condition 301 and to control the coupling based on the coupling scheme only when the light load condition 301 is indicated.
• the controller 300 may be configured to disable an integration 315 of respective voltages 303 in each of the DC-link capacitors 163, 164 when the information indicating the light load condition 301 is received.
• Figure 3 illustrates an exemplary embodiment of the whole control structure (of controller 300) that makes use of this fact to implement a sorting-based modulation method as illustrated in block 320.
• This sorting-based modulation method 312 as illustrated in the block 320 provides the two main functionalities, described in the following:
• DC-link control implements only a proportional (control) when working under light load conditions indicated by 301.
• the DC-link controller 315 may provide a current or a power reference, depending on the existing implementation alternatives.
• the Integrator part (I) may be disconnected to avoid negative power/current references that may push the UPFR to instability.
• the DC link voltage ascending order sorting modulation algorithm 320 is shown in Figure 3.
• the input of the block 320 is the output voltage reference v ph ref 308 from the current control loop 318.
• this voltage reference 308 is made physical by a connection of the set of less-charged dc-link voltages 331 in the whole branch that better match v P h ref 308.
• the series combination of less charged dc-links 331 (series combination implies they add-up to a total output voltage) that provide an output voltage the closest to the given reference v ph ref 308. It understands that this method can be extended to cover trivial/slight modifications to this criterion, such as approximation from top (always above ref) or bottom (always below ref).
• DC-link halves 321 , 322, 323, 324 are sorted according to their measured voltage by using a sorting algorithm 327, e.g., such as bubble sort, etc. This method works with any of the typical sorting algorithms, which must be selected according to hardware specifications, number of levels being the most important one. 2) Lower voltages are assigned with higher priority to be connected to the input.
• a sorting algorithm 327 e.g., such as bubble sort, etc.
• the control signal for each leg of IGBT switches is defined 330 using the look-up table 170, as exemplarily shown on the left side of Figure 3.
• This look-up table 170 determines for each SST state including AC voltage v in 146 and control signals d top 171 and d bo ttom 172, the corresponding connected capacitors C top 163 and Cbottom 164.
• Figures 4a and 4b show performance diagrams of the DC voltage waveforms obtained from a simulation of the voltage sorting modulation method 300 shown in Figure 3, where Figure 4b shows a zoom view of the diagram of Figure 4a.
• FIGS. 4a and 4b are for a 3-phase 7 cells SST.
• a PLECS simulation software was used. The simulations were performed using randomly generated values for the components to account for tolerances.
• DC Link voltage references is 1500 V
• grid voltage is 4000 V
• light load conditions are 20 W for the top module of each phase and 10 W for the remaining ones.
• DC-links start at 0 V and control is enabled at 0.25 seconds.
• the resulting DC link voltage waveform is shown in Figure 4a while Figure 4b shows a zoom view of Figure 4a.
• the disclosed modulation method successfully stabilizes all of the DC links at the voltage reference value.
• the transient 402 and steady-state 403 performance is zoomed in Figure 4b.
• Figure 5 shows exemplary current waveforms for the simulation of the voltage sorting modulation method 300 under light load conditions.
• Figure 6 shows exemplary voltage waveforms for the simulation of the voltage sorting modulation method 300 under light load conditions.
• FIG. 6 shows the evolution of the DC link capacitors’ voltage when they are charging. It is clear in this image that the capacitors with lower voltages are the ones getting connected to the input. Note: the graph uses sampled values, which causes the stair-like appearance of the plot but helps in highlighting the evolution of the voltage between samples.

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• 2022
  • 2022-03-01 CN CN202280090034.7A patent/CN118648226A/zh active Pending
  • 2022-03-01 EP EP22712879.0A patent/EP4470102A1/de active Pending
  • 2022-03-01 WO PCT/EP2022/055038 patent/WO2023165672A1/en not_active Ceased

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