WO2023165672A1

WO2023165672A1 - Techniques for power conversion between dc and ac power networks in light load conditions

Info

Publication number: WO2023165672A1
Application number: PCT/EP2022/055038
Authority: WO
Inventors: Francisco Daniel FREIJEDO FERNÁNDEZ; Álvaro RUBINOS SICRE; Rong Xu
Original assignee: Huawei Digital Power Technologies Co., Ltd.
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2023-09-07

Abstract

The disclosure relates to the field of power conversion between DC and AC power networks, in particular in light load conditions. A power converter (100) comprises a first phase branch (130) which comprises a plurality of power conversion modules (141, 142, 143, 144) connected in series. Each power conversion module comprises at least one coupleable conversion path (242, 243, 244) and a controllable coupling network (147) configured to couple the at least one conversion path (242, 243, 244) into the power conversion module (141) in response to a control signal (311). A controller (300) generates the control signals (311) for controlling the coupling networks (147) based on a coupling scheme (170). The coupling scheme (170) prioritizes the conversion paths (242, 243, 244) with respect to a value of the DC voltage (145, 145a, 145b) at the respective conversion path (242, 243, 244).

Description

TECHNIQUES FOR POWER CONVERSION BETWEEN DC AND AC POWER NETWORKS IN LIGHT LOAD CONDITIONS

TECHNICAL FIELD

The disclosure relates to the field of power conversion between direct current (DC) and alternating current (AC) power networks or power grids, in particular in light load conditions. The disclosure particularly relates to techniques for individual capacitor voltage balancing in light load conditions for unity power factor (UPF) solid state transformers (SST).

BACKGROUND

Solid State Transformers (SST) apply Multi-Module Multi-level topologies for power conversion between AC grids and DC grids. Modular multilevel cascaded converters based on Unity Power Factor Rectifiers (UPFR) are a prevalent solution to achieve the SST implementation. In these architectures, control of the DC-Link voltages under light load conditions is challenging. The problem comes from the fact that the Pulse Width Modulation (PWM) voltage reference is not properly followed by the physical system, i.e., the Unity Power Factor Rectifier, especially in the vicinity of zero-crosses. From the perspective of the current control loop, the problem lies in a poorly performing actuator when the references are of a low amplitude. This sort of problem can also be associated to a discontinuous conduction mode (DCM) of operation.

Previous control methods mostly considered the use of phase interleaved PWM operation together with an individual duty cycle adjustment for each individual module. This has the theoretical advantage of increasing the effective sampling frequency and hence the power quality. However, in the case of light-load, the DCM condition results in the disadvantage that the output voltage is not matching its reference and the effective switching frequency reduction is far from being real. So, in practice, non-linear operation leads to uncontrollability when the branch currents, i.e., the load, is very light.

SUMMARY

The disclosure provides a solution for an efficient control scheme and a respective power converter for an efficient control in light load situations in order to overcome the abovedescribed problems. The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

As opposed to the conventional methods, this disclosure considers the substitution of the interleaving PWM implementation by a new sorting-based algorithm in which the less charged dc-link voltages set the switching-on conditions. I.e., the branch current flows through and charges the less charged dc-links for a whole sampling period. In the case of multiple dc-links per module, it is possible to charge only the less charged submodules.

Of course, the disclosed sorting modulation method works well in DCM, so the current total harmonic distortion (THDi) is large. Really, a large THDi is a consequence of switching operation with a very low active power handling. Nevertheless, the disclosed technique better handles the non-linearity and achieves a robust performance and full controllability, which is not the case of standard PWM with phase interleaving.

This disclosure focuses on the case when the SST interfaces the MV AC grid with series of modules. In one example, the modules may be designed for unity power factor operation, e.g., unity power factor rectifiers. This kind of solution are of high commercial value for power electronics power supplies, e.g., power supplies for data centers, but they also present operational challenges, such as working in light load conditions: control becomes difficult and power quality tends to be poor. The novel technique presented in this disclosure drastically improves the quality of the current/voltage waveforms by adding a new sorting modulation method to work during the light load operation.

Hence, the main focus of the disclosure lies on the SST technologies. SSTs are a power electronic based alternative to line-frequency transformers (LFTs). LFTs are classic elements of transmission and distribution to interface different voltage levels in AC grids. LFTs are cost effective, highly efficient with high loads and reliable. However, they suffer from several limitations, including voltage drop under load, sensitivity to harmonics, load imbalances and de offsets, no overload protection, and low efficiency when operating with light loads. On the other hand, SSTs are based on power electronics switches, sensors and intelligent controls, which enable advanced functionalities, such as, power flow control; reactive power, harmonics, and imbalances compensation; smart protection and ride- through capabilities. Furthermore, high switching frequency operation enables a significant reduction of the volume and weight. Some of these features combined may make SST advantageous when compared with classical LFTs. The techniques described in this disclosure are focused on the power electronics interface with the AC high/medium voltage AC grid.

In order to describe the disclosure in detail, the following terms, abbreviations and notations will be used:

DC direct current

AC alternating current

PWM Pulse Width Modulation

SST Solid State Transformer

ISOP Input Series Output Parallel

MV medium voltage, in this disclosure between 1500V and 30kV, for example

LV low voltage, in this disclosure below 1500V, for example

LFT Line Frequency Transformer

CHB cascaded-H bridge

SRC Series Resonant Converter

THD total harmonic distortion

DCM discontinuous conduction mode

In this disclosure, converters, i.e., power converters and power electronics converters are described. Power converters are applied for converting electric energy from one form to another, such as converting between DC and AC or AC and DC or between DC and DC, e.g., between low voltage DC and high or medium voltage DC. Power converter can also change the voltage or frequency or some combination of these. Power electronics converters (including some type of power electronics, such as transistors, diodes, etc.) are based on power electronics switches that can be actively controlled by applying ON/OFF logic (i.e., PWM operation, usually commanded by a closed loop control algorithm).

According to a first aspect, the disclosure relates to a power converter for power conversion between a DC power network and an AC power network, the power converter comprising a first phase branch, the first phase branch comprising a plurality of power conversion modules connected in series, wherein each power conversion module comprises: at least one coupleable conversion path for converting a DC voltage into an AC voltage of the power conversion module or for converting an AC voltage into an DC voltage of the power conversion module; and a controllable coupling network configured to couple the at least one conversion path into the power conversion module or to decouple the at least one conversion path from the power conversion module in response to a control signal, wherein the power converter further comprises: a controller configured to generate the control signals for controlling the coupling networks of the plurality of power conversion modules based on a coupling scheme, wherein the coupling scheme prioritizes the conversion paths of the plurality of power conversion modules with respect to a value of the DC voltage at the respective conversion path.

Such power converter is advantageous in light load situations or discontinuous conduction mode. By prioritizing the conversion paths with respect to the DC voltage value, the nonlinearity can be better handled, and a robust performance and full controllability can be achieved which is not the case in standard PWM with phase interleaving.

In an exemplary implementation of the power converter, a conversion path converting a DC voltage with a lower DC value has a higher priority than a conversion path converting a DC voltage with a higher DC value.

This prioritization provides the advantage that the low voltages are processed with priority. This results in a better performance in light load conditions due to a better resolution of the conversion paths.

In an exemplary implementation of the power converter, each power conversion module comprises: a first DC terminal; a second DC terminal; and a third DC terminal, wherein a first conversion path is arranged between the first DC terminal and the third DC terminal, wherein a second conversion path is arranged between the third DC terminal and the second DC terminal, wherein a third conversion path is arranged between the first DC terminal and the second DC terminal.

This partitioning into different conversion paths provides the advantage that DC links of a higher resolution can be individually added which results in a higher resolution for selecting the different conversion paths and hence a better performance of the power converter, especially in light load situations.

In an exemplary implementation of the power converter, the coupling network comprises: a first bidirectional switch coupled between a first AC terminal and the third DC terminal; and a second bidirectional switch coupled between a second AC terminal and the third DC terminal. This provides the advantage that by the two bidirectional switches the power conversion module can individually control two half DC link capacitors and the respective DC links. Depending on the polarity of the phase current, the capacitors of the two half DC links can be individually switched-on of switched-off, resulting in a better performance of the power converter.

In an exemplary implementation of the power converter, each power conversion module comprises a first conversion path, a second conversion path and a third conversion path, the first conversion path comprising a first DC-link capacitor, the second conversion path comprising a second DC-link capacitor, and the third conversion path comprising a series connection of the first DC-link capacitor and the second DC-link capacitor.

This provides the advantage that the different capacitors can be individually enabled or disabled, e.g., by using a lookup table. This results in a better controllability of the power converter.

In an exemplary implementation of the power converter, the first DC-link capacitor is coupled between the first DC terminal and the third DC terminal; and the second DC-link capacitor is coupled between the third DC terminal and the second DC terminal.

This provides the advantage that a series connection of the DC links can be implemented, thus, voltages across the capacitors can be added per power conversion module to obtain a high voltage per phase branch.

In an exemplary implementation of the power converter, each power conversion module comprises: a first diode coupled between the first AC terminal and the first DC terminal; a second diode coupled between the second AC terminal and the first DC terminal; a third diode coupled between the second DC terminal and the first AC terminal; and a fourth diode coupled between the second DC terminal and the second AC terminal.

This provides the advantage that a unity power factor rectifier can be implemented working with power factor equal to one. A simple layout and high power density can be achieved, since diodes are simpler than active devices. This design allows reduced size of magnetics and cost savings. Higher power quality can be achieved: Low total harmonic distortion in output current and voltage in point of connection is achievable. In an exemplary implementation of the power converter, the power conversion module is configured to provide an AC current which is in phase with the AC voltage of the power conversion module.

This provides the advantage that the design can be simplified since no phase correction blocks are required.

In an exemplary implementation of the power converter, the controller is configured to determine the value of the DC voltage converted by the respective conversion path based on a phase-angle measurement of the AC voltage, a DC-link voltage reference value and respective voltages in each of the DC-link capacitors.

This provides the advantage that the DC voltage value can be easily determined by measuring or determining the above values.

In an exemplary implementation of the power converter, the controller is configured to sort the voltages of the first and second conversion paths of the plurality of power conversion modules assigning a priority to the first and second conversion paths.

This prioritization of the conversion paths provides the advantage of better resolution in light load situations, thus achieving better controllability and robust behavior of the power converter.

In an exemplary implementation of the power converter, the controller is configured to add the DC voltages converted by the sorted conversion paths and to compare the added DC voltages against an AC voltage reference value.

This provides the advantage that the added DC voltages are very close to the AC voltage reference value resulting a precise power conversion.

In an exemplary implementation of the power converter, the controller is configured to determine a subset of the sorted conversion paths which added DC voltages have a minimum difference to the AC voltage reference value.

This provides the advantage that the subset can be easily determined and hence the DC voltages to be added for providing the respective conversion value. In an exemplary implementation of the power converter, the controller is configured to couple the conversion paths from the subset of conversion paths into the power conversion module and to decouple the remaining conversion paths from the power conversion module using the coupling scheme to determine the control signals.

This provides the advantage that the coupling scheme provides an efficient mechanism for selecting the optimum conversion paths to be coupled in the power conversion module.

In an exemplary implementation of the power converter, the controller is configured to receive information indicating a light load condition and to control the coupling based on the coupling scheme only when the light load condition is indicated.

This provides the advantage that the disclosed method can be applied when a light load situation is detected and otherwise the power converter can switch to the normal conversion method, e.g., normal PWM operation.

In an exemplary implementation of the power converter, the controller is configured to disable an integration of respective voltages in each of the DC-link capacitors when the information indicating the light load condition is received.

This provides the advantage of stable and robust behavior. DC-link control implements only a proportional when working under light load conditions. The dc-link controller may provide a current or a power reference, depending on the implementation alternatives already covered in the prior art. The Integrator part may be disconnected to avoid negative power/current references that may push the UPFR to instability.

According to a second aspect, the disclosure relates to a method for providing a control signal to a power converter according to the first aspect, the method comprising: sorting DC-link halves, i.e., values of the DC voltages at the respective conversion paths associated to the respective DC link capacitor, according to their measured voltage by using a sorting algorithm, wherein lower voltages are assigned with higher priority than higher voltages; connecting capacitors of higher priority in an order according to their priority until the sum of their measured voltages is the one that minimizes a difference with the voltage reference; and defining the control signal for each leg of IGBT switches according to a look-up table, the look-up table determining for each SST state including AC voltage v_in and control signals d_top and d_bottom, the corresponding connected capacitors Ctop and Cpottom-

Such a method shows superior performance in light load situations or discontinuous conduction mode. By prioritizing the conversion paths with respect to the DC voltage value, the non-linearity can be better handled, and a robust performance and full controllability can be achieved which is not the case in standard PWM with phase interleaving.

In an exemplary implementation of the method, the lookup table is defined as follows: For a positive AC voltage v_in, the following differentiation applies: for d_top = 0 and dbottom = 0, Ctop is enabled and Cbottom is enabled; for d_top = 0 and dbottom = 1 , C_top is enabled and Cbottom is disabled; for d_top = 1 and dbottom = 0, C_top is disabled and Cbottom is enabled; for d_top = 1 and dbottom = 1 , C_top is disabled and Cbottom is disabled; and for a negative AC voltage v_in, the following differentiation applies: for d_top = 0 and dbottom = 0, C_top is enabled and Cbottom is enabled; for d_top = 0 and dbottom = 1 , C_top is disabled and Cbottom is enabled; for d_top = 1 and dbottom = 0, Ctop is enabled and Cbottom is disabled; for d_top = 1 and dbottom = 1 , C_top is disabled and Cbottom is disabled.

Such a lookup table provides a better controllability and prioritization of the different conversion paths resulting in superior performance in DCM and light load conditions.

According to a third aspect, the disclosure relates to a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the method according to the second aspect described above and below with respect to Figure 3.

The computer program product may run on a controller or a processor for controlling the above-described power converter, e.g., a controller according to the first aspect as described above.

According to a fourth aspect, the disclosure relates to a computer-readable medium, storing instructions that, when executed by a computer, cause the computer to execute the method according to the second aspect described above. Such a computer readable medium may be a non-transient readable storage medium. The instructions stored on the computer-readable medium may be executed by a controller or a processor for controlling the above-described power converter. BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the disclosure will be described with respect to the following figures, in which:

Figure 1 shows a block diagram of a power converter 100 in a multilevel modular configuration for power conversion between a DC power network 110 and an AC power network 120 according to the disclosure;

Figure 2 shows a block diagram of an individual power converter module 141 , i.e., SST cell of the power converter 100 shown in Figure 1 and a coupling scheme 170 for the power converter module 141 according to the disclosure;

Figure 3 shows a block diagram of a controller 300 implementing an exemplary voltage sorting modulation method according to the disclosure for the power converter modules 141 shown in Figures 1 and 2;

Figures 4a and 4b show performance diagrams of the DC voltage waveforms obtained from a simulation of the voltage sorting modulation method 300 shown in Figure 3, where Figure 4b shows a zoom view of the diagram of Figure 4a;

Figure 5 shows exemplary current waveforms for the simulation of the voltage sorting modulation method 300 under light load conditions; and

Figure 6 shows exemplary voltage waveforms for the simulation of the voltage sorting modulation method 300 under light load conditions.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims. It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

In this disclosure, Solid State Transformers (SST) technology and multilevel power converters are described. The Solid-State Transformer technology can be applied in datacenters and other applications, for example. SST technology may utilize multi-module multi-level topologies when interfacing medium voltage (MV) AC grids. Input Series Output Parallel (ISOP) topologies are a prevalent solution for a two-stage power conversion between a MV AC grid and a Low voltage (LV) de grid. For the second power conversion stage, at least one DC-DC converter per cell is needed. The DC-DC converter delivers power from the cell DC-link to the common LVDC grid (i.e., output parallel); to do so, the DC-DC topology should provide galvanic isolation. Series resonant converter (SRC) working in open loop (50% duty cycle) are a simple yet widely considered solution for the second power stage of ISOP SSTs.

Modular Multilevel Cascaded Converters are a prevalent solution to achieve the SST implementation. Modular Multilevel Cascaded Converters may be based on cascaded-H bridge (CHB) topology, for example. In such implementation, a four quadrant three-phase cascaded-H bridge (CHB) topology may be connected to the grid. The AC output voltage can be synthesized by the sum of modules in the same branch. This can be achieved by a proper operation of the power electronics switches (e.g., IGBTs or MOSFETs) that connect/disconnect the DC-links to the AC side via the turn on/off of the devices. For example, using a full-bridge inverter, the switching combinations for each module set the AC output voltages to be v_dc, 0 or -v_dc. The use of multiple modules has the following advantages: i) the power electronics switches are suited for a low voltage class, which in practice allows to use low voltage power electronics technologies in high/medium voltage applications; ii) the power quality of the AC output voltage waveform increases with the number of modules; more voltage levels implies less harmonics; iii) related to previous point, the output filter effort is reduced as the output harmonics are less and less significant. The advantages of multilevel converters are at the cost of increasing the complexity; both in terms of topology and control. Focusing on control, the main goal is to achieve a reliable and robust regulation of the DC-link voltages. The ISOP SST concept can be optimized for applications in which the power delivery is always in the same direction; more specifically, the SST is a power electronics-based load. In that scenario, the four- quadrant cells can be substituted by unity power factor PWM topologies.

Unity Power Factor Rectifiers (UPFR) can be used as building block for Cascade H-Bridge (CHB) based SST. Key features of the UPFR based approach are: a) Power conversion is constrained to work with power factor equal to 1 (assuming an ideal system without harmonics, only fundamental components, the AC current and the ac voltage are in- phase); b) Simple Layout and High power density is achieved (e.g., diodes are simpler than active devices); c) High frequency PWM operation: i) reduced size of magnetics and Cost effective; ii) High power quality: low Total Harmonic Distortion THD, in output current and voltage in the point of connection are achievable; d) Vector control and PWM techniques, similar to the ones employed in Four quadrants CHB, are suitable. Especially for data center applications, these features are of high interest.

The disclosed modulation method presented hereinafter is only dependent on the power consumption, but not on the DC-DC topology or control method. Hence, the disclosed modulation method can be applied in all of the topologies described above for controlling the power conversion.

Figure 1 shows a block diagram of a power converter 100 in a multilevel modular configuration for power conversion between a DC power network 110 and an AC power network 120 according to the disclosure.

The power converter 100 comprises a first phase branch 130, e.g., branch C as exemplarily detailed in Figure 1. The AC power network 120 can be a multi-phase power grid, e.g., a three-phase power grid as shown in Figure 1. For the other two branches 131 , 132 (Branch B and Branch C), the power converter 100 may be analogously designed.

The first phase branch 130 comprises a plurality of power conversion modules 141 , 142, 143, 144, also called SST cells, wherein the inputs (left-hand side) of the power conversion modules 141 , 142, 143, 144 are connected in series while the outputs (righthand side) of the power conversion modules 141 , 142, 143, 144 are connected in parallel, as can be seen from Figure 1. Each power conversion module 141 comprises at least one coupleable conversion path 242, 243, 244, as shown in Figure 2, for converting an AC voltage 146 into a DC voltage 145 of the power conversion module (141) or vice versa. Each power conversion module 141 comprises a controllable coupling network 147, as shown in Figure 2, configured to couple the at least one conversion path 242, 243, 244 into the power conversion module 141 or to decouple the at least one conversion path 242, 243, 244 from the power conversion module 141 in response to a control signal 311 , as shown in Figure 3.

The power converter 100 further comprises a controller 300, as shown in Figure 3, configured to generate the control signals 311 for controlling the coupling networks 147 of the plurality of power conversion modules 141 , 142, 143, 144 based on a coupling scheme 170, as shown in Figures 2 and 3 and described below with respect to Figures 2 and 3. The coupling scheme 170 prioritizes the conversion paths 242, 243, 244 of the plurality of power conversion modules 141 , 142, 143, 144 with respect to a value of the DC voltage 145, 145a, 145b at the respective conversion path 242, 243, 244.

A conversion path converting a DC voltage with a lower DC value can have a higher priority than a conversion path converting a DC voltage with a higher DC value.

Further details of the power conversion module 141 are described below with respect to Figure 2, and further details of the controller 300 and the coupling scheme 170 are described below with respect to Figure 3.

Figure 2 shows a block diagram of an individual power converter module 141 , i.e., SST cell of the power converter 100 shown in Figure 1 and a coupling scheme 170 for the power converter module 141 according to the disclosure.

Each power conversion module, as exemplarily shown for the power conversion module 141 shown in Figure 2, comprises: a first DC terminal 151 ; a second DC terminal 152; and a third DC terminal 153. A first conversion path 242 may be arranged between the first DC terminal 151 and the third DC terminal 153. A second conversion path 243 may be arranged between the third DC terminal 153 and the second DC terminal 152. A third conversion path 244 may be arranged between the first DC terminal 151 and the second DC terminal 152. The coupling network 147 may comprise: a first bidirectional switch 147a coupled between a first AC terminal 161 and the third DC terminal 153; and a second bidirectional switch 147b coupled between a second AC terminal 162 and the third DC terminal 153.

Each power conversion module 141 may comprise a first conversion path 242, a second conversion path 243 and a third conversion path 244. The first conversion path 242 may comprise a first DC-link capacitor 163. The second conversion path 243 may comprise a second DC-link capacitor 164. The third conversion path 244 may comprise a series connection of the first DC-link capacitor 163 and the second DC-link capacitor 164 as shown in Figure 2.

The first DC-link capacitor 163 may be coupled between the first DC terminal 151 and the third DC terminal 153. The second DC-link capacitor 164 may be coupled between the third DC terminal 153 and the second DC terminal 152.

Each power conversion module 141 may comprise: a first diode D1 coupled between the first AC terminal 161 and the first DC terminal 151 ; a second diode D2 coupled between the second AC terminal 162 and the first DC terminal 151 ; a third diode D3 coupled between the second DC terminal 152 and the first AC terminal 161 ; and a fourth diode D4 coupled between the second DC terminal 152 and the second AC terminal 162.

The power conversion module 141 may be configured to provide an AC current 148 (i_ph) which is in phase with the AC voltage 146 (y_in) of the power conversion module 141.

The controller 300 may be configured to determine the value of the DC voltage 145, 145a, 145b converted by the respective conversion path 142, 143, 144 based on a phase-angle measurement of the AC voltage 146, a DC-link voltage reference value 302, as shown in Figure 3, and respective voltages 303 (shown in Figure 3) in each of the DC-link capacitors 163, 164.

Further functionalities of the controller 300 are described below with respect to Figure 3.

The novel modulation technique described in this disclosure is particularly detailed for the embodiment of the AC/DC side 201 of the power converter module 141 , i.e., SST cell depicted in Figure 1. As illustrated in Figure 2, this cell 141 includes, D1 to D4 diodes, T1 to T4 bidirectional, fully controlled switches 147a (e.g., MOSFETS) and two half DC-links capacitors 142, 143 that form a whole DC-link. This particular topology permits to connect two different loads per half DC-link, so independent control per half DC-link (e.g., charging the top cap but not the bottom one) is included. The description of the embodiment herein is applicable to all the family of UPFR based cells with same operation principle, and of course, for any number of series connected cells, ranging from 1 to infinite.

A key idea to understand AC/DC conversion in this kind of system is that it works with unity power factor: the input voltage and current are in phase. As a consequence, input voltage phase-angle measurement immediately detects current zeros crosses. With this information available, it is possible to determine which DC-link capacitors are charging/not-charging: i.e., the same AC current flows through all the cells of the same branch, so setting duty cycles permits to charge or bypass the different DC-link capacitors. Every combination for the cell depicted on the left is reflected on the look-up table 170, also referred to as coupling scheme 170, on the right-side of Figure 2.

Figure 3 shows a block diagram of a controller 300 implementing an exemplary voltage sorting modulation method according to the disclosure for the power converter modules 141 shown in Figures 1 and 2.

The controller 300 is based on a novel voltage sorting modulation scheme 312 or algorithm as detailed in the block 320 shown at the bottom side of Figure 3. This voltage sorting modulation scheme 312 determines the control signals 311 for transmission to the hardware 130, i.e., the different branches of the power converter 100 shown in Figure 1.

The voltage sorting modulation scheme 312 receives a reference power per phase ph and module m as first input: P_p^_m 305, a reference voltage v_p ^r _t 308 per phase ph for a number of k phases, a number of k times n voltages 309 per phase ph and module m for the top DC links shown in block 320, and a number of k times n voltages 310 per phase ph and module m for the bottom DC links shown in block 320. For these input signals, the controller 300 determines the control signals 311 for transmission to the hardware 130.

The reference voltage v_p ^e _h ^f 308 per phase ph for the number of k phases are determined by a current control block 318 that performs current control based on a reference phase current i_p ^e _h ^f 307 and the phase current i_ph 305, e.g., applying PR control and Goodwin anti-windup. The reference phase current i 307 is determined by a current reference calculation block 317 using the phase voltage v_ph 308 phase-locked by a PLL 316, a reference value 306 for the total power reference pff 306 and the reference power P _m 305 per phase ph and module m.

Both reference power values pff 306 and P _m 305 are determined by a DC Squared Control block 315 implementing PI control and Goodwin anti-windup. This DC Squared Control block 315 evaluates DC voltage reference vff 302, DC phase voltages v_{dc ph m} 303, power sharing 314 and light load condition 301. Under light load condition 301 , integral control and anti-windup of this block 315 can be inactive.

That means, DC-link control 315 implements only a proportional control (P) when working under light load conditions 301. The DC-link controller 315 may provide a current or a power reference, depending on the implementation alternatives. The Integrator part (I) may be disconnected to avoid negative power/current references that may push the UPFR to instability.

The controller 300 may be configured to sort 327 the voltages of the first and second conversion paths 242, 243 of the plurality of power conversion modules 141 , 142, 143, 144 assigning a priority 325, 326 to the first and second conversion paths 242, 243.

The controller 300 may be configured to add the DC voltages 304 converted by the sorted conversion paths 242, 243 and to compare the added DC voltages 332 against an AC voltage reference value 308.

The controller 300 may be configured to determine a subset 331 of the sorted conversion paths 242, 243 which added DC voltages 332 have a minimum difference 329 to the AC voltage reference value 308.

The controller 300 may be configured to couple the conversion paths 242, 243, 244 from the subset 331 of conversion paths into the power conversion module and to decouple the remaining conversion paths from the power conversion module using the coupling scheme 170 to determine the control signals 311 . The controller 300 may be configured to receive information indicating a light load condition 301 and to control the coupling based on the coupling scheme only when the light load condition 301 is indicated.

The controller 300 may be configured to disable an integration 315 of respective voltages 303 in each of the DC-link capacitors 163, 164 when the information indicating the light load condition 301 is received.

Thus, Figure 3 illustrates an exemplary embodiment of the whole control structure (of controller 300) that makes use of this fact to implement a sorting-based modulation method as illustrated in block 320.

This sorting-based modulation method 312 as illustrated in the block 320 provides the two main functionalities, described in the following:

1) DC-link control implements only a proportional (control) when working under light load conditions indicated by 301. The DC-link controller 315 may provide a current or a power reference, depending on the existing implementation alternatives. The Integrator part (I) may be disconnected to avoid negative power/current references that may push the UPFR to instability.

2) The DC link voltage ascending order sorting modulation algorithm 320 is shown in Figure 3. The input of the block 320 is the output voltage reference v_ph ^ref 308 from the current control loop 318. Then, this voltage reference 308 is made physical by a connection of the set of less-charged dc-link voltages 331 in the whole branch that better match v_Ph^ref 308. In other words, the series combination of less charged dc-links 331 (series combination implies they add-up to a total output voltage) that provide an output voltage the closest to the given reference v_ph ^ref 308. It understands that this method can be extended to cover trivial/slight modifications to this criterion, such as approximation from top (always above ref) or bottom (always below ref).

This novel way of defining the control signals 311 can be achieved with these steps:

1) Every sampling cycle, DC-link halves 321 , 322, 323, 324 are sorted according to their measured voltage by using a sorting algorithm 327, e.g., such as bubble sort, etc. This method works with any of the typical sorting algorithms, which must be selected according to hardware specifications, number of levels being the most important one. 2) Lower voltages are assigned with higher priority to be connected to the input.

3) These capacitors of higher priority 331 are connected in an order according to their priority until the sum of their measured voltages is the one that minimizes the difference 329 with the voltage reference 308 (including/not including an always top/bottom criterion).

4) The control signal for each leg of IGBT switches is defined 330 using the look-up table 170, as exemplarily shown on the left side of Figure 3.

This look-up table 170 determines for each SST state including AC voltage v_in 146 and control signals d_top 171 and d_bottom 172, the corresponding connected capacitors C_top 163 and Cbottom 164.

For a positive AC voltage v_in 146, the following differentiation applies: For d_top = 0 and dbottom = 0, C_top is enabled and C_bottom is enabled. For d_top = 0 and dbottom = 1 , C_top is enabled and Cbottom is disabled. For d_top = 1 and dbottom = 0, C_top is disabled and Cbottom is enabled. For d_top = 1 and dbottom = 1 , C_top is disabled and Cbottom is disabled.

For a negative AC voltage v_in 146, the following differentiation applies: For d_top = 0 and dbottom = 0, C_to_P is enabled and Cbottom is enabled. For d_top = 0 and dbottom = 1, C_top is disabled and Cbottom is enabled. For d_top = 1 and dbottom = 0, C_top is enabled and Cbottom is disabled. For d_top = 1 and dbottom = 1 , C_top is disabled and Cbottom is disabled.

Figures 4a and 4b show performance diagrams of the DC voltage waveforms obtained from a simulation of the voltage sorting modulation method 300 shown in Figure 3, where Figure 4b shows a zoom view of the diagram of Figure 4a.

The simulation results shown in Figures 4a and 4b are for a 3-phase 7 cells SST. A PLECS simulation software was used. The simulations were performed using randomly generated values for the components to account for tolerances.

Key variables are set as follows: DC Link voltage references is 1500 V, grid voltage is 4000 V and light load conditions are 20 W for the top module of each phase and 10 W for the remaining ones. In the results shown in Figures 4a, 4b, 5 and 6, DC-links start at 0 V and control is enabled at 0.25 seconds. The resulting DC link voltage waveform is shown in Figure 4a while Figure 4b shows a zoom view of Figure 4a. After the initial transient 401 , the disclosed modulation method successfully stabilizes all of the DC links at the voltage reference value. The transient 402 and steady-state 403 performance is zoomed in Figure 4b.

Figure 5 shows exemplary current waveforms for the simulation of the voltage sorting modulation method 300 under light load conditions.

As a consequence of light load conditions, SST works under discontinuous conduction mode (DCM). Thus, as explained before, AC current waveforms have a high THDi. These current waveforms are given by light load conditions. In this way, it is proved that a poor THDi does not hamper the ability of the disclosed voltage sorting modulation method 300 to accurately follow the voltage reference. Current waveforms 501 , 502, 503 are shown in Figure 5.

The performance of the modulation method can also be evaluated regarding its effects in the shape of the voltage waveform. Figure 6 shows the evolution of the DC link capacitors’ voltage when they are charging. It is clear in this image that the capacitors with lower voltages are the ones getting connected to the input. Note: the graph uses sampled values, which causes the stair-like appearance of the plot but helps in highlighting the evolution of the voltage between samples.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other. Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1 . A power converter (100) for power conversion between a DC power network (110) and an AC power network (120), the power converter comprising a first phase branch (130), the first phase branch (130) comprising a plurality of power conversion modules (141 , 142, 143, 144) connected in series, wherein each power conversion module (141) comprises: at least one coupleable conversion path (242, 243, 244) for converting a DC voltage (145) into an AC voltage (146) of the power conversion module (141) or for converting an AC voltage (146) into an DC voltage (145) of the power conversion module (141); and a controllable coupling network (147) configured to couple the at least one conversion path (242, 243, 244) into the power conversion module (141) or to decouple the at least one conversion path (242, 243, 244) from the power conversion module (141) in response to a control signal (311), wherein the power converter (100) further comprises: a controller (300) configured to generate the control signals (311) for controlling the coupling networks (147) of the plurality of power conversion modules (141 , 142, 143, 144) based on a coupling scheme (170), wherein the coupling scheme (170) prioritizes the conversion paths (242, 243, 244) of the plurality of power conversion modules (141 , 142, 143, 144) with respect to a value of the DC voltage (145, 145a, 145b) at the respective conversion path (242, 243, 244).

2. The power converter (100) of claim 1 , wherein a conversion path converting a DC voltage with a lower DC value has a higher priority than a conversion path converting a DC voltage with a higher DC value.

3. The power converter (100) of claim 1 or 2, each power conversion module (141) comprising: a first DC terminal (151); a second DC terminal (152); and a third DC terminal (153), wherein a first conversion path (242) is arranged between the first DC terminal (151) and the third DC terminal (153), wherein a second conversion path (243) is arranged between the third DC terminal (153) and the second DC terminal (152), wherein a third conversion path (244) is arranged between the first DC terminal (151) and the second DC terminal (152).

4. The power converter (100) of claim 3, wherein the coupling network (147) comprises: a first bidirectional switch (147a) coupled between a first AC terminal (161) and the third DC terminal (153); and a second bidirectional switch (147b) coupled between a second AC terminal (162) and the third DC terminal (153).

5. The power converter (100) of claim 4, wherein each power conversion module (141) comprises a first conversion path (242), a second conversion path (243) and a third conversion path (244), the first conversion path (242) comprising a first DC-link capacitor (163), the second conversion path (243) comprising a second DC-link capacitor (164), and the third conversion path (244) comprising a series connection of the first DC-link capacitor (163) and the second DC-link capacitor (164).

6. The power converter (100) of claim 5, wherein the first DC-link capacitor (163) is coupled between the first DC terminal (151) and the third DC terminal (153); and wherein the second DC-link capacitor (164) is coupled between the third DC terminal (153) and the second DC terminal (152).

7. The power converter (100) of claim 6, wherein each power conversion module (141) comprises: a first diode (D1) coupled between the first AC terminal (161) and the first DC terminal (151); a second diode (D2) coupled between the second AC terminal (162) and the first DC terminal (151); a third diode (D3) coupled between the second DC terminal (152) and the first AC terminal (161); and a fourth diode (D4) coupled between the second DC terminal (152) and the second AC terminal (162).

8. The power converter (100) of any of the preceding claims, wherein the power conversion module (141) is configured to provide an AC current (148) which is in phase with the AC voltage (146) of the power conversion module (141).

9. The power converter (100) of any of the preceding claims, wherein the controller (300) is configured to determine the value of the DC voltage (145, 145a, 145b) converted by the respective conversion path (142, 143, 144) based on a phase-angle measurement of the AC voltage (146), a DC-link voltage reference value (302) and respective voltages (303) in each of the DC-link capacitors (163, 164).

10. The power converter (100) of any of claims 5 to 7, wherein the controller (300) is configured to sort (327) the voltages of the first and second conversion paths (242, 243) of the plurality of power conversion modules (141 , 142, 143, 144) assigning a priority (325, 326) to the first and second conversion paths (242, 243).

11 . The power converter (100) of claim 10, wherein the controller (300) is configured to add the DC voltages (304) converted by the sorted conversion paths (242, 243) and to compare the added DC voltages (332) against an AC voltage reference value (308).

12. The power converter (100) of claim 11 , wherein the controller (300) is configured to determine a subset (331) of the sorted conversion paths (242, 243) which added DC voltages (332) have a minimum difference (329) to the AC voltage reference value (308).

13. The power converter (100) of claim 12, wherein the controller (300) is configured to couple the conversion paths (242, 243, 244) from the subset (331) of conversion paths into the power conversion module and to decouple the remaining conversion paths from the power conversion module using the coupling scheme (170) to determine the control signals (311).

14. The power converter (100) of any of the preceding claims, wherein the controller (300) is configured to receive information indicating a light load condition (301) and to control the coupling based on the coupling scheme only when the light load condition (301) is indicated.

15. The power converter (100) of claim 14, wherein the controller (300) is configured to disable an integration (315) of respective voltages (303) in each of the DC-link capacitors (163, 164) when the information indicating the light load condition (301) is received.