KR20190133435A - Apparatus for dc link voltage imbalance compensation - Google Patents

Abstract

The present invention relates to a direct current (DC) link voltage imbalance compensation device. The DC link voltage imbalance compensation device comprises: a converter connected with an alternating current (AC) power source; an inverter unit connected with the converter; a DC link including first and second capacitors formed between the converter and the inverter unit and connected in series to each other; and a balance controller receiving the first voltage which is formed between a first node formed in the first capacitor and a second node formed between the first and second capacitors, and the second voltage formed between the second node and a third node formed in the second capacitor so as to compensate an imbalance of the capacitor voltage formed in the DC link. Therefore, it is possible to solve a DC link voltage imbalance phenomenon generated in a three-level converter system.

Description

DC link voltage unbalance compensation device {APPARATUS FOR DC LINK VOLTAGE IMBALANCE COMPENSATION}

The present invention relates to an unbalance compensation technique of a DC link voltage, and more particularly, a DC link voltage that effectively controls a voltage unbalance of a direct current (DC) link capacitor of a three-level converter by controlling a neutral current change without additional hardware. An unbalance compensation device.

In modern society, the development of economy, education and industry has increased the demand for skyscrapers and apartments along with the urban concentration of the population. The elevator, which is a transportation facility in a high-rise building, has been developed to meet the needs of eco-friendly energy sources and efficient power conversion systems that are not dependent on fossil fuels, as well as to improve ride comfort, save energy, and save space. It is going on.

AC / DC power converters used to convert large amounts of AC power to DC power generally use three-phase diode currents and AC / DC PWM power converters. The existing high power / high voltage elevator system mainly uses a two-level back-to-back structure in which the inverter and the converter are connected in series to improve the characteristics of the inverter output voltage and to ensure responsiveness according to load torque changes. In this case, two levels of PWM voltage are output to the inverter output voltage. Compared to multilevel converters, the switch has a higher breakdown voltage, distorts output voltage and current, exhibits low THD performance, and requires the attachment of a sine wave filter attached to an LC and electromagnetic issues.

Multi-level converters in high-capacity systems have the advantages of lower voltages on switches, lower dv / dt, and smaller reactor sizes and wires compared to two-level converters, making them an alternative to systems using two-level converters. . In addition, high power can be obtained using a medium voltage semiconductor device, and as the output voltage level increases, the magnitude of dv / dt and surge voltage generated during switching decreases, thereby solving the problem of stator winding insulation breakdown and bearing breakdown when the motor starts. As the number of levels increases, good output harmonic characteristics can be obtained at the minimum switching frequency, and the EMI problem during switching can be improved.

However, there is a problem of voltage unbalance of the DC-link due to the current flowing through the neutral point, and when the voltage is concentrated on one capacitor, the voltage applied to one switching element increases, and the stress of the element increases and, in the worst case, breaks down. Can be. In addition, the THD of the output current may increase, making the system unstable.

Korean Patent Registration No. 10-0153815 (1998.07.07) relates to a single-phase load unbalance partial compensation device for alleviating voltage unbalance caused by unbalanced current flowing in large single-phase loads. When a large unbalanced load is applied to a three-phase system by connecting a single-phase load between them, compensating reactive power between ab phases is used to alleviate voltage inequality, which is unbalanced compared to conventional three-phase unbalance compensation devices. Uncompensated device to be installed in substation supplying electric railway load and single phase arc because the effect is excellent when compensating part of load, the main circuit is simple, there is little risk like series resonance, and installation space can be reduced. It can be applied to the back.

Korean Patent Registration No. 10-0435503 (2004.06.01) relates to an unbalanced power compensation and instantaneous low voltage compensation control device. According to the present invention, the present invention measures the power supply voltage every minute and monitors for abnormality. When detected, the electrostatic source voltage is separated into normal and reverse phases, respectively, and then controlled through a normal voltage synchronous coordinate controller and a reverse phase voltage synchronous coordinate controller. In addition, a current controller is used internally to obtain overcurrent protection and fast voltage response of the three-phase inverter 10. An internal current controller controls the current in the inductor. The output from the current controller turns the three-phase inverter on and off. By doing so, when an unbalanced voltage is generated, not only fast voltage compensation but also an unbalance of each phase can be eliminated.

Korean Patent Registration No. 10-0153815 (1998.07.07) Korea Patent Registration No. 10-0435503 (2004.06.01)

An embodiment of the present invention is to provide a DC (Direct Current) link voltage unbalance compensation device that efficiently controls the voltage unbalance of the DC link capacitor of the three-level converter without additional hardware.

One embodiment of the present invention is to provide a DC link voltage unbalance compensation device that improves the DC link voltage unbalance by controlling the image current flowing through the neutral point without using complicated calculations.

An embodiment of the present invention is to provide a DC link voltage unbalance compensation device that performs a closed loop control with a gain value according to the unbalance of the DC link capacitor voltage and follows the neutral current change to compensate for the unbalance of the DC link capacitor voltage.

Among the embodiments, a direct current (DC) link voltage unbalance compensation device includes a converter connected to an AC power source, an inverter connected to the converter, and a DC including first and second capacitors formed in series between the converter and the inverter. A first voltage formed between a link and a first node formed in the first capacitor and a second node formed between the first and second capacitors and a second formed between the second node and a third node formed in the second capacitor And a balance controller that receives the voltage and compensates for the unbalance of the capacitor voltage formed on the DC link.

The converter may correspond to a three-level I-type converter.

The balance controller may further include a voltage control module configured to control a third voltage by adding the first and second voltages to calculate a neutral point current change.

The balance controller may compensate for the unbalance of the DC link capacitor voltage by performing closed loop control with a gain value according to the unbalance of the DC link capacitor voltage and following a change in the neutral point current of the second node.

The balance controller may include a gain calculator configured to control the addition or subtraction of a target neutral point voltage and an actual neutral point voltage, and correct the error through PI control to calculate the gain value, using the power value of the converter based on the gain value. A neutral point current change calculation unit calculating a neutral point current change of two nodes, and a neutral point voltage output unit configured to control neutralization of the neutral point current change and the actual neutral point current, and output a neutral point voltage by correcting an error through PI control.

The neutral point current change calculator can calculate the neutral point current change through Equation 4 below.

[Equation 4]

The disclosed technique can have the following effects. However, since a specific embodiment does not mean to include all of the following effects or only the following effects, it should not be understood that the scope of the disclosed technology is limited by this.

Direct current (DC) link voltage unbalance compensation device according to an embodiment of the present invention is simple and easy to implement by controlling the image current flowing in the neutral point is economical and efficient.

The DC link voltage unbalance compensation device according to an embodiment of the present invention can compensate for the unbalance of the DC link capacitor voltage by performing closed-loop control with a gain value according to the unbalance of the DC link capacitor voltage and following the change of the neutral point current.

DC link voltage unbalance compensation device according to an embodiment of the present invention can be applied to a wide range of elevator control systems, ships and heavy industries, regardless of the type of motor, such as a permanent magnet synchronous motor and induction motor.

1 is a view for explaining a DC link voltage unbalance compensation device according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a balance controller of the DC link voltage unbalance compensation device of FIG. 1.
3 is a DC link equivalent circuit diagram of the DC link voltage unbalance compensation device of FIG. 1.
4 is a flowchart illustrating a control process of a balance controller of the DC link voltage unbalance compensation device of FIG. 1.

Description of the present invention is only an embodiment for structural or functional description, the scope of the present invention should not be construed as limited by the embodiments described in the text. That is, since the embodiments may be variously modified and may have various forms, the scope of the present invention should be understood to include equivalents capable of realizing the technical idea. In addition, the objects or effects presented in the present invention does not mean that a specific embodiment should include all or only such effects, the scope of the present invention should not be understood as being limited thereby.

On the other hand, the meaning of the terms described in the present application should be understood as follows.

Terms such as "first" and "second" are intended to distinguish one component from another component, and the scope of rights should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is referred to as being "connected" to another component, it should be understood that there may be other components in between, although it may be directly connected to the other component. On the other hand, when a component is referred to as being "directly connected" to another component, it should be understood that there is no other component in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "comprise" or "have" refer to a feature, number, step, operation, component, part, or feature thereof. It is to be understood that the combination is intended to be present and does not exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

In each step, an identification code (e.g., a, b, c, etc.) is used for convenience of description, and the identification code does not describe the order of the steps, and each step clearly indicates a specific order in context. Unless stated otherwise, they may occur out of the order noted. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

The present invention can be embodied as computer readable code on a computer readable recording medium, and the computer readable recording medium includes all kinds of recording devices in which data can be read by a computer system. . Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. Generally, the terms defined in the dictionary used are to be interpreted to coincide with the meanings in the context of the related art, and should not be interpreted as having ideal or excessively formal meanings unless clearly defined in the present application.

1 is a view illustrating a direct current (DC) link voltage unbalance compensation device according to an embodiment of the present invention.

Referring to FIG. 1, the DC link voltage unbalance compensation device 100 includes a converter 110, an inverter unit 120, a DC link 130, and a balance controller 140.

The converter 110 generally refers to a device for converting between alternating current and direct current, frequency interconversion of alternating current, conversion of constants, and the like. In more detail, it may correspond to an apparatus for converting alternating current into direct current. In one embodiment, the converter 110 of the DC link voltage unbalance compensation device 100 may correspond to a pulse width modulation (PWM) converter. Here, the PWM converter refers to a power converter that converts AC into direct current by pulse width modulation control. In one embodiment, converter 110 may correspond to a multilevel converter. More specifically, the converter 110 may correspond to a diode-clamped multilevel converter, a flying capacitor multilevel converter, or an H-Bridge multilevel converter. For example, the converter 110 may correspond to a diode-clamped multilevel converter and the diode-clamped multilevel converter has a T type and an I type, and the converter 110 is an I type diode-clamped multilevel converter. It can be implemented as. In addition, the converter 110 may be implemented as a three-level converter because it is inefficient due to the complexity of the voltage balancing algorithm in the case of a converter of three or more levels. As a result, the converter 110 of the DC link voltage unbalance compensation device 100 may be implemented as a three-level I-type Diode-Clamped converter as a PWM converter.

The inverter unit 120 is configured to include an inverter. An inverter is a kind of power converter, and means a device that converts DC power into AC power. In an embodiment, the inverter unit 120 may be connected to the converter 110 to convert DC power received through the converter 110 into AC power and transmit the same to an electric motor (for example, a permanent magnet synchronous motor (PMSM)). have.

The DC link 130 includes first and second capacitors 132 and 134 formed between the converter 110 and the inverter unit 120 and connected in series. Here, the DC link may refer to a DC circuit connecting the converter 110 and the inverter unit 120. More specifically, the DC link 130 may correspond to a connection between the circuit including the converter 110 and the inverter unit 120 including the inverter and may include a DC link capacitor. Here, the first and second capacitors 132 and 134 correspond to DC link capacitors and are connected in parallel between the positive electrode and the negative electrode so that the transient current on the load side does not return to the distributor side (not shown) and is rectified. It can serve to soften the direct current pulse. The DC link voltage means a voltage of a DC circuit corresponding to the DC link. In one embodiment, the unbalance of the DC link voltage may correspond to an unbalance of the voltage across the DC link capacitor, which may mean an unbalance of the DC link capacitor voltage and the unbalance of the DC link capacitor voltage is soon the first and second capacitors. It may refer to the voltage unbalance of the neutral point formed between the (132, 134).

The balance controller 140 may include a first voltage and a second node and a second capacitor formed between the first node formed in the first capacitor 132 and the second node formed between the first and second capacitors 132 and 134. The second voltage formed between the third nodes formed at 134 may be received. Here, the second node may correspond to a neutral point formed between the first capacitor 132 and the second capacitor 134. In one embodiment, the balance controller 140 may receive the first and second voltages to compensate for the unbalance of the DC link 130 capacitor voltages.

In one embodiment, the balance controller 140 may further include a DC voltage controller for controlling the third voltage by the sum of the first and second voltages to calculate the neutral point current change. Here, the third voltage may correspond to the total voltages of the first and second capacitors 132 and 134.

The balance controller 140 may compensate for the unbalance of the DC link capacitor voltage by performing closed-loop control with a gain value according to the unbalance of the DC link capacitor voltage and following the change of the neutral point current. When the neutral current flows through the second node corresponding to the neutral point of the DC link, an unbalance of the DC link voltage occurs. In one embodiment, the balance controller 140 may compensate for the unbalance of the DC link capacitor voltage by following the neutral current change of the second node. More specifically, the balance controller 140 performs closed loop control with a gain value generated according to an unbalance of the DC link capacitor voltage. Here, the closed loop control is a system in which the output signal is directly affected by the control operation, and transmits an error control operation signal, which is a difference between the input signal and the feedback signal, to reduce the error and reach the final output value. In one embodiment, the balance controller 140 may perform a closed loop control so that the actual neutral voltage reaches the target neutral voltage by correcting the error by receiving feedback of the neutral voltage output to the actual neutral voltage. Here, the actual neutral point voltage may correspond to the difference between the first voltage of the first capacitor and the second voltage of the second capacitor, and the target neutral point voltage may correspond to a target value of the difference between the first voltage and the second voltage. .

FIG. 2 is a block diagram illustrating a balance controller of the DC link voltage unbalance compensation device of FIG. 1.

Referring to FIG. 2, the balance controller 140 includes a gain calculator 142, a neutral point current change calculator 144, and a neutral point voltage output unit 146.

)과 제1 및 제2 전압에 따른 실제 중성점 전압(

)의 가감을 제어할 수 있다. 여기에서, 목표 중성점 전압(

)은 DC 링크 커패시터에 해당하는 제1 및 제2 커패시터들(132, 134)사이의 제2 노드에서 발생하는 불평형에 따른 중성점 전압차의 목표 수치에 해당할 수 있다. 이득 산출부(142)는 목표 중성점 전압(

)의 수치를 0으로 결정할 수 있다. 일 실시예에서, 이득 산출부(142)는 제1 커패시터의 제1 전압에서 제2 커패시터의 제2 전압을 감하여, 중성점의 불평형에 따른 제1 및 제2 전압의 전압차에 해당하는 실제 중성점 전압(

)을 구할 수 있다. 일 실시예에서, 이득 산출부(142)는 목표 중성점 전압(

)에서 실제 중성점 전압(

)을 감하고 PI(Proportional Integral) 제어를 통해 오차를 보정하여 이득값(k)을 산출할 수 있다. 여기에서 PI 제어는 비례-적분 제어를 의미하는 피드백 제어에 해당한다.The gain calculator 142 may use a target neutral point voltage (

) And the actual neutral point voltage (according to the first and second voltages)

Can be controlled. Where the target neutral voltage (

) May correspond to a target value of the neutral point voltage difference due to an unbalance occurring at the second node between the first and second capacitors 132 and 134 corresponding to the DC link capacitor. The gain calculator 142 may use a target neutral point voltage (

) Can be determined as 0. In one embodiment, the gain calculator 142 subtracts the second voltage of the second capacitor from the first voltage of the first capacitor, so that the actual neutral point voltage corresponding to the voltage difference between the first and second voltages according to the unbalance of the neutral point. (

) Can be obtained. In an embodiment, the gain calculator 142 may use a target neutral voltage (

) Is the actual neutral voltage (

) And the gain can be corrected through the PI (Proportional Integral) control to calculate the gain value (k). Here, PI control corresponds to feedback control, which means proportional-integral control.

)를 산출할 수 있다. 일 실시예에서, 중성점 전류 변화(

)는 DC 링크 커패시터 전압을 변화시키고 중성점 전류 변화(

)는 아래의 수학식4를 통해 산출할 수 있다.The neutral point current change calculator 144 uses the power value p of the converter 110 based on the gain value k to change the neutral point current of the second node (

) Can be calculated. In one embodiment, the neutral current change (

) Changes the DC link capacitor voltage and changes the neutral current (

) Can be calculated through Equation 4 below.

[Equation 4]

는 제어주기Ts동안의 중성점 전류 변화를, Vdc는 커패시터들의 전체전압을, k는 이득값을, <p>Ts는 제어주기Ts동안의 컨버터의 전력값을, Vmax 및 Imax는 DC 링크 전압 불평형 보상 장치의 상전압 및 상전류의 최댓값을, Vmin 및 Imin은 상전압 및 상전류의 최솟값을, Vmid 및 Imid는 중성점 전압 및 중성점 전류를 의미한다.From here,

Is the change in neutral current during control period Ts, Vdc is the total voltage of the capacitors, k is the gain value, <p> Ts is the power value of the converter during control period Ts, and Vmax and Imax are DC link voltage unbalance compensation. The maximum value of the phase voltage and the phase current of the device, Vmin and Imin are the minimum values of the phase voltage and the phase current, and Vmid and Imid are the neutral point voltage and the neutral point current.

)와 실제 중성점 전류(

)의 가감을 제어하고 PI 제어를 통해 오차를 보정하여 제2 노드의 중성점 전압(

)을 출력할 수 있다. 일 실시예에서, 중성점 전압 출력부(146)는 출력된 중성점 전압(

)을 실제 중성점 전압(

)에 피드백 할 수 있고 밸런스 제어기(140)는 상기 피드백에 따른 결과가 목표 중성점 전압(

)에 도달하도록 폐루프 제어를 수행할 수 있다.The neutral point voltage output unit 146 is a neutral point current change (

) And the actual neutral point current (

), And correct the error through the PI control, so that the neutral voltage (

) Can be printed. In one embodiment, the neutral point voltage output unit 146 outputs the neutral point voltage (

) Is the actual neutral voltage (

), And the balance controller 140 may return a target neutral voltage (

Closed loop control can be performed to reach

3 is a DC link equivalent circuit diagram of the DC link voltage unbalance compensation device of FIG. 1.

)에 의해서 실제 중성점 전압(

)을 결정할 수 있다. 일 실시예에서, 커패시터를 통하는 전류는 _1과 _2 이며, 실제 중성점 전압(

)은 한 제어주기 _동안 노드 O 에서 아래의 수학식1 내지 3과 같이 변화할 수 있다. 여기에서, 실제 중성점 전압(

)은 제1 전압과 제2 전압의 차이에 해당할 수 있다.Referring to FIG. 3, the DC link voltage unbalance compensation device 100 may vary the neutral current (

By the actual neutral voltage (

) Can be determined. In one embodiment, the current through the capacitor is _1 and _2, and the actual neutral voltage (

) May change as shown in Equations 1 to 3 at node O during one control period _. Where the actual neutral voltage (

) May correspond to a difference between the first voltage and the second voltage.

 [Equation 1]

[Equation 2]

[Equation 3]

Where <idc1> Ts is the current flowing in the first capacitor during the Ts period, <idc2> Ts is the current flowing in the second capacitor during the Ts period, Cdc is the capacitance of the first and second capacitors, and <Vdc1> Ts is the first voltage during the Ts period, <Vdc2> Ts is the second voltage during the Ts period, Vdc is the total voltage of the capacitors, and <p> Ts is the power value of the connector during the period Ts, k Is the gain value.

4 is a flowchart illustrating a control process of a balance controller of the DC link voltage unbalance compensation device of FIG. 1.

Referring to FIG. 4, the balance controller 140 of the DC link voltage unbalance compensation device 100 according to an embodiment of the present invention adds or subtracts a target neutral voltage and an actual neutral voltage and corrects an error through PI control to compensate for an unbalance. The gain value k can be calculated (step S410).

)를 산출할 수 있다(단계 S420).The balance controller 140 adds a feedforward term using the power value p of the converter based on the gain value k to change the neutral point current (

) Can be calculated (step S420).

)를 추종하여 실제 중성점 전류(

)를 제어하여 중성점 전압을 출력할 수 있다(단계 S430). 보다 구체적으로, 밸런스 제어기(140)는 중성점 전류 변화(

)와 실제 중성점 전류(

)의 가감 및 PI 제어를 통한 오차보정을 통해 제2 노드의 중성점 전압(

)을 출력할 수 있다.The balance controller 140 changes the neutral point current (

) To follow the actual neutral current (

) And the neutral point voltage may be output (step S430). More specifically, the balance controller 140 changes the neutral current (

) And the actual neutral point current (

), And the error correction through PI control, the neutral point voltage of the second node (

) Can be printed.

)을 피드백하여 실제 중성점 전압(

)과 오차를 보정하고 목표 중성점 전압의 수치에 도달하도록 폐루프 제어를 수행할 수 있다(단계 S440).The balance controller 140 outputs an output neutral point voltage (

) To feed back the actual neutral voltage (

), The closed loop control may be performed to correct the error and to reach the target neutral voltage value (step S440).

Compared to the method of directly compensating the change of the neutral voltage by performing a complicated calculation considering a table of the space vector region for the compensation of the neutral voltage unbalance of the conventional three-level converter, the DC link voltage unbalance compensating apparatus 100 is a balance controller 140. The closed loop control is performed by the gain value resulting from the unbalance of the DC link 130 voltage to follow the change of the neutral current flowing through the neutral point, thereby improving the DC link voltage unbalance.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

100: DC link voltage unbalance compensation device
110: converter 120: inverter unit
130: DC link
132: first capacitor 134: second capacitor
140: balance controller 142: gain calculator
144: neutral current change calculation unit
146: neutral voltage output

Claims (6)

A converter connected to an AC power source;
An inverter unit connected to the converter;
A DC link formed between the converter and the inverter section and including first and second capacitors connected in series; And
A first voltage formed between the first node formed in the first capacitor and a second node formed between the first and second capacitors, and a second voltage formed between the second node and the third node formed in the second capacitor; And a balance controller that receives and compensates for the unbalance of the DC link capacitor voltage formed on the DC link.
The method of claim 1, wherein the converter
DC link voltage unbalance compensation device, characterized by a three-level I-type pulse width modulation (PWM) converter.
The balance controller of claim 1, wherein the balance controller
And a voltage control module for controlling a third voltage caused by the sum of the first and second voltages to calculate a change in the neutral point current.
The balance controller of claim 1, wherein the balance controller
Compensating for the unbalance of the DC link capacitor voltage by performing closed-loop control to achieve the actual neutral point voltage to the target neutral point voltage by using a gain value according to the unbalance of the DC link capacitor voltage and following the change of the neutral point current of the second node. DC link voltage unbalance compensation device, characterized in that.
The method of claim 4, wherein the balance controller
A gain calculator configured to control the ramping of the target neutral point voltage and the actual neutral point voltage according to the first and second voltages, and correct the error through PI control to calculate the gain value;
A neutral point current change calculator configured to calculate the neutral point current change of the second node based on the gain value of the converter; And
And a neutral point voltage output unit configured to control a change in the neutral point current and an actual neutral point current, and correct an error through PI control to output a neutral point voltage of the second node.
The balance controller of claim 5, wherein the balance controller is
DC link voltage unbalance compensation device, characterized in that for calculating the neutral current change through the equation (4).
[Equation 4]

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