EP4369394A1 - Leistungshalbleitergehäuse und verfahren zu seiner herstellung - Google Patents

Leistungshalbleitergehäuse und verfahren zu seiner herstellung Download PDF

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Publication number
EP4369394A1
EP4369394A1 EP22206519.5A EP22206519A EP4369394A1 EP 4369394 A1 EP4369394 A1 EP 4369394A1 EP 22206519 A EP22206519 A EP 22206519A EP 4369394 A1 EP4369394 A1 EP 4369394A1
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EP
European Patent Office
Prior art keywords
die pad
power semiconductor
die
semiconductor package
molded body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22206519.5A
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English (en)
French (fr)
Inventor
Marcus Boehm
Stefan Woetzel
Andreas Grassmann
Bernd Schmoelzer
Uwe Schindler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
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Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Priority to EP22206519.5A priority Critical patent/EP4369394A1/de
Priority to CN202311493520.6A priority patent/CN118016625A/zh
Priority to US18/388,559 priority patent/US20240162205A1/en
Publication of EP4369394A1 publication Critical patent/EP4369394A1/de
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40257—Connecting the strap to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode

Definitions

  • This disclosure relates in general to a power semiconductor package as well as to a method for fabricating such a power semiconductor package.
  • Power semiconductor packages may comprise components which during operation have greatly differing electrical potentials. It may be desirable to electrically isolate components with a high potential from external parts like e.g. a heatsink. On the other hand, a power semiconductor package may generate a considerable amount of heat during operation. It may therefore be desirable to provide a heat dissipation pathway with as low a thermal resistance as possible. Electrically isolating components however have an increased thermal resistance compared to conductive components. Furthermore, elaborate isolation concepts may increase the costs of power semiconductor packages. Improved power semiconductor packages as well as improved methods for fabricating a power semiconductor package may help with solving these and other problems.
  • a power semiconductor package comprising: a leadframe comprising a first die pad, a second die pad and a plurality of external contacts, wherein the first and second die pads are separated by a first gap, a power semiconductor die arranged on and electrically coupled to a first side of the first die pad, a diode arranged on and electrically coupled to a first side of the second die pad, and a molded body encapsulating the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides, wherein a second side of the first die pad opposite the first side of the first die pad is exposed from the second side of the molded body and wherein a second side of the second die pad opposite the first side of the second die pad is completely covered by an electrically insulating material.
  • Various aspects pertain to a method for fabricating a power semiconductor package, the method comprising: providing a leadframe which comprises a first die pad, a second die pad and a plurality of external contacts, wherein the first and second die pads are separated by a first gap, arranging a power semiconductor die on a first side of the first die pad and electrically coupling the power semiconductor die to the first side of the first die pad, arranging a diode on a first side of the second die pad and electrically coupling the diode to the first side of the second die pad, encapsulating the power semiconductor die and the diode with a molded body, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides, such that a second side of the first die pad opposite the first side of the first die pad is exposed from the second side of the molded body, and completely covering a second side of the second die pad opposite the first side of the second die pad with an electrically insulating material.
  • the examples of a power semiconductor package described below may use various types of semiconductor dies or circuits incorporated in the semiconductor dies, among them AC/DC or DC/DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, analogue integrated circuits, mixed signal integrated circuits, sensor circuits, power integrated circuits, etc.
  • AC/DC or DC/DC converter circuits power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, analogue integrated circuits, mixed signal integrated circuits, sensor circuits, power integrated circuits, etc.
  • the examples may also use semiconductor dies comprising MOS transistor structures or vertical transistor structures like, for example, IGBT (Insulated Gate Bipolar Transistor) structures or, in general, transistor structures in which at least one electrical contact pad is arranged on a first main face of the semiconductor die and at least one other electrical contact pad is arranged on a second main face of the semiconductor die, opposite to the first main face of the semiconductor die.
  • MOS transistor structures or vertical transistor structures like, for example, IGBT (Insulated Gate Bipolar Transistor) structures or, in general, transistor structures in which at least one electrical contact pad is arranged on a first main face of the semiconductor die and at least one other electrical contact pad is arranged on a second main face of the semiconductor die, opposite to the first main face of the semiconductor die.
  • IGBT Insulated Gate Bipolar Transistor
  • An efficient power semiconductor package as well as an efficient method for fabricating a power semiconductor package may for example reduce material consumption, ohmic losses, chemical waste, etc. and may thus enable energy and/or resource savings.
  • Improved power semiconductor packages and improved methods for fabricating a power semiconductor package, as specified in this description may thus at least indirectly contribute to green technology solutions, i.e. climate-friendly solutions providing a mitigation of energy and/or resource use.
  • Figures 1A and 1B show a power semiconductor package 100 comprising a leadframe with a first die pad 110, a second die pad 120 and a plurality of external contacts 130.
  • the power semiconductor package 100 further comprises a power semiconductor die 140, a diode 150 and a molded body 160.
  • Fig. 1A shows a plan view of the power semiconductor package 100 (the molded body 160 is transparent in order to show the interior of the package) and
  • Fig. 1B shows a sectional view along the line B-B' in Fig. 1A .
  • the power semiconductor package 100 may be configured to operate with a high voltage and/or a strong electrical current.
  • the power semiconductor package 100 may for example be configured to operate with a voltage of about 650V or more, or 1.2kV or more.
  • the power semiconductor package 100 may comprise any suitable electrical circuit and may be used in any suitable application.
  • the power semiconductor package 100 may for example be part of a power factor correction (PFC) circuit.
  • the power semiconductor package 100 may for example be used in a solar inverter application.
  • PFC power factor correction
  • the first die pad 110, the second die pad 120 and the external contacts 130 may in particular be part of the same leadframe. However, it is also possible that one or more of these components are part of a different leadframe.
  • the leadframe or the leadframes may comprise or consist of any suitable metal or metal alloy.
  • the leadframe(s) may e.g. comprise or consist of Al, Cu or Fe.
  • the leadframe(s) may be plated. The plating may e.g. comprise or consist of Au, Ti, W or Ni.
  • the first die pad 110 may be configured to act as a carrier for a first semiconductor die, e.g. the power semiconductor die 140, and the second die pad 120 may be configured to act as a carrier for a second semiconductor die, e.g. the diode 150. It is however also possible that the first die pad 110 and/or the second die pad 120 are configured to act as a carrier for more than one semiconductor die.
  • the first die pad 110 may comprise a first side 111 and an opposing second side 112.
  • the second die pad 120 may comprise a first side 121 and an opposing second side 122.
  • the first die pad 110 may have any suitable thickness, the thickness being measured between the first and second sides 111, 112.
  • the first die pad 110 may for example have a thickness in the range of about 0.5mm to about 5mm. The lower limit of this range may also be about 0.7mm, about 1mm, or about 2mm and the upper limit may also be about 4mm or about 3mm.
  • the second die pad 120 may have a thickness which is smaller than the thickness of the first die pad 110.
  • the second die pad 120 may e.g. have a thickness which is about 0.1mm, or about 0.2mm, or about 0.3mm, or about 0.5mm smaller than the thickness of the first die pad 110.
  • fabricating the second die pad 120 comprises applying a thinning process to the die pad.
  • the thinning process may e.g. comprise one or more of rolling, milling and stamping the die pad in order to obtain a reduced thickness compared to the thickness of the first die pad 110.
  • the second side 112 of the first die pad 110 may be arranged in a first plane (plane A in Fig. 1B ) and the second side 122 of the second die pad 120 is arranged in a different second plane (plane B in Fig. 1B ).
  • the distance between the planes A and B corresponds to the difference in thickness between the first and second die pads 110, 120.
  • Tuning of the distance between planes A and B may require a trade-off decision between the insulation quality and material choice of the mold compound on the one hand (thicker gaps allow better insulation and usage of mold compounds with larger (cheaper) filler particles) and the thermal package performance on the other hand (thinner gaps provide better cooling paths to the heatsink 310) .
  • the first sides 111, 121 of the first and second die pads 110, 120 may be arranged coplanar in a third plane (plane C). It is however also possible that the first sides 111, 121 are not coplanar.
  • the first and second die pads 110, 120 are separated by a first gap 170. This may in particular mean that the first and second die pads 110, 120 are not in direct physical contact with one another. Furthermore, this may mean that the first and second die pads 110, 120 are not in direct electrical contact with one another. In other words, the first gap 170 may physically and electrically separate the first and second die pads 110, 120 from one another.
  • the power semiconductor die 140 and the diode 150 and/or the first and second die pads 110, 120 may be electrically coupled to one another via electrical connectors like bond wires, ribbons or contact clips (not shown in Figs. 1A and 1B ).
  • the first gap 170 may have any suitable width (the width being the distance between the die pads 110, 120).
  • the width of the first gap 170 may be 0.2mm or more, or 0.4mm or more, or 0.6mm or more, or 0.8mm or more, or 1mm or more, or 1.5mm or more, or 3mm or more, or 5mm or more, or 10mm or more.
  • the first gap 170 is filled with electrically insulating material.
  • the first gap 170 may for example be filled with mold material of the molded body 160. It is however also possible that a different material than the mold material of the molded body 160 partially or completely fills the first gap 170.
  • a dielectric connector piece may be arranged in the first gap 170, wherein the connector piece is configured to mechanically couple the first and second die pads 110, 120 (e.g. during fabrication of the power semiconductor package 100).
  • the power semiconductor die 140 is arranged on and electrically coupled to the first side 111 of the first die pad 110.
  • the diode 150 is arranged on and electrically coupled to the first side 121 of the second die pad 120.
  • the power semiconductor die 140 may for example be a MOSFET or an IGBT or HEMT (high electron mobility transistor).
  • the power semiconductor die 140 may e.g. be mounted on the first die carrier 110 in a flip chip configuration, in particular a "source-down" configuration.
  • the power semiconductor die 140 and the diode 150 may be coupled to the first and second die pads 110, 120 via "standard” soldered joints or diffusion soldered joints or sintered joints. According to an example, no semiconductor dies are arranged over the second sides 112, 122 of the die pads 110, 120.
  • the power semiconductor die 140 is mounted on the first die pad 110 in a "source down" configuration, wherein a source electrode faces the first side 111 of the first die pad 110.
  • a drain electrode may be arranged on the upper side of the power semiconductor die 140 and may face away from the first die pad 110.
  • the molded body 160 encapsulates the power semiconductor die 140 and the diode 150.
  • the molded body 160 has a first side 161, an opposite second side 162 and lateral sides 163 connecting the first and second sides 161, 162.
  • the molded body 160 may comprise or consist of any suitable mold material.
  • the molded body 160 may comprise filler particles, e.g. inorganic particles configured to reduce the thermal resistance of the molded body 160.
  • the molded body 160 may for example be fabricated using compression molding, injection molding or transfer molding.
  • the external contacts 130 may be exposed from one or more of the lateral sides 163 of the molded body 160.
  • external contacts 130 may be arranged along two opposite lateral sides 163 of the molded body 160.
  • An arrangement of external contacts 130 to all four lateral sides 163 is also conceivable.
  • one or more of the external contacts 130 may be contiguous with the first die pad 110 (i.e. the respective external contact and the die pad are a single piece) and/or one or more of the external contacts may be contiguous with the second die pad 120. It is of course also possible that no external contact 130 is contiguous with the first and/or the second die pad 110, 120.
  • a distance between a plane which comprises the second side 162 of the molded body 160 and a parallel further plane, wherein the external contacts 130 are exposed from the lateral sides 163 of the molded body 160 in the further plane is about 1mm or more, or about 2mm or more, or about 3mm or more, or about 3.4mm.
  • the lateral sides 163 may be shaped such that a creepage distance between these two planes is about 3mm or more, or about 4mm or more, or about 5mm, or about 7mm or more.
  • the second side 112 of the first die pad 110 is exposed from the second side 162 of the molded body 160.
  • the second side 112 of the first die pad 110 may in particular be partially or completely exposed from the molded body 160.
  • the second side 122 of the second die pad 120 is completely covered by an electrically insulating material.
  • the electrically insulating material is the mold material of the molded body 160 (this example is shown in Fig. 1B ). In other words, in this case the second side 122 of the second die pad 120 is completely covered by the molded body 120.
  • the electrically insulating material is a material that is different from the mold material of the molded body 160.
  • the electrically insulating material may for example comprise or consist of a polymer, a laminate, a coating, a thermal interface material (TIM), a preform, a plastic, etc.
  • the electrically insulating material may be configured to electrically insulate the second die pad 120 at the second side 162 of the molded body 160.
  • the electrically insulating material may e.g. be configured to insulate the second die pad 120 at the second side 162 of the molded body 160 against a voltage difference of 100V or more, or 500V or more, or 1kV or more, or 1.2kV or more, or 2kV or more.
  • the first die pad 110 is at ground (GND) potential.
  • the second die pad 120 on the other hand may be at a high potential, e.g. 100V or more, or 500V or more, or 1kV or more, or 1.2kV or more, or 2kV or more.
  • the second side 162 of the molded body 160 may be configured to be arranged on a heatsink.
  • the heatsink may be joined with the the second side 112 of the first die pad 110 by joining methods, e.g., by soldering or welding. Such a joint without any dielectric material between the first die pad 110 and the heatsink may provide a heat dissipation path with a low thermal resistance.
  • the first die pad 110 is at a low potential, e.g. at GND potential, it is not problematic that the heatsink is electrically coupled to the first die pad 110. Since the second die pad 120 however is at a high potential, it may be necessary to electrically insulate it from the heatsink.
  • Using the mold material of the molded body 160 as electrical insulation between the second die pad 120 and the heatsink may be more cost efficient than providing a separate insulation.
  • Figures 2A and 2B show a further power semiconductor package 200 which may be similar or identical to the power semiconductor package 100, except for the differences described in the following.
  • Fig. 2A shows a perspective view and Fig. 2B shows a side view.
  • the power semiconductor package 200 may comprise a first electrical connector 210 which couples the power semiconductor die 140 to the diode 150.
  • the first electrical connector 210 may be coupled to an upper side of the power semiconductor die 140 and to the first side 121 of the second die pad 120.
  • the first electrical connector 210 may in particular be coupled to a power electrode, e.g. a drain electrode or a collector electrode, on the upper side of the power semiconductor die 140.
  • the first electrical connector 210 may e.g. comprise or consist of a contact clip, a bond wire or a ribbon.
  • the power semiconductor package 200 comprises the first and second die pads 110, 120 and it further comprises a third pad 220.
  • the third die pad 220 may be separated from the first die pad 110 by a second gap 230 and it may be separated from the second die pad 120 by a third gap 240.
  • the second gap 230 is an extension, e.g. a straight extension, of the first gap 170 (compare Fig. 2A ).
  • the third gap 240 is arranged essentially perpendicular to the first gap 170 and/or the second gap 230.
  • the first, second and third gaps 170, 230 and 240 may essentially form a T-junction (compare Fig. 2A ).
  • the third die pad 220 may comprise or consist of the same material as described with respect to the first and second die pads 110, 120.
  • the third die pad 220 may be part of the same leadframe as the first die pad 110 and/or the second die pad 120.
  • the third die pad 220 may e.g. have the same thickness as the second die pad 120.
  • the third die pad 220 may comprise a first side and an opposite second side.
  • the first side may be coplanar with the first sides 111, 121 of the first and second die pads 110, 120.
  • the second side of the third die pad 220 may be coplanar with the second side 122 of the second die pad 120.
  • the third die pad 220 is covered by electrically insulating material (e.g. the mold material of the molded body 160) at the second side 162 of the molded body 160, similar to the second die pad 120.
  • the third die pad 220 does not carry any semiconductor die or diode and instead acts as connector for external contacts 130 (compare Fig. 2A ).
  • the external contact(s) 130 coupled to the first die pad 110 may e.g. be configured as input terminals of the power semiconductor package 200.
  • the external contact(s) 130 coupled to the third die pad 220 may e.g. be configured as output terminals of the power semiconductor package 200.
  • the power semiconductor package 200 may comprise a second electrical connector 250 coupling the diode 150 to the third die pad 220.
  • the second electrical connector 250 may be coupled to an electrode on the upper side of the diode 150 and to the first side of the third die pad 220.
  • the second electrical connector 250 may e.g. comprise or consist of a contact clip, a bond wire or a ribbon.
  • the power semiconductor die 140 may be arranged on the first die pad 110 such that the power semiconductor die 140 partially overhangs.
  • the power semiconductor die 140 may comprise an electrode, e.g. a gate electrode, on the overhanging part of its lower side. In this manner, this electrode can be contacted, e.g. using a bond wire.
  • the first die pad 110 may comprise a cutout section, wherein the power semiconductor die 140 overhangs in the cutout section.
  • Figure 3 shows an electronics system 300 comprising the power semiconductor package 100, a heatsink 310 and an application board 320.
  • the electronics system comprises the power semiconductor package 200 instead of the power semiconductor package 100.
  • the heatsink 310 is arranged at the second side 162 of the molded body 160 and the application board 320 is arranged at the first side 161 of the molded body 160.
  • the electrically insulating material isolates the second die pad 120 from the heatsink 310.
  • the heatsink 310 may e.g. be coupled to the first die pad 110 by one or more of soldering, welding, mechanical fixing, gluing with conductive glue, etc.
  • a layer of thermal interface material (TIM) may be arranged between the power semiconductor package 100 or 200 and the heatsink 310.
  • the layer of TIM may in particular be arranged between the first die pad 110 and the heatsink 310 as well as between the second die pad 120 and the heatsink.
  • the TIM sheet may be electrically conductive. This may offer advantages in terms of cost and thermal conductivity (for example, in this case the TIM can be a simple Al foil). If there is no insulation over the second die pad 120 at the second side 162 after molding (i.e. there is a hole left in the mold body during molding at the second side 162) a liquid, insulating gap filler may be dispensed in this hole in the mold.
  • a generic liquid (which is electrically insulating) could be applied as gap filler for the topping up of the left mold hole over the second die pad 120 at the second side 162
  • the generic liquid may in this case be used as a wide TIM layer which may essentially cover the whole package at the second side 162.
  • the power semiconductor package 100 or 200 may be a surface mount device (SMD) configured to be surface mounted onto the application board 320.
  • SMD surface mount device
  • TDD through hole device
  • Figure 4 shows an exemplary electrical circuit 400, wherein the semiconductor package 100 or 200 may be used in a part 410 of this electrical circuit 400.
  • the electrical circuit 400 may for example comprise a power factor correction circuit of e.g. a solar inverter.
  • the electrical circuit 400 may comprise the part 410 which may be realized using the semiconductor package 100 or 200 and it may also comprise a variable voltage source 420, a DC/DC converter 430 and a load 440.
  • Figure 5 is a flow chart of an exemplary method 500 for fabricating a power semiconductor package.
  • the method 500 may for example be used to fabricate the power semiconductor packages 100 and 200.
  • the method 500 comprises at 501 a process of providing a leadframe which comprises a first die pad, a second die pad and a plurality of external contacts, wherein the first and second die pads are separated by a first gap, at 502 a process of arranging a power semiconductor die on a first side of the first die pad and electrically coupling the power semiconductor die to the first side of the first die pad, at 503 a process of arranging a diode on a first side of the second die pad and electrically coupling the diode to the first side of the second die pad, at 504 a process of encapsulating the power semiconductor die and the diode with a molded body, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides, such that a second side of the first die pad opposite the first side of the first die pad is exposed from the second side of the molded body, and at 505 a process of completely covering a second side of the second die pad opposite the first side of the second die pad with an
  • Example 1 is a power semiconductor package, comprising: a leadframe comprising a first die pad, a second die pad and a plurality of external contacts, wherein the first and second die pads are separated by a first gap, a power semiconductor die arranged on and electrically coupled to a first side of the first die pad, a diode arranged on and electrically coupled to a first side of the second die pad, and a molded body encapsulating the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides, wherein a second side of the first die pad opposite the first side of the first die pad is exposed from the second side of the molded body and wherein a second side of the second die pad opposite the first side of the second die pad is completely covered by an electrically insulating material.
  • Example 2 is the power semiconductor package of example 1, wherein the insulating material is a mold material of the molded body.
  • Example 3 is the power semiconductor package of example 1, wherein the electrically insulating material is different from a mold material of the molded body.
  • Example 4 is the power semiconductor package of one of the preceding examples, wherein the first sides of the first and second die pad are coplanar.
  • Example 5 is the power semiconductor package of one of the preceding examples, wherein the second side of the first die pad is arranged in a first plane and the second side of the second die pad is arranged in a different, second plane.
  • Example 6 is the power semiconductor package of one of the preceding examples, wherein the external contacts are exposed from two opposite lateral sides of the molded body.
  • Example 7 is the power semiconductor package of one of the preceding examples, wherein a first one of the external contacts is contiguous with the first die pad and a second one of the external contacts is contiguous with the second die pad.
  • Example 8 is the power semiconductor package of one of the preceding examples, wherein the power semiconductor die comprises a first side and an opposite second side, wherein the second side faces the first side of the first die pad, and wherein a first electrical connector couples the first side of the power semiconductor die to the first side of the second die pad.
  • Example 9 is the power semiconductor package of one of the preceding examples, wherein the leadframe further comprises a third die pad separated from the first die pad by a second gap and separated from the second die pad by a third gap.
  • Example 10 is the power semiconductor package of example 9, wherein the diode comprises a first side and an opposite second side, wherein the second side faces the first side of the second die pad, and wherein a second electrical connector couples the first side of the diode to a first side of the third die pad.
  • Example 11 is the power semiconductor package of example 9 or 10, wherein a third one of the external contacts is contiguous with the third pad.
  • Example 12 is the power semiconductor package of one of the preceding examples, wherein the power semiconductor die is coupled to the first die pad in a flip-chip configuration such that a source electrode of the power semiconductor die faces the first die pad.
  • Example 13 is the power semiconductor package of one of the preceding examples, wherein a thickness of the electrically insulating material over the second side of the second die pad is in the range of 50 ⁇ m to 0.5mm, in particular in the range of 0.1mm to 0.3mm, more in particular wherein the thickness is about 0.2mm.
  • Example 14 is a method for fabricating a power semiconductor package, the method comprising: providing a leadframe which comprises a first die pad, a second die pad and a plurality of external contacts, wherein the first and second die pads are separated by a first gap, arranging a power semiconductor die on a first side of the first die pad and electrically coupling the power semiconductor die to the first side of the first die pad, arranging a diode on a first side of the second die pad and electrically coupling the diode to the first side of the second die pad, encapsulating the power semiconductor die and the diode with a molded body, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides, such that a second side of the first die pad opposite the first side of the first die pad is exposed from the second side of the molded body, and completely covering a second side of the second die pad opposite the first side of the second die pad with an electrically insulating material.
  • Example 15 is the method of example 14, wherein covering the second side of the second die pad with the electrically insulating material comprises molding over the second side of the second die pad.
  • Example 16 is an apparatus with means for performing the method according to example 14 or 15.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
EP22206519.5A 2022-11-10 2022-11-10 Leistungshalbleitergehäuse und verfahren zu seiner herstellung Pending EP4369394A1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP22206519.5A EP4369394A1 (de) 2022-11-10 2022-11-10 Leistungshalbleitergehäuse und verfahren zu seiner herstellung
CN202311493520.6A CN118016625A (zh) 2022-11-10 2023-11-09 功率半导体封装及其制造方法
US18/388,559 US20240162205A1 (en) 2022-11-10 2023-11-10 Power semiconductor package and method for fabricating the same

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982879A (ja) * 1995-09-20 1997-03-28 Fuji Electric Co Ltd 樹脂封止型半導体装置
US20050151236A1 (en) * 2003-11-12 2005-07-14 International Rectifier Corporation Low profile package having multiple die
US20070216011A1 (en) * 2006-03-17 2007-09-20 Ralf Otremba Multichip module with improved system carrier
US20160343644A1 (en) * 2014-05-12 2016-11-24 Mitsubishi Electric Corporation Power semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982879A (ja) * 1995-09-20 1997-03-28 Fuji Electric Co Ltd 樹脂封止型半導体装置
US20050151236A1 (en) * 2003-11-12 2005-07-14 International Rectifier Corporation Low profile package having multiple die
US20070216011A1 (en) * 2006-03-17 2007-09-20 Ralf Otremba Multichip module with improved system carrier
US20160343644A1 (en) * 2014-05-12 2016-11-24 Mitsubishi Electric Corporation Power semiconductor device and method of manufacturing the same

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US20240162205A1 (en) 2024-05-16

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