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  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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  • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
  • H01L29/151—Compositional structures
  • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
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  • H01L29/0843—Source or drain regions of field-effect devices
  • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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  • H01L29/1025—Channel region of field-effect devices
  • H01L29/1029—Channel region of field-effect devices of field-effect transistors
  • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
  • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
  • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66568—Lateral single gate silicon transistors
  • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
  • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location

Definitions

• the present disclosure generally relates to semiconductor devices and, more particularly, to semiconductor devices with enhanced semiconductor materials and associated methods.
• U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.
• a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown.
• the direction of main current flow is perpendicular to the layers of the superlattice.
• U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice.
• U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.
• U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of Si02/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
• An article entitled “Phenomena in silicon nanostructure devices” also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen.
• the Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices.
• a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
• the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
• One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon.
• An article to Luo et al. entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002) further discusses the light emitting SAS structures of Tsu.
• U.S. Pat. No. 7,105,895 to Wang et al. discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude.
• the insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.
• a method for producing an insulating or barrier layer for semiconductor devices which includes depositing a layer of silicon and at least one additional element on the silicon substrate whereby the deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on the deposited layer.
• a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate.
• a plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite.
• a semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and comprising a plurality of stacked groups of layers.
• Each group of layers may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
• the at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18 0 greater than 10 percent.
• the at least one oxygen monolayer of the given group of layers may comprise an atomic percentage of 18 0 greater than 50 percent, and more particularly greater than 90 percent.
• the at least one oxygen monolayer of the given group of layers may further comprises 16 0 in some embodiments.
• the at least one oxygen monolayer of each group of layers may comprise an atomic percentage of 18 0 greater than 10 percent.
• the semiconductor device may further include source and drain regions on the semiconductor layer and defining a channel in the superlattice, and a gate above the superlattice.
• the semiconductor device may further include a metal layer above the superlattice.
• the superlattice may divide the semiconductor layer into a first region and a second region, with the first region having a same conductivity type and a different dopant concentration than the second region.
• the superlattice may divide the semiconductor layer into a first region and a second region, with the first region having a different conductivity type than the second region.
• the base semiconductor layer may comprise silicon.
• a method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and comprising a plurality of stacked groups of layers.
• Each group of layers may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
• the at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18 0 greater than 10 percent.
• the at least one oxygen monolayer of the given group of layers may comprise an atomic percentage of 18 0 greater than 50 percent, and more particularly greater than 90 percent.
• the at least one oxygen monolayer of the given group of layers may further comprises 16 0 in some embodiments.
• the at least one oxygen monolayer of each group of layers may comprise an atomic percentage of 18 0 greater than 10 percent.
• the method may further include forming source and drain regions on the semiconductor layer and defining a channel in the superlattice, and forming a gate above the superlattice.
• the method may further include forming a metal layer above the superlattice.
• the superlattice may divide the semiconductor layer into a first region and a second region, with the first region having a same conductivity type and a different dopant concentration than the second region.
• the superlattice may divide the semiconductor layer into a first region and a second region, with the first region having a different conductivity type than the second region.
• the base semiconductor layer may comprise silicon.
• FIG. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with an example embodiment.
• FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1.
• FIG. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with an example embodiment.
• FIG. 4A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2.
• FIG. 4B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2.
• FIG. 4C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1 /3/1 Si/O superlattice as shown in FIG. 3.
• FIG. 5 is a schematic cross-sectional view of a semiconductor device including a superlattice with an enriched 18 0 monolayer in accordance with an example embodiment.
• FIG. 6 is a schematic cross-sectional view of another semiconductor device including a superlattice with a plurality of enriched 18 0 monolayers and dividing a semiconductor layer into regions of different conductivity types.
• FIG. 7 is a graph of measured oxygen concentration vs depth for a test semiconductor device including typical 16 0 monolayers and 18 0 enhanced monolayers.
• FIG. 8 is a table showing 18 0 and 16 0 dose loss for the implementation of FIG. 7.
• FIG. 9 is a graph of 18 0 and 16 0 dose loss vs. anneal temperature for the implementation of FIG. 7.
• FIG. 10 is a graph of 18 0 and 16 0 dose loss percentage vs. anneal temperature for the implementation of FIG. 7.
• FIG. 11 is a schematic cross-sectional view of a semiconductor device including a superlattice channel with one or more enriched 18 0 monolayers.
• FIG. 12 is a schematic cross-sectional view of a semiconductor device including a superlattice with one or more enriched 18 0 monolayers and dividing a semiconductor layer into regions having a same conductivity type and different dopant concentrations.
• FIG. 13 is a schematic cross-sectional view of a semiconductor device including a superlattice with one or more enriched 18 0 monolayers and including a metal contact layer above the superlattice.
• the present disclosure relates to the formation of semiconductor devices utilizing an enhanced semiconductor superlattice.
• the enhanced semiconductor superlattice may also be referred to as an “MST” layer/film or “MST technology” in this disclosure.
• the MST technology relates to advanced semiconductor materials such as the superlattice 25 described further below.
• Applicant theorizes, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass
• Applicant’s use a "conductivity reciprocal effective mass tensor", for electrons and holes respectively, defined as: for electrons and: for holes, where is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
• Applicant s definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor.
• Applicant theorizes without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport.
• the inverse of the appropriate tensor element is referred to as the conductivity effective mass.
• the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
• Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, Applicant has identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.
• the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition.
• the superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 1.
• Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon.
• the energy band-modifying layers 50 are indicated by stippling in FIG. 1 for clarity of illustration.
• the energy band-modifying layer 50 illustratively includes one non semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
• constrained within a crystal lattice of adjacent base semiconductor portions it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer 50 therebetween, as seen in FIG. 2.
• this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46a-46n through atomic layer deposition techniques so that not all (i.e.
• non-semiconductor monolayer may be possible.
• reference herein to a non semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
• this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. These properties may thus advantageously allow the superlattice 25 to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.
• the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.
• the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.
• the superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n.
• the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
• the cap layer 52 may have between 1 to 100 monolayers 46 of the base semiconductor, and, more preferably between 10 to 50 monolayers. However, in some applications the cap layer 52 may be omitted, or thicknesses greater than 100 monolayers may be used.
• Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group lll-V semiconductors, and Group ll-VI semiconductors.
• Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art.
• the base semiconductor may comprise at least one of silicon and germanium, for example.
• Each energy band-modifying layer 50 may comprise a non semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example.
• the non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
• the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art.
• the base semiconductor may comprise at least one of silicon and germanium, for example.
• the term monolayer is meant to include a single atomic layer and also a single molecular layer.
• the energy band modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e. , there is less than full or 100% coverage).
• a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.
• this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed, it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition.
• a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.
• Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction.
• the calculated conductivity effective mass for electrons is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46.
• the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.
• the lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
• the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.
• FIG. 3 another embodiment of a superlattice 25’ in accordance with the invention having different properties is now described.
• a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a’ has three monolayers, and the second lowest base semiconductor portion 46b’ has five monolayers. This pattern repeats throughout the superlattice 25’.
• the energy band-modifying layers 50’ may each include a single monolayer.
• the enhancement of charge carrier mobility is independent of orientation in the plane of the layers.
• all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.
• FIGS. 4A-4C band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Flence all bands above the gap may be shifted by an appropriate “scissors correction.” Flowever, the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.
• FIG. 4A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice 25 shown in FIG. 1 (represented by dotted lines).
• the directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
• the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
• the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.
• the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
• the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
• FIG. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.
• FIG. 4C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1 /3/1 Si/O structure of the superlattice 25’ of FIG. 3 (dotted lines). Due to the symmetry of the 5/1 /3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
• the above-described superlattice films 25 may be fabricated with one or more oxygen monolayers 50 which have an increased or enhanced amount of 18 0.
• the approximate concentration of stable oxygen isotopes present in the gas flow used for oxygen deposition may be as follows:
• a superlattice 125 is formed adjacent a semiconductor layer 121 (e.g., substrate) which includes two groups of monolayers 145a, 145b, each including a base semiconductor portion 146a, 146b with four semiconductor (e.g., silicon) monolayers 146, and a respective oxygen monolayer 150a, 150b.
• a semiconductor layer 121 e.g., substrate
• four semiconductor (e.g., silicon) monolayers 146 e.g., silicon
• oxygen monolayer 150a, 150b e.g., oxygen monolayer
• other base semiconductor portion thicknesses may be used in different embodiments, e.g., up to twenty-five monolayers 146 or even fifty monolayers (or more) in some implementations.
• the oxygen monolayer 150a is fabricated using a gas flow having an enhanced or increased amount of 18 0 to thereby provide an 18 0 enriched monolayer.
• the monolayer 150a may comprise an atomic percentage of 18 0 greater than ten percent. That is, the number of 18 0 atoms present in the monolayer 150a may constitute 10% or more of the total oxygen atoms in this monolayer(s).
• the atomic percentage of 18 0 atoms in the monolayer 150a may be greater than fifty percent of the total oxygen atoms, and more particularly greater than ninety percent.
• the 18 0 enriched monolayer 150a may also include some portion of 16 0.
• each of the two groups of layers 145a’, 145b’ has a respective 18 0 enriched monolayer 150a’.
• Other superlattice layer configurations may also be used in different embodiments.
• the use of one or more 18 0 enriched monolayers 150a in an MST layer may be advantageous in view of the kinetic isotope effect of interstitial oxygen within the semiconductor (e.g., silicon) lattice of the base semiconductor portions 146a, 146b. More particularly, free oxygen atoms in silicon are relatively highly mobile, which may lead to unwanted diffusion via an interstitial mechanism. Diffusion of oxygen is thermally activated, and is therefore susceptible to occur in subsequent thermal processing steps (e.g., gate formation, etc.) after the superlattice 125 formation.
• the semiconductor e.g., silicon
• free oxygen atoms in silicon are relatively highly mobile, which may lead to unwanted diffusion via an interstitial mechanism. Diffusion of oxygen is thermally activated, and is therefore susceptible to occur in subsequent thermal processing steps (e.g., gate formation, etc.) after the superlattice 125 formation.
• 18 0 is chemically equivalent to 16 0 in terms of its nuclear spin (both are 0), it is well suited for use in the above-described superlattice structures where oxygen monolayers with typical 16 0 concentrations would otherwise be used.
• activation energy for a lighter isotope is less than for a heavier isotope.
• 16 0 is a lighter isotope than 18 0, meaning that 18 0 will have a higher activation energy than 16 0.
• activated processes for 18 0 are accordingly slower, meaning that 18 0 will diffuse more slowly than 16 0.
• 18 0 enriched monolayers 150a will experience less diffusion/oxygen loss during the above-noted thermal processing, for example.
• the location of the oxygen monolayer 150a occurs between 20 and 30 nm from the surface and has an 18 0 concentration in a range of 1x10 21 atoms/cm 3 .
• the corresponding measurements for the test film are shown in the table 180 of FIG. 8, the corresponding dose loss vs. anneal temperature is shown in the graph 190, and the corresponding dose loss percentage vs. anneal temperature is shown in the graph 195 of FIG. 10.
• MOSFET 220 includes a substrate 221, source/drain regions 222, 223, source/drain extensions 226, 227, and a channel region therebetween provided by an 18 0 enhanced superlattice 225.
• the channel may be formed partially or completely within the superlattice 225.
• Source/drain silicide layers 230, 231 and source/drain contacts 232, 233 overlie the source/drain regions as will be appreciated by those skilled in the art.
• Regions indicated by dashed lines 234a, 234b are optional vestigial portions formed originally with the superlattice 225, but thereafter heavily doped. In other embodiments, these vestigial superlattice regions 234a, 234b may not be present as will also be appreciated by those skilled in the art.
• a gate 235 illustratively includes a gate insulating layer 237 adjacent the channel provided by the superlattice 225, and a gate electrode layer 236 on the gate insulating layer. Sidewall spacers 240, 241 are also provided in the illustrated MOSFET 220.
• the device 100 in accordance with another example of a device in which an 18 0 enriched superlattice 325 may be incorporated is a semiconductor device 300, in which the superlattice is used as a dopant diffusion blocking superlattice to advantageously increase surface dopant concentration to allow a higher ND (active dopant concentration at metal/semiconductor interface) during in-situ doped epitaxial processing by preventing diffusion into a channel region 330 of the device.
• the device 100 illustratively includes a semiconductor layer or substrate 301 , and spaced apart source and drain regions 302, 303 formed in the semiconductor layer with the channel region 330 extending therebetween.
• the dopant diffusion blocking superlattice 325 illustratively extends through the source region 302 to divide the source region into a lower source region 304 and an upper source region 305, and also extends through the drain region 303 to divide the drain region into a lower drain region 306 and an upper drain region 307.
• the dopant diffusion blocking superlattice 325 may also conceptually be considered as a source dopant blocking superlattice within the source region 302, a drain dopant blocking superlattice within the drain region 303, and a body dopant blocking superlattice beneath the channel 330, although in this configuration all three of these are provided by a single blanket deposition of the MST material across the substrate 301 as a continuous film.
• the semiconductor material above the dopant blocking superlattice 325 in which the upper source/drain regions 305, 307 and channel region 330 are defined may be epitaxially grown on the dopant blocking superlattice 325 either as a thick superlattice cap layer or bulk semiconductor layer, for example.
• the upper source/drain regions 305, 307 may each be level with an upper surface of this semiconductor layer (i.e. , they are implanted within this layer).
• the upper source/drain regions 305, 307 may advantageously have a same conductivity as the lower source/drain regions 304, 306, yet with a higher dopant concentration.
• the upper source/drain regions 305, 307 and the lower source/drain regions 304, 306 are N-type for a N- channel device, but these regions may also be P-type for a P-channel device as well.
• Surface dopant may be introduced by ion implantation, for example.
• the dopant diffusion is reduced by the MST film material of the diffusion blocking superlattice 325 because it traps point defects/interstitials introduced by ion implantation which mediate dopant diffusion.
• the semiconductor device 300 further illustratively includes a gate 308 on the channel region 330.
• the gate illustratively includes a gate insulating layer 309 gate electrode 310. Sidewall spacers 311 are also provided in the illustrated example. Further details regarding the device 300, as well as other similar structures in which an 18 0 enriched superlattice may be used, are set forth in U.S. Pat. No. 10,818,755 to Takeuchi et al. , which is assigned to the present Applicant and hereby incorporated herein in its entirety by reference.
• both source and drain dopant diffusion blocking superlattices 425s, 425d advantageously provide for Schottky barrier height modulation via hetero-epitaxial film integration.
• the lower source and drain regions 404, 406 include a different material than the upper source and drain regions 405, 407.
• the lower source and drain regions 404, 406 are silicon
• the upper source and drain regions 405, 407 are SiGeC, although different materials may be used in different embodiments.
• Lower metal layers (Ti) 442, 443 are formed on the upper source and drain regions (SiGeC layers) 405, 407.
• Upper metal layers (Co) 444, 445 are formed on the lower metal layers 442, 443, respectively. Because the MST material is effective in integrating hetero-epitaxial semiconductor material, incorporation of C(1-2%) to Si or SiGe on Si may induce a positive conduction band offset. More particularly, this is a SiGeC/MST/n+ Si structure that is effective for reducing Schottky barrier height. Further details regarding the device 400 are set forth in the above-noted 755 patent.
• the materials and techniques identified herein may be used in many different types of semiconductor devices, such as discrete devices and/or integrated circuits.
• the 18 0 enriched superlattice 125’ divides the substrate 121’ and the cap layer 52’, but the substrate has a different conductivity type (P) than the cap layer (N) to thereby define a PN junction.
• the PN junction may be lateral, as opposed to vertically oriented as shown in the example of FIG. 6.
• Further PN junction applications in which 18 0 enriched superlattice may be used are set forth in U.S. Pat. No.
• 18 0 enriched monolayers may also be incorporated in superlattices and associated applications such as those described in co-pending application nos. 17/236,289 and 17/236,329 filed 04/21/2021, which are hereby incorporated herein in their entireties by reference.
• an 18 0 source can be used interchangeably with traditional 16 0 sources to fabricate the above-described semiconductor superlattices.
• Applicant has found that similar 18 0 flow rates yield similar oxygen dosages to those of 16 0.
• the semiconductor monolayer growth and etch rates are also similar between 16 0 and 18 0 sources.
• Phenomenological study/observations have revealed that 16 0 incorporation in the 18 0 superlattice layers is affected by the above-described MEGA etch. More particularly, with respect to the test device represented in FIG.
• a related method for making a semiconductor device 120 may include forming a semiconductor layer 121 , and forming a superlattice 125 adjacent the semiconductor layer and including stacked groups of layers 145a, 145b.
• Each group of layers 145a, 145b may include stacked base semiconductor monolayers 146 defining a base semiconductor portion 146a, 146b, and at least one oxygen monolayer 150a constrained within a crystal lattice of adjacent base semiconductor portions.
• the at least one oxygen monolayer 150a may comprise an atomic percentage of 18 0 greater than 10 percent, as discussed further above.
• further method aspects may include forming source and drain regions 222, 223 on the semiconductor layer 221 and defining a channel in the superlattice 225, and forming a gate 235 above the superlattice.
• further method aspects may include forming a metal layer 442/444 and/or 443/445 above the superlattice 425s, 425d, as discussed further above.

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