EP4256611A1 - Circuits de cellule binaire de calcul en mémoire (cim) placés chacun dans une orientation d'un agencement de circuit de cellule binaire cim comprenant un circuit de ligne de mots de lecture (rwl) dans un circuit de réseau de cellules binaires cim - Google Patents

Circuits de cellule binaire de calcul en mémoire (cim) placés chacun dans une orientation d'un agencement de circuit de cellule binaire cim comprenant un circuit de ligne de mots de lecture (rwl) dans un circuit de réseau de cellules binaires cim

Info

Publication number
EP4256611A1
EP4256611A1 EP21801308.4A EP21801308A EP4256611A1 EP 4256611 A1 EP4256611 A1 EP 4256611A1 EP 21801308 A EP21801308 A EP 21801308A EP 4256611 A1 EP4256611 A1 EP 4256611A1
Authority
EP
European Patent Office
Prior art keywords
true
circuit
bit cell
cim
complement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21801308.4A
Other languages
German (de)
English (en)
Inventor
Xiaonan Chen
Zhongze Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/404,378 external-priority patent/US11626156B2/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP4256611A1 publication Critical patent/EP4256611A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Definitions

  • the field of the disclosure relates generally to compute-in-memory (CIM) arrays used in circuits for high-speed parallel data processing, such as neural networks.
  • CCM compute-in-memory
  • Machine learning is an example of artificial intelligence (Al) that can be employed to improve performance of some applications in a processing device
  • a neural network is one type of processor configuration in which an application can learn by evaluating input data based on historical information, receiving feedback on the accuracy of the evaluation, and adjusting the historical information accordingly.
  • the operations of a neural network implementing machine learning are performed by arrays of nodes that each resemble a brain synapse. Each node performs a multiply-accumulate (MAC) operation in which each input in a set of inputs is multiplied by a weight data in a multiplication operation and the products representing the weighted inputs are summed together.
  • Each evaluation can include thousands of calculations. Initial weight data is modified based on feedback to increase accuracy of an application.
  • FIG. 1 is an illustration of a node 100 of a neural network configured to perform a MAC operation.
  • the node 100 receives a set of inputs X 0 -X M that are each multiplied by a corresponding one of weight values W 0 -W M .
  • the weight values W 0 -W M are based on feedback from previous calculations and are updated to improve the accuracy of calculations regarding a particular type of input data over time.
  • the products P 0 -P M of the multiplications are accumulated (e.g., added) in an accumulation function ⁇ to generate a sum SUM, and the node 100 generates an output OUT that is a function AF (e.g., activation function) of the sum SUM.
  • AF e.g., activation function
  • the input data and weight data may each be represented by a bit of binary data.
  • Each bit cell of the array includes a memory bit cell for storing the weight data and a multiplication circuit.
  • a multiplication of two one- bit binary data values in a CIM bit cell may be implemented as a logical AND-based operation (e.g., AND or Not AND (NAND)) or as a logical OR-based operation (e.g., OR, Not OR (NOR), or not exclusive-OR (XNOR)).
  • Figure 2 is a truth table illustrating a multiplication of a received input X and input W to produce an XNOR output in a CIM bit cell circuit.
  • the input X is an activation input and the input W is a stored weight data.
  • a CIM array bit cell circuit that executes MAC instructions in a processing circuit improves performance in machine learning applications but occupies a large area of an integrated circuit (IC).
  • the layout of CIM bit cell circuits in a CIM: array determines both the total area occupied by the CIM array and the uniformity of operation of the respective CIM bit cell circuits.
  • CIM bit cell circuits each disposed in an orientation of a CIM bit cell circuit layout including a read word line (RWL) circuit in a CIM bit cell array circuit.
  • RWL read word line
  • An exemplary CIM bit cell array circuit (“CIM array circuit”) includes exemplary CIM bit cell circuits to execute a multiply-accumulate (MAC) operation.
  • the CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form.
  • the CIM bit cell circuits also include a true pass-gate circuit and a complement pass-gate circuit for generating a product of the weight data and an activation input on a product node.
  • the product is a not exclusive-OR (XNOR) of the true weight data and the activation input.
  • the CIM bit cell circuits also include an RWL circuit coupled to the product node and a ground voltage rail for initializing the product data.
  • the CIM bit cell circuits also include a plurality of gates that extend in a first axis direction and are separated from each other in a second axis direction orthogonal to the first axis direction.
  • the plurality of gates includes consecutive gates in the second axis direction and each of the consecutive gates is coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit.
  • the respective CIM bit cell circuits operate with increased uniformity, which improves performance and reliability of the CIM array circuit.
  • a CIM bit cell circuit including a memory bit cell circuit, a true pass-gate circuit, a complement pass-gate circuit, and an RWL circuit.
  • the memory bit cell circuit comprises a true pull-up transistor coupled to a supply voltage rail and a true output node and a true pull-down transistor coupled to the true output node and a ground voltage rail.
  • the memory bit cell circuit comprises a complement pull-up transistor coupled to the supply voltage rail and a complement output node and a complement pull-down transistor coupled to the complement output node and the ground voltage rail.
  • the true pass-gate circuit comprises a first true transistor coupled to the true output node and a product node and a second true transistor coupled to the true output node and the product node.
  • the complement pass-gate circuit comprises a first complement transistor coupled to the complement output node and the product node and second complement transistor coupled to the complement output node and the product node.
  • the RWL circuit comprises an RWL transistor coupled to the ground voltage rail and the product node.
  • the CIM bit cell circuit also includes a plurality of gates extending in a first axis direction and separated from each other in a second axis direction orthogonal to the first axis direction, wherein the plurality of gates comprises consecutive gates in the second axis direction, each of the consecutive gates coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit.
  • a CIM bit cell circuit including a semiconductor substrate, a P-type diffusion region in the semiconductor substrate, and an N-type diffusion region in the semiconductor substrate.
  • the CIM bit cell circuit includes a memory bit cell circuit, a true pass-gate circuit, a complement pass-gate circuit, and an RWL transistor.
  • the memory bit cell circuit comprises a true pull-up transistor coupled to a supply voltage rail and a true output node and a true pull-down transistor coupled to the true output node and a ground voltage rail.
  • the memory bit cell circuit comprises a complement pull-up transistor coupled to the supply voltage rail and a complement output node and a complement pull-down transistor coupled to the complement output node and the ground voltage rail.
  • the true pass-gate circuit comprises a first true transistor coupled to the true output node and a product node and a second true transistor coupled to the true output node and the product node.
  • the complement pass- gate circuit comprises a first complement transistor coupled to the complement output node and the product node and second complement transistor coupled to the complement output node and the product node.
  • the RWL transistor is coupled to the ground voltage rail and the product node.
  • the true pull-down transistor, the complement pull-down transistor, the first true transistor, the first complement transistor, and the RWL transistor each comprise a portion of the N-type diffusion region.
  • a CIM bit cell array circuit including a semiconductor substrate and a plurality of CIM bit cell circuits on the semiconductor substrate.
  • Each of the plurality of CIM bit cell circuits comprises a P-type diffusion region disposed in the semiconductor substrate and an N-type diffusion region disposed in the semiconductor substrate.
  • Each of the plurality of CIM bit cell circuits further comprises a memory bit cell circuit, a true pass-gate circuit, a complement pass- gate circuit, an RWL circuit, and a plurality of gates.
  • the memory bit cell circuit comprises a true pull-up transistor coupled to a supply voltage rail and a true output node and a true pull-down transistor coupled to the true output node and a ground voltage rail.
  • the memory bit cell circuit comprises a complement pull-up transistor coupled to the supply voltage rail and a complement output node and a complement pull-down transistor coupled to the complement output node and the ground voltage rail.
  • the true pass-gate circuit comprises a first true transistor coupled to the true output node and a product node and a second true transistor coupled to the true output node and the product node.
  • the complement pass-gate circuit comprises a first complement transistor coupled to the complement output node and the product node and second complement transistor coupled to the complement output node and the product node.
  • the RWL circuit comprises an RWL transistor coupled to the ground voltage rail and the product node.
  • the plurality of gates extends in a first axis direction and are separated from each other in a second axis direction orthogonal to the first axis direction, wherein each of the memory bit cell circuit, the true pass-gate circuit, and the complement pass-gate circuit comprises at least one transistor disposed in the P-type diffusion region and at least one transistor disposed in the N-type diffusion region, and the plurality of gates comprises consecutive gates in the second axis direction, each of the consecutive gates coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit.
  • a method of fabricating a CIM bit cell array circuit comprising a plurality of CIM bit cell circuits on a semiconductor substrate.
  • the method comprises forming a P-type diffusion region and an N-type diffusion region in the semiconductor substrate.
  • the method comprises forming a memory bit cell circuit comprising a true pull-up transistor coupled to a supply voltage rail and a true output node, a true pull-down transistor coupled to the true output node and a ground voltage rail, a complement pull-up transistor coupled to the supply voltage rail and a complement output node, and a complement pull-down transistor coupled to the complement output node and the ground voltage rail.
  • the method comprises forming a true pass-gate circuit comprising a first true transistor coupled to the true output node and a product node, and a second true transistor coupled to the true output node and the product node.
  • the method comprises forming a complement pass-gate circuit comprising a first complement transistor coupled to the complement output node and the product node, and a second complement transistor coupled to the complement output node and the product node.
  • the method comprises forming an RWL circuit comprising an RWL transistor coupled to the ground voltage rail and the product node and forming a plurality of gates extending in a first axis direction and separated from each other in a second axis direction orthogonal to the first axis direction, wherein the plurality of gates comprises consecutive gates in the second axis direction, and each of the consecutive gates is coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit.
  • Figure 1 is a block diagram of a neural network node for performing a multiply-accumulate (MAC) operation
  • Figure 2 is a truth table illustrating binary products generated in a not exclusive-OR (XNOR) operation for each combination of values of two binary inputs;
  • FIG. 3 is a schematic diagram of a compute-in-memory (CIM) bit cell circuit for a CIM array circuit that can execute a M AC operation;
  • CIM compute-in-memory
  • Figure 4A is a top view of four exemplary CIM bit cell circuits as illustrated in Figure 3, each CIM bit cell circuit in a respective orientation of a CIM bit cell circuit layout that includes a read word line (RWL) transistor to minimize performance variations;
  • RWL read word line
  • Figure 4B is a top view of a CIM bit cell circuit in one of the orientations of a CIM bit cell circuit layout in Figure 4 A;
  • Figure 5 is a schematic diagram of three (3) CIM bit cell circuits each for storing a true weight data and a complement weight data and generating an XNOR product data based on an activation input data;
  • Figure 6 is a top view of a set of three (3) CIM bit cell circuits each configured to perform a MAC operation corresponding to the neural network node in Figure 1 and a cluster of three (3) RWL transistors corresponding to the three (3) CIM bit cell circuits in a conventional CIM bit cell array circuit:
  • Figure 7 is a layout top view of N-well regions including P-type diffusion regions and P-well regions including N-type diffusion regions disposed in a semiconductor substrate in the sub-array of CIM bit cell circuits in Figure 5, the N-well regions limited to a distance corresponding to six (6) CIM bit cell circuits;
  • Figure 8 is a top view of N-well regions including P-type diffusion regions and P-well regions including N-type diffusion regions disposed in a semiconductor substrate according to the CIM bit cell array circuit in Figure 4A, the N-well regions extending a distance in a first axis direction corresponding to at least seven (7) CIM bit cell circuits;
  • Figure 9 is a timing diagram illustrating P-type diffusion regions of CIM bit cell circuits disposed in a semiconductor substrate in an array corresponding to Figure 4A and including metal traces for providing a supply voltage and a ground voltage to at least seven (7) consecutive CIM bit cell circuits disposed in a first axis direction;
  • Figures 10A and 10B are a flowchart illustrating a method of fabricating the CIM bit cell array circuit in Figure 4A;
  • FIG 11 is a block diagram of an exemplary wireless communications device that includes a radio frequency (RF) module including the CIM bit cell array circuit in Figure 4A; and
  • RF radio frequency
  • Figure 12 is a block diagram of an exemplary integrated circuit (IC) package including an exemplary CIM array circuit including a CIM bit cell circuit including a memory circuit, a true pass-gate circuit, a complement pass-gate circuit, and an RWL circuit disposed in an orientation of a common CIM bit cell circuit layout for increased operation uniformity, as illustrated in Figure 4 A, and according to any of the aspects disclosed herein.
  • IC integrated circuit
  • CIM bit cell circuits each disposed in an orientation of a CIM bit cell circuit layout including a read word line (RWL) circuit in a CIM bit cell array circuit.
  • RWL read word line
  • An exemplary CIM bit cell array circuit (“CIM array circuit”) includes exemplary CIM bit cell circuits to execute a multiply-accumulate (MAC) operation.
  • the CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form.
  • the CIM bit cell circuits also include a true pass-gate circuit and a complement pass-gate circuit for generating a product of the weight data and an activation input on a product node.
  • the product is a not exclusive-OR (XNOR) of the true weight data and the activation input.
  • the CIM bit cell circuits also include an RWL circuit coupled to the product node and a ground voltage rail for initializing the product data.
  • the CIM bit cell circuits also include a plurality of gates that extend in a first axis direction and are separated from each other in a second axis direction orthogonal to the first axis direction.
  • the plurality of gates includes consecutive gates in the second axis direction and each of the consecutive gates is coupled to at least one of the memory bit cell circuit, the hue pass-gate circuit, the complement pass-gate circuit, and the RWL circuit.
  • the respective CIM bit cell circuits operate with increased uniformity, which improves performance and reliability of the CIM array circuit.
  • FIG. 3 is a schematic diagram illustrating a CIM bit cell circuit 300 that executes a binary multiply operation of a true weight data TWD and activation data AD.
  • the activation data AD is used to generate activation data AD(0)-AD(3), which are each provided to the CIM bit cell circuit 300.
  • a binary multiply for a MAC operation is executed by the CIM bit cell circuit 300 and a product data PD is provided to a read bit line RBL.
  • a plurality of the CIM bit cell circuits 300 (not shown) generate the product data PD that are accumulated on the read bit line RBL as an accumulated result ACC. Increasing uniformity in operation of the respective CIM bit cell circuits 300 increases reliability and performance of the MAC operation.
  • the multiply operation within each CIM bit cell circuit 300 is a Boolean XNOR operation of the true weight data TWD and the activation data AD.
  • the CIM bit cell circuit 300 stores the true weight data TWD at a true output node 302 and stores a complement weight data CWD at a complement output node 304 of a memory bit cell circuit 306.
  • the CIM bit cell circuits 300 generate the product data PD on a product node 308 that is coupled (e.g., capacitively coupled) to the read bit line RBL by a capacitor 310 in response to the activation data AD.
  • the CIM bit cell circuit 300 stores the true weight data TWD in the memory bit cell circuit 306.
  • the memory bit cell circuit 306 includes a true pull-up transistor 312T, a true pull-down transistor 314T, a complement pull-up transistor 312C, and a complement pull-down transistor 314C in a cross-coupled configuration.
  • each of the transistors 312T, 312C, 314T, and 314C are metal-oxide semiconductor (MOS) field effect transistors (FETs) (MOSFETs).
  • MOS metal-oxide semiconductor
  • FETs metal-oxide semiconductor field effect transistors
  • the CIM bit cell circuit 300 is not limited in this regard.
  • the true pull-up transistor 312T is coupled to a supply voltage rail 316.
  • coupling the true pull-up transistor 312T to the supply voltage rail 316 refers to providing an electrical connection or path by way of one or more electrical conductors.
  • the true pull-up transistor 312T receives a supply voltage V DD .
  • the true pull-up transistor 312T is also coupled to the true output node 302.
  • the true pull-down transistor 314T is coupled to the true output node 302 and also to a ground voltage rail 318, which receives a ground voltage V ss .
  • the complement pull-up transistor 312C is coupled to the supply voltage rail 316 and also to the complement output node 304.
  • the complement pull-down transistor 314C is coupled to the complement output node 304 and to the ground voltage rail 318.
  • the true pull-up transistor 312T and the true pull-down transistor 314T are controlled by the complement output node 304, and the complement pull-up transistor 312C and the complement pull-down transistor 314C are controlled by the true output node 302.
  • the product data PD is generated on the product node 308 by a hue pass-gate circuit 320T coupled to the true output node 302 and a complement pass-gate circuit 320C coupled to the complement output node 304.
  • the true pass-gate circuit 320T includes a first true transistor 322P and a second true transistor 322N, both of which are coupled to the true output node 302 and to the product node 308.
  • the complement pass-gate circuit 320C includes a first complement transistor 324P and a second complement transistor 324N, both of which are coupled to the complement output node 304 and to the product node 308.
  • the first true transistor 322P, the second true transistor 322N, the first complement transistor 324P, and the second complement transistor 324N are controlled by the activation data AD(0:3), which are each true or complement versions of the activation data AD being multiplied by the true weight data TWD.
  • the true pass-gate circuit 320T and the complement pass-gate circuit 320C generate a product data PD of the XNOR operation on the product node 308.
  • the activation data AD is provided as a single bit binary value where a binary “1” corresponds to a positive voltage (e.g., 2 volts (V)) and a binary “0” corresponds to ground (e.g., 0 V).
  • the activation data AD is provided in true form as AD(0) and AD(3) and provided in complement form as AD(1) and AD(2).
  • AD(0) and AD(3) are binary “0”
  • AD(1) and AD(2) are binary “1”.
  • the true weight data TWD is passed by the true pass-gate circuit 320T to the product node 308.
  • the complement weight data CWD is passed by the complement pass-gate circuit 320C to the product node 308.
  • the product data PD generated in the CIM bit cell circuit 300 corresponds to the truth table of an XNOR operation in Figure 2 with the inputs being the activation data AD and the true weight data TWD.
  • the capacitor 310 couples the product node 308 to the read bit line RBL. In the context of the capacitor 310, coupling refers to capacitive coupling rather than providing an electrical connection.
  • the product node 308 is also coupled (e.g., by electrical connection over a conductive path) to the ground voltage rail 318 by an RWL circuit 326 that includes an RWL transistor 328.
  • the true weight data TWD is reset/initialized to a known state in response to the read word line RWL being activated in combination with the activation data AD controlling the true and complement pass- gate circuits 320T and 320C.
  • Figure 4A is a top plan view of exemplary CIM bit cell circuits 400(A)-400(D) corresponding to the CIM bit cell circuit 300 illustrated in Figure 3.
  • the CIM bit cell circuits 400(A)-400(D) are disposed in a CIM bit cell array circuit 402 on a semiconductor substrate 404.
  • the CIM bit cell array circuit 402 is also referred to herein as a “CIM array 402”.
  • the CIM bit cell circuits 400(A)-400(D) are disposed in respective orientations OA, OB, OC, and OD of a CIM bit cell circuit layout PL 400 (“CIM cell layout PL 400 ”).
  • Each of the CIM bit cell circuits 400(A)-400(D) includes a memory bit cell circuit 406, corresponding to the memory bit cell circuit 306 in Figure 3, and a product node 408, corresponding to the product node 308.
  • the CIM bit cell circuits 400(A)-400(D) also include a true pass-gate circuit 410T and a complement pass-gate circuit 410C, corresponding to the true and complement pass-gate circuits 320T and 320C in Figure 3.
  • Each of the CIM bit cell circuits 400(A)-400(D) also includes an RWL circuit 412, corresponding to the RWL circuit 326 in Figure 3.
  • the orientations OA-OD of the CIM bit cell circuits 400(A)-400(D) are based on the CIM cell layout PL 400 being flipped with respect to either the X-axis direction or the Y-axis direction, such that relative positions of features of the memory bit cell circuit 406, the true pass-gate circuit 410T, the complement pass-gate circuit 410C, and the RWL circuit 412 remain consistent among the different orientations OA-OD with respect to distances and relative locations.
  • the orientation OA of the CIM bit cell circuit 400(A) mirrors the orientation OB of the CIM bit cell circuit 400(B) on an opposite side of a line LY 400 in the Y-axis direction.
  • the orientation OB corresponds to the orientation OA being flipped over (e.g., like turning a page) across the line LY 400 in the Y-axis direction, which makes the features in the orientation OA symmetric to the features in the orientation OB with respect to the line LY 400 .
  • the orientation OA of the CIM bit cell circuit 400(A) mirrors the orientation OC of the CIM bit cell circuit 400(C) with respect to a line LX 400 in the X-axis direction and the orientation OD is a mirror image of the orientation OB with respect to the line LX 400 .
  • the RWL circuit 412 is in the same relative position in all orientations OA-OD.
  • the memory bit cell circuit 406 includes a true pull-up transistor 414T coupled to a supply voltage node 415 and to a true output node 416T.
  • the memory bit cell circuit 406 includes a true pull-down transistor 418T coupled to the true output node 416T and to a ground voltage node 420.
  • the memory bit cell circuit 406 includes a complement pull-up transistor 414C coupled to a supply voltage node 415 and to a complement output node 416C.
  • the memory bit cell circuit 406 also includes a complement pull-down transistor 418C coupled to a ground voltage node 420.
  • the memory bit cell circuit 406 stores a true weight data TWD at the true output node 416T and stores a complement weight data CWD at the complement output node 416C.
  • the supply voltage nodes 415 receive the supply voltage V DD from a supply voltage rail (not shown).
  • the ground voltage nodes 420 receive the ground voltage Vss from a ground voltage rail (not shown).
  • the true pass-gate circuit 410T includes a first true transistor 426P and a second true transistor 426N that are both coupled to the true output node 416T and a product node PN.
  • the complement pass-gate circuit 410C includes a first complement transistor 428P and a second complement transistor 428N that are both coupled to the complement output node 416C and to the product node PN.
  • the RWL circuit 412 includes an RWL transistor 422 coupled to the ground voltage node 420 and the product node PN.
  • the RWL transistor 422 is coupled to the product node PN in each of the CIM bit cell circuits 400(A)-400(D) by a metal trace MTL (e.g., in a second metal layer), which couples the RWL transistor 422 to a central point PCTR of the product node PN.
  • the metal trace MTL. is shown only in the CIM bit cell circuit 400(A).
  • the first true transistor 426P and the second true transistor 426N couple the true output node 416T to the product node PN based on an activation data AD, which is a single binary data bit.
  • the activation data AD is provided in true and complement forms as AD(0)-AD(3) and is hereinafter referred to as AD(0)-AD(3).
  • the first true transistor 426P and the second true transistor 426N are different types of transistors (e.g., P-type FET (PFET) and N-type FET (NFET), respectively) and receive the activation data AD(0) and AD(1), respectively, which are of opposite polarities, such that the true output node 416T is coupled to the product node PN based on the activation data AD(0) being a first polarity and the activation data AD(1) being a second polarity.
  • the first complement transistor 428P and the second complement transistor 428N also couple the complement output node 416C to the product node PN based on the activation data AD(2) and AD(3).
  • the first complement transistor 428P and the second complement transistor 428N are also different types of transistors and receive the activation data AD(2) and AD(3) which cause the complement output node 416C to be coupled to the product node PN based on the activation data AD(2) being a first polarity and AD(3) being a second polarity.
  • a product voltage PV supplied to the product node PN by the true and complement pass-gate circuits 410T and 410C corresponds to an XNOR of the true weight data TWD and the activation data AD.
  • the CIM cell layout PL 400 includes a P- type diffusion region 430P and an N-type diffusion region 430N.
  • the P-type diffusion region 430P is an uninterrupted area of the semiconductor substrate 404 (see Figure 4A) that is continuously doped with a trivalent impurity (e.g., boron, gallium, indium, etc.)
  • the N-type diffusion region 430N is an uninterrupted area of the semiconductor substrate 404 that is continuously doped with a pentavalent impurity (e.g., phosphorous, arsenic, antimony, etc.).
  • the true pull-up transistor 414T, the complement pull-up transistor 414C, the first true transistor 426P, and the first complement transistor 428P are all PFETs disposed in the P-type diffusion region 430P.
  • the true pull-up transistor 414T, the complement pull-up transistor 414C, the first true transistor 426P, and the first complement transistor 428P include respective portions 432P of the P-type diffusion region 430P.
  • the true pull-down transistor 418T, the complement pull-down transistor 418C, the second true transistor 426N, the second complement transistor 428N, and the RWL transistor 422 are all NFETs disposed in the N-type diffusion region 430N and include respective portions 432N of the N-type diffusion region 430N.
  • Figure 4B also shows metal traces 434 (e.g., in a first metal level) interconnecting the respective transistors of the memory bit cell circuit 406, the true pass- gate circuit 410T, the complement pass-gate circuit 410C, and the RWL transistor 422.
  • Figure 4B also shows gates 436(1)-436(5) extending in the Y-axis direction in CIM bit cell circuit 400(A).
  • the gates 436(l)-436(5) are separated from each other according to a gate pitch P GATE measured from center to center of the gates 436(l)-436(5) in the X- axis direction.
  • the X-axis direction is orthogonal to the Y-axis direction.
  • the gates 436(l)-436(5) are five (5) consecutive gates (i.e., consecutive in the X-axis direction). Each of the consecutive gates 436(l)-436(5) is coupled to at least one transistor in each of the memory bit cell circuit 406, the true pass-gate circuit 41 OT, the complement pass-gate circuit 410C, and the RWL circuit 412.
  • each of the consecutive gates 436(l)-436(5) is coupled to and control s at least one of the true pull -up transistor 414T, the true pull-down transistor 418T, the complement pull-up transistor 414C, the complement pud-down transistor 418C, the first true transistor 426P, the second true transistor 426N, the first complement transistor 428P, the second complement transistor 428N, and the RWL transistor 422.
  • the gate 436(1) is coupled to the RWL transistor 422 in CIM bit cell circuit 400(A) and a next one (i.e., gate 436(2)) of the consecutive gates 436(1)- 436(5) is coupled to the true pull-up transistor 414T and the true pull-down transistor 418T.
  • the gate 436(3) is coupled to both the first true transistor 426P and the second true transistor 426N of the true pass-gate circuit 410T.
  • the gate 436(3) is electrically split into a first portion 436(3A) coupled to the first true transistor 426P and a second portion 436(3B) coupled to the second true transistor 426N.
  • the first true transistor 426P and the second true transistor 426N are activated in unison in the true pass-gate circuit 410T with opposite voltage polarities on the first and second portions 436(3A) and 436(3B).
  • the gate 436(4) is coupled to the first complement transistor 428P and the second complement transistor 428N of the complement pass-gate circuit 410C.
  • the gate 436(4) is electrically split into a first portion 436(4A) coupled to the first complement transistor 428P and a second portion 436(4B) coupled to the second complement transistor 428N.
  • the first complement transistor 428P and the second complement transistor 428N are activated in unison with opposite voltage polarities on the first and second portions 436(4A) and 436(4B).
  • the gate 436(5) is coupled to the complement pull-up transistor 414C and the complement pull-down transistor 418C.
  • the RWL transistor 422 is a distance D RWL from a central point P CTR of the product node PN and the metal trace MTL couples (electrically) the RWL transistor 422 to the product node PN in the CIM bit cell circuit 400(A).
  • the metal trace MTL extends the distance D RWL , which is less than four times (i.e., ⁇ 4X) the gate pitch P GATE of the gates 436(l)-436(5), in the X-axis direction.
  • the gate pitch P GATE is a center-to-center distance of the consecutive gates 436(1)-436(5) in the X-axis direction.
  • the metal trace MTL extends the distance D RWL in each of the CIM bit cell circuits 400(A) -400(D). Resistance of the metal trace MTL is based on the distance D RWL in each of the CIM bit cell circuits 400(A)- 400(D). As a result of such symmetry, variation of a current ID RWL in the metal trace MTL., between the product node PN and the RWL transistor 422 to reset/initialize the product node PN, is minimized among the CIM bit cell circuits 400(A) -400(D).
  • FIG 5 is a schematic diagram illustrating an example of a CIM sub-array circuit 500 including a row 502 of three (3) of the CIM bit cell circuits 300 in Figure 3 coupled to a read bit line RBL.
  • the product data PD of each of the respective CIM bit cell circuits 300 is accumulated on the read bit line RBL in a MAC operation.
  • the CIM sub-array circuit 500 is an example showing how a plurality of the CIM bit cell circuits 300 are interconnected in an array (not shown).
  • Figure 5 is provided to show that, in addition to the read bit line RBL being coupled to all of the CIM bit cell circuits 300, the read word line RWL is also coupled to all of the CIM bit cell circuits 300 in the sub-array circuit 500 to allow the CIM bit cell circuits 300 in the row 502 to be reset/initialized by activation of the read word line RWL in combination with the activation data AD controlling the true and complement pass-gate circuits 320T and 320C.
  • Figure 6 is a top plan view of a physical layout 600 of a sub-array 602 corresponding to the CIM sub-array circuit 500 in Figure 5.
  • the sub-array 602 includes CIM CELL(O), CIM CELL(l), and CIM CELL(2) disposed in a row 603 in the X-axis direction.
  • the sub-array 602 also includes an RWL circuit 604.
  • Features of the CIM CELL(0)-CIM CELL(2) and the RWL circuit 604 corresponding to those of the CIM bit cell circuits 300 in Figure 3 are referred to by the same labels in Figure 6 as used in Figure 3.
  • Each of the CIM CELL(0)-CIM CELL(2) are similar to the CIM bit cell circuits 300 shown in Figure 3.
  • the RWL transistors 328 of the CIM CELL(0)- CIM CELL(2) are separated from the CIM CELL(0)-CIM CELL(2) and grouped together in the RWL circuit 604 because the RWL transistors 328 are controlled by the read word line RWL provided on a same gate 606,
  • the RWL transistors 328 are disposed in the Y- axis direction, which is the direction gates 608 are disposed in the physical layout 600, so the gate 606 can control all the RWL transistors 328.
  • a plurality of the sub- arrays 602 disposed in the Y-axis direction in a larger array would have the RWL circuits 604 aligned, such that their respective RWL transistors 328 could be activated together by the same gate 606.
  • the physical layout 600 including the RWL circuit 604 may simplify routing the read word line RWL to the RWL transistors 328 of each of the CIM CELL(0)- CIM CELL(2), such layout results in non- symmetric distances D0-D2 from the RWL circuit 604 to the CIM CELL(0)-CIM CELL(2).
  • the distance DO in the X-axis direction from the CIM CELL(0) to the RWL circuit 604 is greater than the distance DI from the CIM CELL.(1) to the RWL. circuit 604, and the distance D I from the CIM CELL(l) to the RWL circuit 604 is greater than the distance D2 from the CIM CELL(2) to the RWL circuit 604.
  • the distances D0-D2 determine the lengths of metal traces (not shown) used to couple the CIM CELL(0)-CIM CELL(2) to the RWL circuit 604 to provide current paths for resetting/initializing the respective product nodes PN. Resistance of a metal trace depends on length, and a current in a metal trace decreases with increased resistance. Thus, due to the greater distance DO, the CIM CELL(0) would have a smaller reset/initialization current than the CIM CELL(2), resulting in a longer reset/initialization time. Thus, a time to reset/initialize all the CIM bit cell circuits 300 in the sub-array 602 is delayed by the CIM CELL(2), which reduces performance of the processor. If the CIM CELL(0) is not allowed sufficient time to reset/initialize, a reset/initialize operation may be unreliable.
  • the physical layout 600 with RWL circuit 604 being separate from the CIM CELL(0)-CIM CELL(2), allows an efficient placement of the RWL transistors 328 and a gate 606, performance and reliability of the reset/initialization operation suffer in the physical layout 600.
  • the CIM array 402 in Figure 4A incorporates the RWL circuits 412 and provides higher performance and reliability than a conventional array having the physical layout 600 in Figure 6.
  • Figure 7 is a layout top view of a CIM bit cell array circuit 700 based on the conventional physical layout 600 in Figure 6.
  • the layout top view in Figure 7 illustrates P-type diffusion regions 702P and N-type diffusion regions 702N of sub-arrays 704(A)- 704(D) that each correspond to the sub-array 602 of Figure 6.
  • the P-type diffusion regions 702P are formed in N-wells 706 that extend in the X-axis direction.
  • N-type diffusion regions 708 for RWL circuits 710(A)-710(D) that correspond to the RWL circuits 604 in Figure 6.
  • the RWL circuits 710(A)-710(D) are associated with respective ones of the sub-arrays 704(A)-704(D).
  • the N-wells 706 are disposed in the X-axis direction but the N-type diffusion regions 708 in the RWL circuits 710(A)-710(D) are disposed in the Y-axis direction to correspond to a direction of a gate 606 (not shown).
  • one N-well 706 extends through both of the sub-arrays 704(C) and 704(D). Due to the N-type diffusion regions 708, the N-wells 706 cannot extend in the X-axis direction farther than two sub-arrays 704 each including the CELL(0)-CIM CELL(2) or a total of six (6) CIM CELLS in the X-axis direction. N-well ties 712 are, therefore, placed every two (2) sub- arrays 704 in the X-axis direction.
  • Figure 8 is a layout top view of an exemplary CIM bit cell array circuit 800 of CIM bit cell circuits 802 based on the exemplary CIM bit cell circuits 400(A)-400(D) in Figure 4A.
  • the layout top view in Figure 8 illustrates P-type diffusion regions 804P and N-type diffusion regions 804N corresponding to the P-type and N-type diffusion regions 430P and 430N, respectively, in the CIM array 402 in Figure 4A.
  • the RWL circuit 412 is incorporated into the CIM cell layout PL 400 by including the RWL transistor 422 into the N-type diffusion region 430N with the true pull-down transistor 418T, the complement pull-down transistor 418C, the second true transistor 426N, and the second complement transistor 428N.
  • N-well 806 continues uninterrupted in the X-axis direction through a plurality of consecutive CIM bit cell circuits 802.
  • the N-well 806 includes the P-type diffusion regions 430P of seven (7) or more of the CIM bit cell circuits 400 disposed consecutively in the X-axis direction.
  • Figure 9 is a layout top view illustrating another view of an exemplary CIM bit cell array circuit 900 corresponding to the CIM bit cell array 800 in Figure 8.
  • Figure 9 shows P-type diffusion regions 902P(A)-902P(D), in a plurality of CIM bit cell circuits 904(0)-904(7), that each correspond to the CIM bit cell circuits 400(A)-400(D) in the CIM array 402 in Figure 4A.
  • Figure 9 also shows N-type diffusion regions 902N(A)- 902N(D) in the CIM bit cell circuits 904(0)-904(7).
  • Figure 9 shows metal trace 906 coupled to the supply voltage rail (not shown) for providing the supply voltage VDD to the CIM bit cell circuits 904(0)- 904(7) disposed in an X-axis direction.
  • Figure 9 also shows metal trace 908 disposed in an X-axis direction and coupled to the ground voltage rail (not shown) for providing the ground voltage Vss to the CIM bit cell circuits 904(0)-904(7).
  • Figure 9 also shows metal trace 910 disposed in an X-axis direction for providing the read word line RWL to the CIM bit cell circuits 904(0)-904(7).
  • the metal traces 906, 908, and 910 may extend uninterrupted for more than six (6) of the CIM bit cell circuits 904(0)-904(7).
  • the metal trace 906 is coupled to at least seven (7) of the CIM bit cell circuits 904(0)-904(7) disposed consecutively in the X-axis direction and is configured to provide the supply voltage VDD to the at least seven (7) of the CIM bit cell circuits 904(0)-904(7).
  • FIGS. 10A and 10B are a flowchart 1000 illustrating a method of fabricating a CIM bit cell array circuit 402 comprising a plurality of CIM bit cell circuits 400 on a semiconductor substrate 404. The method includes forming a P-type diffusion region 430P and an N-type diffusion region 430N in the semiconductor substrate 404 (block 1002).
  • the method includes forming a memory bit cell circuit 406 comprising a true pull- up transistor 414T coupled to a supply voltage node 415 and a true output node 416T, a true pull-down transistor 418T coupled to the true output node 416T and a ground voltage node 420, a complement pull-up transistor 414C coupled to the supply voltage node 415 and a complement output node 416C, and a complement pull-down transistor 418C coupled to the complement output node 416C and the ground voltage node 420 (block 1004).
  • the method comprises forming a true pass-gate circuit 410T comprising a first true transistor 426P coupled to the true output node 416T and the product node PN, and a second true transistor 426N coupled to the true output node 416T and the product node PN (block 1006).
  • the method comprises forming a complement pass-gate circuit 410C comprising a first complement transistor 428P coupled to the complement output node 416C and the product node PN, and a second complement transistor 428N coupled to the complement output node 416C and the product node PN (block 1008).
  • the method comprises forming an RWL circuit 412 comprising an RWL transistor 422 coupled to the ground voltage node 420 and the product node PN (block 1010).
  • the method further comprises forming a plurality of gates 436(1 )-436(5) extending in a first axis direction and separated from each other in a second axis direction orthogonal to the first axis direction, wherein the plurality of gates 436(l)-436(5) comprises consecutive gates 436(1 )-436(5) in the second axis direction, and each of the consecutive gates 436(1)- 436(5) is coupled to at least one of the memory bit cell circuit 406, the true pass-gate circuit 410T, the complement pass-gate circuit 410C, and the RWL circuit 412 (block 1012).
  • FIG 11 illustrates an exemplary wireless communications device 1100 that includes radio frequency (RF) components formed from one or more integrated circuits (ICs) 1102, wherein any of the ICs 1102 can include an exemplary CIM bit cell array circuit including CIM bit cell circuits each including a read word line circuit and each disposed in an orientation of a CIM bit cell circuit layout to increase uniformity for improved CIM bit cell array circuit performance and reliability, as illustrated in any of Figures 4A, 4B, 8 and 9, and according to any of the aspects disclosed herein.
  • the wireless communications device 1100 may include or be provided in any of the above- referenced devices, as examples. As shown in Figure 11 , the wireless communications device 1100 includes a transceiver 1104 and a data processor 1106.
  • the data processor 1106 may include a memory to store data and program codes.
  • the transceiver 1104 includes a transmitter 1108 and a receiver 1110 that support bi-directional communications.
  • the wireless communications device 1100 may include any number of transmitters 1108 and/or receivers 1110 for any number of communication systems and frequency bands. All or a portion of the transceiver 1104 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.
  • the transmitter 1108 or the receiver 1110 may be implemented with a super- heterodyne architecture or a direct-conversion architecture.
  • a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage.
  • IF intermediate frequency
  • the direct-conversion architecture a signal is frequency-converted between RF and baseband in one stage.
  • the super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements.
  • the transmitter 1108 and the receiver 1110 are implemented with the direct-conversion architecture.
  • the data processor 1106 processes data to be transmitted and provides I and Q analog output signals to the transmitter 1108.
  • the data processor 1106 includes digital-to-analog converters (DACs) 1112(1), 1112(2) for converting digital signals generated by the data processor 1106 into the I and Q analog output signals, e.g., I and Q output currents, for further processing.
  • DACs digital-to-analog converters
  • lowpass filters 1114(1), 1114(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion.
  • Amplifiers (AMPs) 1116(1), 1116(2) amplify the signals from the lowpass filters 1114(1), 1114(2), respectively, and provide I and Q baseband signals.
  • An upconverter 1118 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 1122 through mixers 1120(1), 1120(2) to provide an upconverted signal 1124.
  • TX transmit
  • LO local oscillator
  • a filter 1126 filters the upconverted signal 1124 to remove undesired signals caused by the frequency upconversion as well as noise in a receive frequency band.
  • a power amplifier (PA) 1128 amplifies the upconverted signal 1124 from the filter 1126 to obtain the desired output power level and provides a transmit RF signal.
  • the transmit RF signal is routed through a duplexer or switch 1130 and transmitted via an antenna 1132.
  • the antenna 1132 receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch 1130 and provided to a low noise amplifier (LNA) 1134.
  • LNA low noise amplifier
  • the duplexer or switch 1130 is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals.
  • the received RF signal is amplified by the LNA 1134 and filtered by a filter 1136 to obtain a desired RF input signal.
  • Downconversion mixers 1138(1), 1138(2) mix the output of the filter 1136 with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator 1140 to generate I and Q baseband signals.
  • the I and Q baseband signals are amplified by AMPs 1142(1), 1142(2) and further filtered by lowpass filters 1144(1), 1144(2) to obtain 1 and Q analog input signals, which are provided to the data processor 1106.
  • the data processor 1106 includes analog-to-digital converters (ADCs) 1146(1), 1146(2) for converting the analog input signals into digital signals to be further processed by the data processor 1106.
  • ADCs analog-to-digital converters
  • the TX LO signal generator 1122 generates the I and Q TX LO signals used for frequency upconversion, while the RX L.0 signal generator 1140 generates the 1 and Q RX LO signals used for frequency downconversion.
  • Each LO signal is a periodic signal with a particular fundamental frequency.
  • a TX phase-locked loop (PLL) circuit 1148 receives timing information from the data processor 1 106 and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TX LO signal generator 1122.
  • an RX PLL circuit 1150 receives timing information from the data processor 1106 and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RX LO signal generator 1140.
  • Wireless communications devices 1100 that each include an exemplary CIM bit cell array circuit including CIM bit cell circuits each including a read word line circuit and each disposed in an orientation of a CIM bit cell circuit layout to increase uniformity for improved CIM bit cell array circuit performance and reliability, as illustrated in any of Figures 4A, 4B, 8, and 9, and according to any of the aspects disclosed herein, may be provided in or integrated into any processor-based device.
  • Figure 12 illustrates an example of a processor-based system 1200 including an exemplary CIM bit cell array circuit including CIM bit cell circuits each including a read word line circuit and each disposed in an orientation of a CIM bit cell circuit layout to increase uniformity for improved CIM bit cell array circuit performance and reliability, as illustrated in any of Figures 4A, 4B, 8, and 9, and according to any aspects disclosed herein.
  • the processor-based system 1200 includes one or more central processor units (CPUs) 1202, which may also be referred to as CPU or processor cores, each including one or more processors 1204.
  • the CPU(s) 1202 may have cache memory 1206 coupled to the processors) 1204 for rapid access to temporarily stored data.
  • the processor(s) 1204 could include an exemplary CIM bit cell array circuit including CIM bit cell circuits each including a read word line circuit and each disposed in an orientation of a CIM bit cell circuit layout to increase uniformity for improved CIM bit cell array circuit performance and reliability, as illustrated in any of Figures 4A, 4B, 8, and 9, and according to any aspects disclosed herein.
  • the CPU(s) 1202 is coupled to a system bus 1208 and can intercouple master and slave devices included in the processor-based system 1200. As is well known, the CPU(s) 1202 communicates with these other devices by exchanging address, control, and data information over the system bus 1208. For example, the CPU(s) 1202 can communicate bus transaction requests to a memory controller 1210 as an example of a slave device. Although not illustrated in Figure 12, multiple system buses 1208 could be provided, wherein each system bus 1208 constitutes a different fabric.
  • Other master and slave devices can be connected to the system bus 1208. As illustrated in Figure 12, these devices can include a memory system 1212 that includes the memory controller 1210 and one or more memory arrays 1214, one or more input devices 1216, one or more output devices 1218, one or more network interface devices 1220, and one or more display controllers 1222, as examples.
  • Each of the memory system 1212, the one or more input devices 1216, the one or more output devices 1218, the one or more network interface devices 1220, and the one or more display controllers 1222 can include an exemplary CIM bit cell array circuit including CIM bit cell circuits each including a read word line circuit and each disposed in an orientation of a CIM bit cell circuit layout to increase uniformity for improved CIM bit cell array circuit performance and reliability, as illustrated in any of Figures 4A, 4B, 8, and 9, and according to any of the aspects disclosed herein.
  • the input device(s) 1216 can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc.
  • the output device(s) 1218 can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc.
  • the network interface device(s) 1220 can be any device configured to allow exchange of data to and from a network 1224.
  • the network 1224 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTHTM network, and the Internet.
  • the network interface device(s) 1220 can be configured to support any type of communications protocol desired.
  • the CPU(s) 1202 may also be configured to access the display controller(s) 1222 over the system bus 1208 to control information sent to one or more displays 1226.
  • the display controllers) 1222 sends information to the display(s) 1226 to be displayed via one or more video processors 1228, which process the information to be displayed into a format suitable for the display(s) 1226.
  • the display(s) 1226 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
  • the display controllers) 1222, display(s) 1226, and/or the video processor(s) 1228 can include an exemplary CIM bit cell array circuit including CIM bit cell circuits each including a read word line circuit and each disposed in an orientation of a CIM bit cell circuit layout to increase uniformity for improved CIM bit cell array circuit performance and reliability, as illustrated in any of Figures 4A, 4B, 8, and 9, and according to any of the aspects disclosed herein.
  • Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both.
  • the master and slave devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples.
  • Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired.
  • Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine, A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
  • a processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
  • RAM Random Access Memory
  • ROM Read Only Memory
  • EPROM Electrically Programmable ROM
  • EEPROM Electrically Erasable Programmable ROM
  • registers a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in a remote station.
  • the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
  • a compute-in-memory (CIM) bit cell circuit comprising: a memory bit cell circuit comprising: a true pull-up transistor coupled to a supply voltage rail and a true output node; a true pull-down transistor coupled to the true output node and a ground voltage rail; a complement pull-up transistor coupled to the supply voltage rail and a complement output node; and a complement pull-down transistor coupled to the complement output node and the ground voltage rail; a true pass-gate circuit comprising: a first true transistor coupled to the true output node and a product node; and a second true transistor coupled to the true output node and the product node; a complement pass-gate circuit comprising: a first complement transistor coupled to the complement output node and the product node; and a second complement transistor coupled to the complement output node and the product node; a read word line (RWL) circuit comprising an RWL transistor coupled to the ground voltage rail and the product node
  • each of the consecutive gates is coupled to at least one of the true pull-up transistor, the true pull-down transistor, the complement pull-up transistor, the complement pull-down transistor, the first true transistor, the second true transistor, the first complement transistor, the second complement transistor, and the RWL transistor.
  • one of the plurality of gates coupled to the RWL transistor is a next consecutive gate to one of the plurality of gates coupled to the true pull-up transistor and the true pull-down transistor.
  • XNOR exclusive-OR
  • a compute-in-memory (CIM) bit cell circuit comprising: a semiconductor substrate; a P-type diffusion region in the semiconductor substrate; an N-type diffusion region in the semiconductor substrate; a memory bit cell circuit comprising: a true pull-up transistor coupled to a supply voltage rail and a true output node; a true pull-down transistor coupled to a ground voltage rail and the true output node; a complement pull-up transistor coupled to the supply voltage rail and a complement output node; and a complement pull-down transistor coupled to the ground voltage rail and the complement output node; a true pass-gate circuit comprising: a first true transistor coupled to the true output node and a product node; and a second true transistor coupled to the true output node and the product node; a complement pass-gate circuit comprising: a first complement transistor coupled to the complement output node and the product node; and a second complement transistor coupled to the complement output node and the product node; and a read word line (RWL) transistor coupled to the product node and the
  • each of the true pull-up transistor, the complement pull-up transistor, the second true transistor, and the second complement transistor comprises a portion of the P-type diffusion region.
  • the memory bit cell circuit is configured to store a true voltage corresponding to a true weight data on the true output node; at least one of the first true transistor and the second true transistor of the true pass-gate circuit and at least one of the first complement transistor and the second complement transistor of the complement pass-gate circuit receive a voltage based on an activation data; and a product voltage supplied to the product node corresponds to a not exclusive-OR (XNOR) of the true weight data and the activation data.
  • XNOR exclusive-OR
  • a compute-in-memory (CIM) bit cell array circuit comprising: a semiconductor substrate; and a plurality of CIM bit cell circuits on the semiconductor substrate, each of the plurality of CIM bit cell circuits comprising: a P-type diffusion region disposed in the semiconductor substrate; an N-type diffusion region disposed in the semiconductor substrate; a memory bit cell circuit comprising: a true pull-up transistor coupled to a supply voltage rail and a true output node; a true pull-down transistor coupled to the true output node and a ground voltage rail; a complement pull-up transistor coupled to the supply voltage rail and a complement output node; and a complement pull-down transistor coupled to the complement output node and the ground voltage rail; a true pass-gate circuit comprising: a first true transistor coupled to the true output node and a product node; and a second true transistor coupled to the true output node and the product node; a complement pass-gate circuit comprising: a first complement transistor coupled to the complement output node and the product node;
  • the memory bit cell circuit is configured to store a true voltage corresponding to a true weight data on the true output node: at least one of the plurality of gates coupled to the true pass-gate circuit and at least one of the plurality of gates coupled to the complement pass-gate circuit receive a voltage based on an activation data; and a product voltage supplied to the product node corresponds to a not exclusive-OR (XNOR) of the true weight data and the activation data.
  • XNOR exclusive-OR
  • the CIM bit cell array circuit of clause 12 or 13, wherein: a third one of the plurality of CIM bit cell circuits mirrors the second one of the plurality of CIM bit cell circuits on an opposite side of a second line extending in the first axis direction.
  • an N-well region comprises the P-type diffusion regions of at least seven (7) of the plurality of CIM bit cell circuits disposed consecutively in the second axis direction.
  • GPS global
  • a method of making a compute-in-memory (CIM) bit cell array circuit comprising a plurality of CIM bit cell circuits on a semiconductor substrate, the method comprising: forming a P-type diffusion region and an N-type diffusion region in the semiconductor substrate; forming a memory bit cell circuit comprising: a true pull-up transistor coupled to a supply voltage rail and a true output node; a true pull-down transistor coupled to the true output node and a ground voltage rail; a complement pull-up transistor coupled to the supply voltage rail and a complement output node; and a complement pull-down transistor coupled to the complement output node and the ground voltage rail; forming a true pass-gate circuit comprising: a first true transistor coupled to the true output node and a product node; and a second true transistor coupled to the true output node and the product node; forming a complement pass-gate circuit comprising: a first complement transistor coupled to the complement output node and the product node; and a second complement transistor coupled to the complement output

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  • Static Random-Access Memory (AREA)

Abstract

Des circuits de réseau de cellules binaires de calcul en mémoire (CIM) comprennent des circuits de cellules binaires CIM pour des opérations de multiplication-accumulation. Les circuits de cellules binaires CIM comprennent un circuit de cellules binaires de mémoire pour stocker des données de poids sous une forme véritable et complémentaire. Les circuits de cellules binaires CIM comprennent un circuit de grille passante véritable et un circuit de grille passante complémentaire pour générer un produit binaire des données de poids et une entrée d'activation sur un nœud de produit. Un circuit RWL accouple le nœud de produit à une tension de mise à la terre pour l'initialisation. Les circuits de cellules binaires CIM comprennent également une pluralité de grilles consécutives accouplées chacune au circuit de cellules binaires de mémoire et/ou au circuit de grille passante véritable et/ou au circuit de grille passante complémentaire et/ou au circuit RWL. Chacun des circuits de cellules binaires CIM dans le circuit de réseau de cellules binaires CIM est placé dans une orientation d'un agencement de circuit de cellules binaires CIM comprenant le circuit RWL.
EP21801308.4A 2020-12-02 2021-09-30 Circuits de cellule binaire de calcul en mémoire (cim) placés chacun dans une orientation d'un agencement de circuit de cellule binaire cim comprenant un circuit de ligne de mots de lecture (rwl) dans un circuit de réseau de cellules binaires cim Pending EP4256611A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202063120582P 2020-12-02 2020-12-02
US17/404,378 US11626156B2 (en) 2020-12-02 2021-08-17 Compute-in-memory (CIM) bit cell circuits each disposed in an orientation of a cim bit cell circuit layout including a read word line (RWL) circuit in a cim bit cell array circuit
PCT/US2021/052871 WO2022119627A1 (fr) 2020-12-02 2021-09-30 Circuits de cellule binaire de calcul en mémoire (cim) placés chacun dans une orientation d'un agencement de circuit de cellule binaire cim comprenant un circuit de ligne de mots de lecture (rwl) dans un circuit de réseau de cellules binaires cim

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EP4256611A1 true EP4256611A1 (fr) 2023-10-11

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EP21801308.4A Pending EP4256611A1 (fr) 2020-12-02 2021-09-30 Circuits de cellule binaire de calcul en mémoire (cim) placés chacun dans une orientation d'un agencement de circuit de cellule binaire cim comprenant un circuit de ligne de mots de lecture (rwl) dans un circuit de réseau de cellules binaires cim

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EP (1) EP4256611A1 (fr)
TW (1) TW202223887A (fr)
WO (1) WO2022119627A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11263522B2 (en) * 2017-09-08 2022-03-01 Analog Devices, Inc. Analog switched-capacitor neural network
WO2019246064A1 (fr) * 2018-06-18 2019-12-26 The Trustees Of Princeton University Moteur de calcul en mémoire configurable, plateforme, cellules binaires et agencements associés

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TW202223887A (zh) 2022-06-16

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