EP4199352A1 - Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance - Google Patents

Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance Download PDF

Info

Publication number
EP4199352A1
EP4199352A1 EP21214440.6A EP21214440A EP4199352A1 EP 4199352 A1 EP4199352 A1 EP 4199352A1 EP 21214440 A EP21214440 A EP 21214440A EP 4199352 A1 EP4199352 A1 EP 4199352A1
Authority
EP
European Patent Office
Prior art keywords
voltage
input
output
circuit
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21214440.6A
Other languages
German (de)
English (en)
Inventor
Mike Hendrikus Splithof
Marco Berkhout
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Goodix Technology Hong Kong Co Ltd
Original Assignee
Goodix Technology Hong Kong Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goodix Technology Hong Kong Co Ltd filed Critical Goodix Technology Hong Kong Co Ltd
Priority to EP21214440.6A priority Critical patent/EP4199352A1/fr
Priority to CN202210513372.9A priority patent/CN114900136A/zh
Priority to PCT/CN2022/138398 priority patent/WO2023109760A1/fr
Publication of EP4199352A1 publication Critical patent/EP4199352A1/fr
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H03F3/45641—Measuring at the loading circuit of the differential amplifier
    • H03F3/45645—Controlling the input circuit of the differential amplifier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H04R3/007—Protection circuits for transducers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/462—Indexing scheme relating to amplifiers the current being sensed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21161—An output signal dependant signal being measured by current measuring at the output of a power amplifier

Definitions

  • the invention relates to a voltage sense circuit for measuring a load connected to a power amplifier.
  • the invention further relates to a current sense circuit for measuring a load connected to a power amplifier and to a method of operating the voltage and current sense circuits to measure a load connected to a power amplifier.
  • a typical configuration for the output stage of a power amplifier is the bridge-tied load (BTL), which is shown in fig. 1A and in which both sides of a load, such as a loudspeaker, are being driven by two outputs in opposite phase. In this way, the current through the load can flow in two opposite directions.
  • the power amplifier is operated in class-D, which means that the output transistors are switched such that the output voltages are modulated square waves with a typical fundamental frequency around 500 Kilohertz's. Ferrite beads or inductors may be placed between the actual amplifier outputs and the speaker to reduce electromagnetic emission and/or to filter the high-frequency residue due to modulation.
  • the impedance of the load connected to the power amplifier may be desired to measure the impedance of the load connected to the power amplifier. This can be achieved by simultaneously measuring the voltage across the load and the current through the load.
  • speaker protection can be provided as the impedance of a speaker provides information about its voice coil temperature, which, in turn, is a measure for the excursion of the speaker membrane as disclosed in " A 4 ⁇ 2.65W Class-D Audio Amplifier with Embedded DC-DC Boost Converter, Current Sensing ADC and DSP for adaptive speaker protection", by Marco Berkhout, Lûtsen Dooper and Benno Krabbenborg, in IEEE Journal of Solid-State Circuits, Vol 48, No 12, pp.2952-2961, 2013 .
  • the measured voltage and current are typically converted to a digital value, which allows further signal processing in the digital domain.
  • Sigma-delta data converters provide a very cost-effective solution for this.
  • Measuring the voltage across the load can be achieved by observing the difference between the voltages V SP and V SN at both sides of the load as shown in fig. IB. However, the measurement of said voltage is affected by the large common mode voltage swing that appears on the output nodes of the amplifier.
  • Measuring the current through the load can be accomplished by adding a known measurement resistor R SENSE in series with the load, as shown in fig. 1C , and by measuring the differential voltage across said known measurement resistor.
  • the impedance of the measurement resistor shall be small compared to the load, typically in the order of 1% of the load or smaller. If the measurement resistor is placed between the outputs of the amplifier and the load, the measurement resistor will experience the same common mode voltage swing as the load, but the differential signal to be observed is much smaller than the voltage across the load. In other words, the common mode rejection requirements for the current interface circuitry will be extremely challenging if this sensing scheme is adopted. This will be at the expense of chip area and/or current consumption.
  • the measurement resistor(s) can be placed at a different location in the current path.
  • a popular solution is to place two measurement resistors in series with the sources of the low-side output transistors as shown in fig. ID. Since one leg of each resistor is grounded, the common mode issue is adequately tackled in this way. As far as the AD modulation scheme is concerned, there are two possible circuit states:
  • Figure 1G shows a current interface, which is a part of the invention, and whose task it is to combine four sense voltages V HSN , V HSP , V LSP and V LSN into a signal that can be handled by the ADC.
  • a fully Integrated Class-D Amplifier in 40nm CMOS with Dynamic Cascode Bias and Load Current Sensing discloses an implementation of a current interface as shown in fig. 1 H .
  • the operation of this circuit is briefly as follows.
  • the output transistors of the bridge have sense resistors in series with their sources (R 1HP , R 1HN , R 1LP , R 1LN ).
  • a total of four local amplifiers together with resistors R 2HP etc. are configured as VI converters to actively generate scaled copies of the sensed currents.
  • OffsetHP etc Deliberately added offset sources (called OffsetHP etc7) shall take care that the currents through R2HP etc. will not change polarity, even when the current through R1HP etc. changes direction. Via additional current mirrors, four scaled currents (two per bridge-half) are subsequently summed in the current domain and will leave the circuit at nodes I OUTP and I OUTN .
  • the differential voltage across the load can become as large as the supply voltage of the power stage. This is generally much too large to be handled by an Analog to Digital converter (ADC) that might be attached to V OP and V on . Therefore, the voltage interface must also incorporate attenuation. Also, the supply voltage of the output stage is often modulated with the (audio) signal to further increase efficiency (class-DG operation). This implies that the common mode voltage will vary along with the audio signal. Additionally, due to the class-D operation, the output common mode voltage contains large high-frequency components. Therefore, common mode rejection is an important requirement for the voltage interface. Finally, the output common mode voltage level of the voltage interface shall fit conveniently between the supply rails of the ADC.
  • a known technique for rejecting common mode in an amplifier is to use two matched voltage dividers as voltage interface wherein the two matched voltage dividers have zero common mode rejection as shown in fig. 1I .
  • voltage level shifting is required to make the signal suitable for the ADC.
  • this introduces additional noise and distortion.
  • Binet et al "A fully Integrated Class-D Amplifier in 40nm CMOS with Dynamic Cascode Bias and Load Current Sensing", ESSCIRC2014- 40th European Solid-State Circuits Conference discloses a current interface wherein the output transistors of the bridge have sense resistors in series with their sources and a total of four local amplifiers together with the sense resistors are configured as converters to actively generate scaled copies of the sensed currents. Deliberately added offset sources shall take care that the currents through the sense resistors will not change polarity, even when the current through said resistors changes direction.
  • the invention relates to a voltage sense circuit for measuring a load connected to a power amplifier wherein the load is configured to receive a first voltage at a first end and a second voltage at a second end, wherein the first and the second voltages are in opposite phase, wherein the voltage sense circuit comprises a first input terminal coupled to the first voltage, a second input terminal coupled to the second voltage, a first output terminal, a second output terminal, a first voltage divider circuit comprising an input coupled to the first input terminal and an output coupled to the first output terminal, a second voltage divider circuit comprising an input coupled to the second input terminal and an output coupled to the second output terminal and a driver circuit comprising a first input configured to receive a reference voltage, a second input configured to receive a common mode signal of the first and the second voltage divider circuits, and an output configured to drive an output common mode voltage of the first and the second voltage divider circuits with the reference voltage.
  • the second input of the driver circuit may be connected to the output of the driver circuit. This provides a suitable connection that allows rejecting common mode variations.
  • Each of the first and second voltage dividers may comprises a pair of resistors wherein each of the pair of resistors comprises a first end and a second end and wherein the first ends of the pair of resistors may be respectively connected to the first and second output terminals and wherein the second ends of the pair of resistors may be connected to each other.
  • first and second voltage dividers may be implemented using voltage sources or in any other suitable manner.
  • the voltage second input and the output of the driver circuit may be connected to the second ends of the pair of resistors. This is a suitable connection to reject common mode variations. However, the voltage second input and the output of the driver circuit may be coupled to the first and second voltage dividers in any suitable way.
  • the driver circuit may comprise a first and a second resistors connected in series between the first and the second output terminals such that a first end of the first resistor may be coupled to the first output terminal, a second end of the first resistor may be coupled to a first end of the second resistor and a second end of the second resistor may be coupled to the second output terminal, and wherein the second input of the driver circuit may be coupled to the first end of the second resistor.
  • the driver circuit may comprises a first and a second output resistors R 3p -R 3n wherein the first output resistor R 3p may be connected between the first output terminal I op and the first end of the first resistor R 2p and the second output resistor R 3n may be connected between the second output terminal I on and the second end of the second resistor R 2n .
  • the physical quantity that the ADC must handle is current and therefore, the same ADC can be connected to the voltage sense interface and to a current sense interface in order to measure both current and voltage to calculate the load.
  • the output variable of the voltage sense circuit is current. This would be beneficial since both the current and the voltage sense ADCs can be then identical circuits, both converting current to digital.
  • the invention further relates to a current sense circuit for measuring a load connected to a power amplifier wherein the load is configured to receive a first voltage V ip at a first end and a second voltage V in at a second end, wherein the first and the second voltages are in opposite phase, wherein the current sense circuit comprises a first input terminal coupled to the first voltage V HSN , a second input terminal coupled to the second voltage V HSP , a third input terminal coupled to the third voltage V LSN , a fourth input terminal coupled to the fourth voltage V LSP , a first output terminal I op , a second output terminal I on , and a common mode loop circuit comprising a first input, a second input, a third input and an output wherein the first and the second inputs are configured to receive a common mode voltage at the first and second output terminals I op and I on , the third input is configured to receive a reference voltage, and to generate a control signal at the output to switch the current sense circuit such that the common mode voltage equals
  • the current sense circuit may further comprise a differential mode loop circuit comprising a first input and a second input and an output wherein the first and the second inputs are configured to receive a voltage difference and generate a control signal to keep the voltage difference equal to zero.
  • the current sense circuit may comprise a first transistor M 1 comprising a source, a gate and a drain, a second transistor M 2 comprising a source, a gate and a drain, and a first, second, third and fourth conversion resistors comprising a first end and a second end wherein the first end of the first, second, third and fourth conversion resistors are respectively coupled to the first, second, third and fourth input terminals, and the second end of the first resistor is coupled to the first input of the differential mode loop circuit and to the source of the first transistor M 1 , the second end of the second resistor is coupled to the second input of the differential mode loop circuit and to the source of the second transistor M 2 , the second end of the third resistor is coupled to the first input of the common mode loop circuit and to the drain of the first transistor M 1 , the second end of the fourth resistor is coupled to the second input of the common mode loop circuit and to the drain of the second transistor M 2 , and the control signals generated by the common mode loop circuit and the differential mode loop circuit control the gates
  • the invention also relates to a method of operating a -current sense circuit and/or a method of operating a voltage sense circuit.
  • Fig. 2 shows a voltage sense circuit 200 according to a first embodiment of the invention.
  • the voltage sense circuit 200 of fig. 2 comprises a first input terminal 202, a second input terminal 204, a first output terminal 206 and a second output terminal 208.
  • the first input terminal 202 of the voltage sense circuit 200 of fig. 2 is configured to receive a first input voltage V ip
  • the second input terminal 204 is configured to receive a second input voltage V in
  • the first output terminal 206 is configured to provide a first output voltage V op
  • the second output terminal 208 is configured to provide a second output voltage V on .
  • the voltage sense circuit 200 of fig. 2 comprises further a first voltage divider circuit 220 and a second voltage divider circuit 222.
  • the first voltage divider circuit 220 comprises an input and an output wherein the input is coupled to the first input terminal 202 of the voltage sense circuit and the output is coupled to the first output terminal 206.
  • the second voltage divider circuit 222 comprises an input and an output wherein the input is coupled to the second input terminal 204 and the output is coupled to the second output terminal 208.
  • the voltage sense circuit 200 of fig. 2 comprises further a driver circuit 232 wherein the driver circuit 232 comprises a first input 234, a second input 236, and an output 238.
  • the first input 234 of the driver circuit 232 is configured to receive a reference voltage
  • the second input 234 is coupled to the first voltage divider circuit 220 and to the second voltage divider circuit 222 and is configured to receive a common mode signal
  • the output 238 is coupled to the first and the second voltage divider circuits and configured to drive an output common mode voltage of the first and the second voltage divider circuits with the reference voltage.
  • the voltage sense circuit 200 shown in fig. 2 may be used to measure a load connected to a power amplifier wherein the load is configured to receive the first voltage (V ip ) at a first end of the load and the second voltage (V in ) at a second end of the load, wherein the first and the second voltages are in opposite phase.
  • a differential voltage is converted into a current with an amplitude and a common mode voltage level that can be conveniently handled by an ADC thereby rejecting the common mode variations mentioned.
  • the resulting output current can be directly integrated by the first integrator stage of a sigma-delta converter attached.
  • Fig. 3 shows a voltage sense circuit 300 according to a further embodiment of the invention wherein the same reference numbers as in fig. 2 have been used to indicate the same elements.
  • the first voltage divider 220 of fig. 3 comprises a first resistor R 1p and a second resistor R 2p wherein the first resistor R 1p comprises a first end 302 and a second end 304 and the second resistor R 2p comprises a first end 306 and a second end 308.
  • the first end 302 of the first resistor R 1p is connected to the first input terminal 202 of the voltage sense circuit 300
  • the second end 304 of the first resistor R 1p is connected to the first output terminal 206 of the voltage sense circuit 300
  • the second end 308 of the second resistor R 2p is connected to the second input 236 and to the output 238 of the driver circuit 232.
  • the second voltage divider 222 shown in fig. 3 comprises a third resistor R 1n and a fourth resistor R 2n wherein the third resistor R 1n comprises a first end 312 and a second end 314, and the fourth resistor R 2n comprises a first end 316 and a second end 318.
  • the first end 312 of the third resistor R 1n is connected to the second input terminal 204
  • the second end 314 of the third resistor R 1n is connected to the second output terminal 208 of the voltage sense circuit 300 and to the first end 316 of the fourth resistor R 2n
  • the second end 318 of the fourth resistor R 2n is connected to the second output 236 of the driver circuit 232, to the output 238 of the driver circuit 232 and to the second end 308 of the second resistor R 2p.
  • the output common mode voltage of the voltage sense circuit 300 shown in fig. 3 is not so close to ground, which is not convenient for an ADC that might be attached to the first and second output terminals 206 and 208. Furthermore, common mode rejection at the output of the voltage sense circuit 300 is provided.
  • the common ground node between the second end 308 of the second resistor R 2p and the second end 318 of the fourth resistor R 2n could be replaced by a voltage source, or by a buffer that drives this common ground node with a convenient voltage.
  • the first and second outputs V op and V on will be around 0.9 Volts, which is convenient if the ADC is supplied by 1.8 Volts with respect to ground.
  • the first and second outputs V op and V on may have any suitable value.
  • Fig. 4 shows a further embodiment according to the invention wherein the driver circuit 400 further comprises a first resistor R 4p and a second resistor R 4n compare to the driver circuit 232 shown in fig. 3 .
  • the first resistor R 4p comprises a first end 402 and a second end 404.
  • the second resistor R 4n comprises a first end 406 and a second end 408.
  • the first end 402 of the first resistor R 4p of the driver circuit 400 is connected to the first output terminal 206
  • the second end 408 of the second resistor R 4n is connected to the second output terminal 208
  • the second end 404 of the first resistor R 4p is connected to the first end 406 of the second resistor R 4n and to an output 420 of an amplifier 422.
  • Fig. 5 shows a further embodiment according to the invention wherein the driver circuit 510 comprises a first output resistor R 3p and a second output resistor R 3n compared to the driver circuit 400 of fig. 4 .
  • the first output resistor R 3p of the driver circuit 510 comprises a first end 512 and a second end 514 and the second output resistor R 3n of the driver circuit 510 comprises a first end 516 and a second end 518.
  • the second end 514 of the first output resistor R 3p of the driver circuit 510 is connected to the first output terminal 204 and the first end of the first output resistor R 3p of the driver circuit 510 is connected to the first end 402 of the first resistor R 4p .
  • the second end 518 of the second output resistor R 3n of the driver circuit 510 is connected to the second output terminal 208 and the first end 516 of the second output resistor R 3n of the driver circuit 510 is connected to the first end 406 of the second resistor R 4 n.
  • the first output terminal 204 and the second output terminal 206 of the voltage sense circuit of fig. 5 are coupled together.
  • the physical quantity that is handled by an ADC connected to the voltage sense circuit of fig. 5 is a current, as the differential voltages between the first output terminal 204 and the second output terminal 206 deliver a current due to the use of the first output resistor R 3p and a second output resistor R 3n and the coupling of the first and second output terminals.
  • Fig. 6 shows a current sense circuit 600 according to an embodiment of the invention.
  • the current sense circuit 600 comprises a first input terminal 602 coupled to a first voltage V HSN , a second input terminal 604 coupled to the second voltage V HSP , a third input terminal 606 coupled to the third voltage V LSN , a fourth input terminal 608 coupled to a fourth voltage V LSP , a first output terminal I op a second output terminal I on , and a common mode loop circuit 610.
  • the common mode loop circuit 610 comprises a first input 612, a second input 614, a third input 616 and an output 618.
  • the first and the second inputs of the common mode loop circuit 610 are respectively configured to receive a common mode voltage at the first and second output terminals I op and I on .
  • the third inout 616 is configured to receive a reference voltage.
  • the common mode loop circuit 610 is configured to generate a control signal at its output 618 to switch a first transistor M 1 and a second transistor M 2 such that the common mode voltage equals the reference voltage.
  • the current sense circuit 600 further comprises a differential mode loop circuit 630 comprising a first input 632 and a second input 634 and an output 636 wherein the first and the second inputs 632 and 634 are configured to receive a voltage difference such that differential mode loop circuit 630 generates a control signal to control the first transistor M 1 and the second transistor M 2 in order to keep the voltage difference equal to zero.
  • the goal of the current sense interface of fig. 6 is to combine four sense voltages V HSN , V HSP , V LSP and V LSN into one signal that can be processed by the ADC.
  • the high side voltages V HSP and V HSN will vary around a positive supply voltage vddp.
  • the low-side sense voltages V LSP and V LSN will vary around ground level, which is the reference node.
  • the ADC will receive an input current I OUT at a voltage level around half the supply voltage of the ADC. This means that analog voltage level shifting is part of the function.
  • the high-side sense voltages share a common vddp voltage. Some kind of differential amplifier could be used to reject the supply modulations.
  • V HSP , V HSN , V LSP , and V LSN connect to the four sense resistors.
  • V HSP and V HSN will be equal to the voltage of the power stage supply, vddp, and V LSP and V LSN will be equal to ground.
  • the four conversion resistors called R SUM,HSP , R SUM,HSN , R SUM,HLP , and R SUM,HLN are equal.
  • Outputs I OP and I ON are differentially shorted by the first integrator of the sigma-delta loop of the ADC. That implies that any current leaving the I OP node will return via the I ON node.
  • the common mode loop circuit 610 will measure the common mode voltage at nodes I OP and I ON and control the gates of M 1 and M 2 in-phase until the common mode voltage equals an external reference voltage, V REF,CM .
  • V REF,CM an external reference voltage
  • R SUM,LSP and R SUM,LSN are both equal to V REF,CM/ R SUM .
  • These currents will also flow in R SUM,HSP and R SUM,HSN and, as a consequence, the external reference voltage will also drop across those high-side resistors. An additional high-side reference voltage is no longer needed.
  • the differential mode loop circuit 630 will measure the difference between voltage Vsi and voltage V S2 and adjust that difference to zero by controlling the gate voltages of M 1 and M 2 in opposite phase.
  • An advantage of this circuit is that the entire voltage headroom between the common mode output voltage and ground will drop across the four conversion resistors called R SUM,HSP , R SUM,HSN , R SUM,HLP , and R SUM,HLN . This is the optimum situation for noise within a given current budget.
  • Figs. 7 and 8 show implementations of the current sense circuit of fig. 6 using transistors.
  • the only contributors to differential output current noise are resistors and the differential pair.
  • fig. 8 instead of controlling the gates of M 1 and M 2 directly, they are controlled in-phase by adjusting the tail current source of the differential mode loop differential pair.
  • the common-mode loop has become a two-stage amplifier in this way, which increases the loop gain for that loop.
  • Fig. 9 shows a power amplifier 900 comprising a current sense circuit 600 and a voltage sense circuit 200 according to the invention.
  • Fig. 9 also shows an ADC 902 connected at the output of the current sense circuit 600 and the voltage sense circuit 200.
  • Fig. 10 shows a flowchart for a method of operating a voltage sense circuit for measuring a load connected to a power amplifier wherein the load is configured to receive a first voltage V ip at a first end and a second voltage V in at a second end, wherein the first and the second voltages are in opposite phase.
  • the method comprises step 1002 comprising receiving, at an input of a first voltage divider circuit 220 of the voltage sense circuit, the first voltage V ip .
  • step 1004 by receiving, at an input of a second voltage divider circuit 222 of the voltage sense circuit, the second voltage V in .
  • step 1006 the method comprises receiving, at a first input 234 of a driver circuit 232 of the voltage sense circuit, a reference voltage, and receiving, at a second input 236 of the driver circuit 232, a common mode signal from the first and the second voltage divider circuits.
  • step 1008 comprising driving, by the driver circuit, an output common mode voltage of the first and the second voltage divider circuits with the reference voltage.
  • Fig. 11 shows a flowchart for a method of operating a current sense circuit for measuring a load connected to a power amplifier wherein the load is configured to receive a first voltage V ip at a first end and a second voltage V in at a second end, wherein the first and the second voltages are in opposite phase.
  • the method comprises a step 1102 of receiving, at a first input terminal 602, a first voltage V HSN , receiving at a second input terminal 604, a second voltage V HSP , receiving, at a third input terminal 606, a third voltage V LSN and, receiving, at a fourth input terminal 608, a fourth voltage V LSP .
  • the method further comprises a step 1104 of receiving, at first and second inputs of a common mode loop circuit 610, a common mode voltage at an output of the current sense circuit, and receiving, at a third input of the common mode loop circuit 610, a reference voltage.
  • the method comprises a step 1106 of generating, at the output of the common mode loop circuit 610, a control signal 636 to switch the current sense circuit 600 such that the common mode voltage equals the reference voltage
EP21214440.6A 2021-12-14 2021-12-14 Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance Pending EP4199352A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP21214440.6A EP4199352A1 (fr) 2021-12-14 2021-12-14 Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance
CN202210513372.9A CN114900136A (zh) 2021-12-14 2022-05-12 用于测量连接到功率放大器的负载的电压和电流感测电路
PCT/CN2022/138398 WO2023109760A1 (fr) 2021-12-14 2022-12-12 Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP21214440.6A EP4199352A1 (fr) 2021-12-14 2021-12-14 Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance

Publications (1)

Publication Number Publication Date
EP4199352A1 true EP4199352A1 (fr) 2023-06-21

Family

ID=79024482

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21214440.6A Pending EP4199352A1 (fr) 2021-12-14 2021-12-14 Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance

Country Status (3)

Country Link
EP (1) EP4199352A1 (fr)
CN (1) CN114900136A (fr)
WO (1) WO2023109760A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703490A (en) * 1995-07-28 1997-12-30 Honeywell Inc. Circuit and method for measuring current in an H-bridge drive network
US20140142879A1 (en) * 2011-05-13 2014-05-22 Continental Automotive Gmbh Differential voltage measurement
EP3171515A1 (fr) * 2015-11-17 2017-05-24 Nxp B.V. Circuit d'attaque de haut-parleur
US20210231710A1 (en) * 2020-01-24 2021-07-29 Qualcomm Incorporated Voltage-to-current architecture and error correction schemes
US20210344310A1 (en) * 2020-05-01 2021-11-04 Cirrus Logic International Semiconductor Ltd. Common-mode insensitive current-sensing topology in full-bridge driver

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104348431B (zh) * 2013-07-31 2017-04-26 快捷半导体(苏州)有限公司 共模反馈的差分放大电路及方法、集成电路
US10720890B1 (en) * 2019-02-12 2020-07-21 Realtek Semiconductor Corp. High-speed high-accuracy amplifier and method thereof
US10944366B2 (en) * 2019-03-04 2021-03-09 STMicroelectronics (Shenzhen) R&D Co. Ltd Advanced load current monitoring circuit and method for a class-AB amplifier
US11063567B2 (en) * 2019-09-25 2021-07-13 Texas Instruments Incorporated Input circuit with wide range input voltage compatibility
US11099589B1 (en) * 2020-03-16 2021-08-24 Alpha And Omega Semiconductor (Cayman) Ltd. Digitally programmable, fully differential error amplifier

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703490A (en) * 1995-07-28 1997-12-30 Honeywell Inc. Circuit and method for measuring current in an H-bridge drive network
US20140142879A1 (en) * 2011-05-13 2014-05-22 Continental Automotive Gmbh Differential voltage measurement
EP3171515A1 (fr) * 2015-11-17 2017-05-24 Nxp B.V. Circuit d'attaque de haut-parleur
US20210231710A1 (en) * 2020-01-24 2021-07-29 Qualcomm Incorporated Voltage-to-current architecture and error correction schemes
US20210344310A1 (en) * 2020-05-01 2021-11-04 Cirrus Logic International Semiconductor Ltd. Common-mode insensitive current-sensing topology in full-bridge driver

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
"Driving Converters - January 2000", 31 January 2000 (2000-01-31), pages 1 - 62, XP055187294, Retrieved from the Internet <URL:http://people.ece.cornell.edu/wes/Projects/AD_notes/SEMINARS/DRIVING.PDF;1> [retrieved on 20150504] *
BINET ET AL.: "A fully Integrated Class-D Amplifier in 40nm CMOS with Dynamic Cascode Bias and Load Current Sensing", ESSCIRC2014- 40TH EUROPEAN SOLID
BINET ET AL.: "A fully Integrated Class-D Amplifier in 40nm CMOS with Dynamic Cascode Bias and Load Current Sensing", ESSCIRC2014- 40TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE
JOHN HAMBURGER HAMBURGER DOBKIN ET AL: "Analog Circuit Design Volume Three", 2 January 2015 (2015-01-02), Saint Louis, XP055567797, ISBN: 978-0-12-800001-4, Retrieved from the Internet <URL:https://www.analog.com/media/en/technical-documentation/application-notes/an105fa.pdf> [retrieved on 20220822] *
MARCO BERKHOUTLUTSEN DOOPERBENNO KRABBENBORG: "A 4f2 2.65W Class-D Audio Amplifier with Embedded DC-DC Boost Converter, Current Sensing ADC and DSP for adaptive speaker protection", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 48, no. 12, 2013, pages 2952 - 2961, XP055156984, DOI: 10.1109/JSSC.2013.2284692
RAJPUT DEEPTI: "Designing of an OP-amp using CMFB Technique", 2 January 2017 (2017-01-02), pages 1 - 10, XP055953471, Retrieved from the Internet <URL:http://ijetsr.com/images/short_pdf/1484317765_deepti_ijetsr.pdf> [retrieved on 20220822] *

Also Published As

Publication number Publication date
WO2023109760A1 (fr) 2023-06-22
CN114900136A (zh) 2022-08-12

Similar Documents

Publication Publication Date Title
US7924089B2 (en) Offset voltage correction circuit and class D amplifier
US7446603B2 (en) Differential input Class D amplifier
US6707337B2 (en) Self-operating PWM amplifier
US7295063B2 (en) Class D amplifier
US7167046B2 (en) Class-D amplifier
US7312657B2 (en) Class D amplifier
US20070146069A1 (en) Filterless class D power amplifier
US8013677B2 (en) One-sided switching pulse width modulation amplifiers
JP4274204B2 (ja) Ｄ級増幅器
US20060044057A1 (en) Class-D amplifier having high order loop filtering
US20060145755A1 (en) Square wave modulation design for a class-D audio amplifier
US20020097090A1 (en) Method and apparatus for error correction of amplifier
US20200228075A1 (en) Class d amplifier current feedback
US4560946A (en) Power amplifier
US7633339B2 (en) Differential amplifier
EP4199352A1 (fr) Circuits de détection de tension et de courant pour mesurer une charge connectée à un amplificateur de puissance
US10819293B2 (en) Power amplifier
US11245368B2 (en) Class D amplifier
WO2023155600A1 (fr) Circuit et procédé de modulation dynamique de tension en mode commun et amplificateur de puissance audio de classe d
US10797665B2 (en) Programmable gain amplifier systems and methods
TWI487271B (zh) 放大器、音頻系統以及輸入信號的放大方法
US20220045656A1 (en) Class-d amplifier with nested feedback loops
KR100770747B1 (ko) 디지털 앰프 및 음성 재생 방법
NL2023246B1 (en) Three level PWM Class D amplifier
US20200228072A1 (en) Class d amplifier stereo to mono converter

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20231219

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR