EP4123969A1 - Mécanisme de reprogrammation pour dispositifs asynchrones - Google Patents

Mécanisme de reprogrammation pour dispositifs asynchrones Download PDF

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Publication number
EP4123969A1
EP4123969A1 EP21290048.4A EP21290048A EP4123969A1 EP 4123969 A1 EP4123969 A1 EP 4123969A1 EP 21290048 A EP21290048 A EP 21290048A EP 4123969 A1 EP4123969 A1 EP 4123969A1
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EP
European Patent Office
Prior art keywords
major frame
rescheduling
signal
rescheduled
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21290048.4A
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German (de)
English (en)
Inventor
Arnaud Bouchet
Patrice Garanx
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ratier Figeac SAS
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Ratier Figeac SAS
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Publication date
Application filed by Ratier Figeac SAS filed Critical Ratier Figeac SAS
Priority to EP21290048.4A priority Critical patent/EP4123969A1/fr
Priority to CA3161311A priority patent/CA3161311A1/fr
Priority to US17/858,217 priority patent/US11886371B2/en
Priority to BR102022013739-0A priority patent/BR102022013739A2/pt
Priority to CN202210847583.6A priority patent/CN115642973A/zh
Publication of EP4123969A1 publication Critical patent/EP4123969A1/fr
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40169—Flexible bus arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

Definitions

  • the examples disclosed herein relate to systems and methods for a rescheduling mechanism for asynchronous devices.
  • Asynchronous devices are devices that operate without reference to a global clock system.
  • the processing clock of asynchronous devices therefore operates independently of any frequency in the system to which the device is connected to.
  • these devices will exhibit asynchronous behaviour relative to each other even if they appear identical from a hardware and software perspective. This is due to the tolerances on the components and the processing clock.
  • the result of this asynchronous behaviour is that the processing cycle of one device will be slower than the processing cycle of the other device. This can cause divergence in systems that use two asynchronous devices such as dual motor control systems. In such situations, an additional mechanism is needed to prevent this divergence.
  • a first is that it must be decided which device becomes the "master” device, to which the "slave” device will be synchronized with.
  • a second issue is how to handle situations when the "master” device is lost and the slave device therefore loses its reference of the "master” device.
  • a third issue is how to handle a "babbling idiot” event of the "master” device. A babbling idiot even relates to situations when a device malfunctions and sends data at inappropriate times.
  • an asynchronous first device is in communication with an asynchronous second device is described herein.
  • the time for the first device to complete a processing cycle is a first device major frame.
  • the first device major frame comprises a first device dedicated processing time slot at the end of the first device major frame.
  • the first device is configured to send a rescheduling signal to the second device when it has completed a first device major frame.
  • the first device is configured, during every first device dedicated processing slot, to: monitor for a rescheduling signal sent from the second device to the first device; and if a rescheduling signal from the second device is received: shift the end of the current first device major frame by a set duration to result in a rescheduled first device major frame; and reschedule the subsequent first device major frames such that each subsequent rescheduled first device major frame starts as soon as the previous rescheduled first device major frame has ended.
  • the first device is further configured to, after start-up, monitor for a rescheduling signal sent from the second device to the first device; and if a rescheduling signal from the second device is received: initiate the first device major frame such that the start of the first device major frame coincides with the time the rescheduling signal from the second device was received.
  • the first device is further configured to after start-up, monitor for a rescheduling signal sent from the second device to the first device; and if no rescheduling signal from the second device is received after a waiting period: initiate the first device major frame after a timeout period.
  • the first device is further configured to, when the end of the current first device major frame is shifted by a set duration to result in a rescheduled first device major frame, modify the duration of the current first device major frame by the set duration.
  • the set duration is determined based on the maximum error of the clock tolerances between the first device and the second device.
  • the set duration is a rounded value of the sum of the clock tolerances of each of the first device and the second device.
  • the asynchronous second device can function in the same way as the asynchronous first device. That is, the time for the second device to complete a processing cycle is a second device major frame; wherein the second device major frame comprises a second device dedicated processing time slot at the end of the second device major frame, wherein the second device is configured to send a rescheduling signal to the first device when it has completed a second device major frame; and wherein the second device is configured, during every second device dedicated processing slot, to: monitor for a rescheduling signal sent from the first device to the second device; and if a rescheduling signal from the first device is received: shift the end of the current second device major frame by a set duration to a rescheduled second device major frame, , reschedule the subsequent second device major frames such that each subsequent rescheduled second major frame starts as soon as the previous rescheduled second device major frame has ended.
  • a method for rescheduling an asynchronous first device in communication with an asynchronous second device is described herein.
  • the time for the first device to complete a processing cycle is a first device major frame.
  • the first device major frame comprises a first device dedicated processing time slot at the end of the first device major frame; the method comprising: sending a rescheduling signal to the second device on completion of a first device major frame; and monitoring, during the dedicated processing time slot, for a rescheduling signal sent from the second device to the first device; if a rescheduling signal from the second device is received: shifting the end of the first device major frame by a set time duration to result in a rescheduled first device major frame, and rescheduling each subsequent first device major frame such that each subsequent rescheduled first device major frame is scheduled to start as soon as the previous rescheduled first device major frame has ended.
  • the method further comprises: after start-up, monitoring for a rescheduling signal sent from the second device to the first device; and if a rescheduling signal from the second device is received: initiating the first device major frame such that the start of the first device major frame coincides with the time the rescheduling signal from the second device was received.
  • the method further comprises: after start-up, monitoring for a rescheduling signal sent from the second device to the first device; and if no rescheduling signal from the second device is received on or after a or the waiting period: initiating the first device major frame after a timeout period.
  • the set duration is determined based on the maximum error of the clock tolerances between the first device and the second device.
  • the set duration is a rounded value of the sum of the clock tolerances of each of the first device and the second device.
  • the method can function in such a way that the second device performs the same method steps as the first device, wherein the time for the second device to complete a processing cycle is a second device major frame.
  • the second device major frame comprises a second device dedicated processing time slot at the end of the second device major frame.
  • the method comprises: sending a rescheduling signal to the first device on completion of a first device major frame; and monitoring, during the dedicated processing time slot, for a rescheduling signal sent from the first device to the second device; if a rescheduling signal from the first device is received: shifting the end of the second device major frame by a set time duration to result in a rescheduled second device major frame, and rescheduling each subsequent second device major frame such that each subsequent rescheduled second device major frame is scheduled to start as soon as the previous rescheduled second device major frame has ended.
  • the examples described herein provide a rescheduling mechanism for two asynchronous devices which does not rely on the synchronizing the two devices using a master/slave principle so that the rescheduling is not affected by the failure of one of the devices. Furthermore, the rescheduling mechanism described herein is simple, robust to failure, of low cost to implement, and does not affect the inner characteristics of the devices.
  • a rescheduling mechanism is therefore disclosed herein for two asynchronous devices that is simple and does not involve synchronization of the two devices using a master/slave principle. "Not involving synchronization" means that this rescheduling mechanism does not modify the inner characteristics of each of the asynchronous devices in terms of real time sequencing.
  • a first device 1 has a first processing clock 2 which operates at a first frequency.
  • a second device 11 has a second processing clock 12 which operates at a second frequency. Due to the manufacturing tolerances of the first device 1 and the second device 11, the first frequency is different from the second frequency.
  • first device 1 and the second device 2 complete rounds of respective processing cycles.
  • the processing cycle of the first device 1 takes place within a time duration which is referred to as a first device major frame 3, and the processing cycle of the second device 1 takes place within a time duration which is referred to as a second device major frame 13.
  • first device major frame 3 has a longer duration than the second device major frame 13.
  • second device major frame 13 has a shorter duration than the second device major frame 13.
  • each of the first 1 and second 11 devices Towards the end of each of the first device major frame 3 and the second device major frame 13, each of the first 1 and second 11 devices have a respective dedicated processing time slot 5, 15, within which rescheduling of either the first device 1 or the second device 11 is possible.
  • the first device 1 has a first device dedicated processing time slot 5, and the second device 11 has a second device dedicated processing time slot 15.
  • the first device dedicated processing time slot 5 has a time duration which is referred to as first device minor frame 4, and the second device dedicated processing time slot 15 has a time duration which is referred to as the second device minor frame 14.
  • the dedicated processing time slot 5, 15 therefore corresponds to a short time period wherein the processing cycle has not ended but the main steps of the processing cycle have been completed. Rescheduling the devices 1, 11 during their dedicated processing time slot 5, 15 therefore does not affect the real time sequencing of the device 1, 11.
  • Each of the first device 1 and the second device 11 are configured to send a rescheduling signal to the other device 1, 11 when it has completed its respective major frame 3, 13.
  • the ending of the first or second major frame 3, 13 coincides with the end of the first or second dedicated processing time slot 5, 15.
  • the rescheduling signal can comprise one or more signals which indicate that the processing cycle of the device 1, 11 has been completed.
  • the rescheduling signal can be simple such as a discrete interface, which is of low cost to implement.
  • the devices 1, 11 will only monitor and respond to the rescheduling signal if it is received by the device 1, 11 during its respective dedicated processing time slot 5, 15. If one of the devices 1, 11 receives the rescheduling signal during its dedicated processing time slot 5, 15, the end of the current major frame 3, 13 of the device 1, 11 will be modified to end earlier (or later) by a set duration which results in a rescheduled major frame 3', 13'. The end of the rescheduled major frame 3', 13' will be closer in phase to the end of the major frame 3, 13 of the device 1, 11 that sent the rescheduling signal.
  • the devices 1, 11 can be configured such that when rescheduling takes place, the set duration by which current major frame 3, 13 of the device 1,11 is shifted can either be a smaller or larger amount. If the current major frame 3, 13 is shifted by a small amount, then rescheduling events will take place more often. The advantage of this is that the major frames 3, 13 of the devices 1, 11 will eventually be very close and have a small amount of jitter. A disadvantage of this is that due temperature changes or ageing of the hardware, the rescheduling conditions of the rescheduled device 1, 11 may be lost.
  • An alternative is to shift the major frame 3, 13 by a large amount.
  • the rescheduling conditions will not be lost due to temperature changes of ageing of the device 1, 11.
  • the major frame 3, 13 is shifted by a larger amount, there will be relatively higher jitter between the devices 1, 11 compared to when the major frame 3, 13 is shifted by a smaller amount.
  • the jitter in this case may not be problematic, as shown below.
  • the value of the set duration by which a major frame 3, 13 is shifted can be determined based on the clock tolerances of the devices 1, 11.
  • the set duration may be a rounded value of the sum of the clock tolerances of each of the devices 1, 11. If both of the devices 1, 11 have a clock tolerance of 8ns, the set duration can be set to 20ns. In this scenario, if the major frames 3, 13 have a duration of 300 ⁇ s and one of the devices 1, 11 is rescheduled by 20ns, the jitter will only be 0.5% of the major frame 3, 13, which is negligible.
  • the second device 11 completes its second major frame 13 before the first device 1 and sends the rescheduling signal to the first device 1.
  • the first device 1 has the end of its major frame 3 shifted by a set time duration, which results in a rescheduled major frame 3'.
  • the rescheduled major frame 3' is rescheduled to end earlier which makes it closer in phase to the second device 11.
  • Other examples are also envisaged wherein the rescheduled major frame 3' is rescheduled to end later.
  • the subsequent major frames 3' are rescheduled so that they begin as soon as the previous major frame 3' has ended.
  • the first device 1 also receives a rescheduling signal during the dedicated processing slot 5 of the subsequent first device major frame 3'.
  • the first device major frame 3' is therefore rescheduled to end earlier by the set time duration, which results in a rescheduled major frame 3".
  • Case #2 shows the situation where no rescheduling takes place. Since the first device 1 has sent a rescheduling signal to the second device 11 when the second device 11 is outside of its dedicated processing time slot 15, there is no rescheduling of the second device major frame 13.
  • the major frame duration is not modified for either of the devices 1, 11, but rescheduling will shorten the length of the current major frame, or instantaneous cycle duration of the device 1, 11 receiving the rescheduling signals from the other device 1, 11 during its dedicated processing time slot 5, 15.
  • the other device will only consider this faulty rescheduling signal during the dedicated processing time slot.
  • the other device 1, 11 will therefore not have its inner functioning affected by the malfunctioning device 1, 11.
  • the rescheduling mechanism is therefore fault tolerant.
  • the first device 1 starts up after a reset and the second device 11 is functioning normally. Once the first device 1 has completed its Power On Built I Test, or Power On Self Test (POST), the first device 1 will wait until it has received the rescheduling signal from the second device 11. Upon receiving the rescheduling signal, the first device 1 will start its first device major frame 3. The first device major frame 3 will therefore be in phase with the start of the major frame 13 of the second device 11.
  • POST Power On Built I Test
  • the other device will perform its processing cycle with its predefined major frame 3, 13 after a waiting period and a dedicated timeout.
  • the second device 11 is not functioning, which can be due to the device 11 not being powered, being faulty, or having its communication link broken. Since the first device 1 does not receive a rescheduling signal from the second device 11, a dedicated timeout in the first device 1 will automatically start the first device major frame 3 of the first device. The rescheduling mechanism is therefore fault tolerant.
  • the implementation of the above described rescheduling mechanism can be of low cost, since the rescheduling signal can be simple such as a discrete interface.
  • the above described rescheduling mechanism is also robust to failure, because a device will only be rescheduled during its dedicated processing time slot 5, 15, by which time the major steps of the processing cycle of the device will have been completed. Therefore, if one of the devices malfunctions, the other device will not be negatively influenced by this.
  • the above described rescheduling mechanism can also be applied during start-up of the devices. In this instance, the rescheduling mechanism is also robust to either malfunction or failure of one of the devices.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
EP21290048.4A 2021-07-19 2021-07-19 Mécanisme de reprogrammation pour dispositifs asynchrones Pending EP4123969A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP21290048.4A EP4123969A1 (fr) 2021-07-19 2021-07-19 Mécanisme de reprogrammation pour dispositifs asynchrones
CA3161311A CA3161311A1 (fr) 2021-07-19 2022-06-01 Mecanisme de replanification pour des dispositifs asynchrones
US17/858,217 US11886371B2 (en) 2021-07-19 2022-07-06 Rescheduling mechanism for asynchronous devices
BR102022013739-0A BR102022013739A2 (pt) 2021-07-19 2022-07-11 Primeiro dispositivo assíncrono, e, método para reagendar um primeiro dispositivo assíncrono
CN202210847583.6A CN115642973A (zh) 2021-07-19 2022-07-19 用于异步设备的重调度机制

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Application Number Priority Date Filing Date Title
EP21290048.4A EP4123969A1 (fr) 2021-07-19 2021-07-19 Mécanisme de reprogrammation pour dispositifs asynchrones

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EP4123969A1 true EP4123969A1 (fr) 2023-01-25

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EP21290048.4A Pending EP4123969A1 (fr) 2021-07-19 2021-07-19 Mécanisme de reprogrammation pour dispositifs asynchrones

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US (1) US11886371B2 (fr)
EP (1) EP4123969A1 (fr)
CN (1) CN115642973A (fr)
BR (1) BR102022013739A2 (fr)
CA (1) CA3161311A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750171A (en) * 1986-07-11 1988-06-07 Tadiran Electronics Industries Ltd. Data switching system and method
US20040261101A1 (en) * 2003-06-18 2004-12-23 Sony Corporation And Sony Electronics Method and apparatus for non-centralized network bandwidth management

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8711991D0 (en) 1987-05-21 1987-06-24 British Aerospace Asynchronous communication systems
GB2217064A (en) 1988-03-23 1989-10-18 Benchmark Technologies Interfacing asynchronous processors
US8407191B1 (en) * 2010-06-29 2013-03-26 Emc Corporation Priority based data scrubbing on a deduplicated data store
WO2015196343A1 (fr) * 2014-06-24 2015-12-30 Intel Corporation Gestion d'électricité pour machine virtuelle
JP7321851B2 (ja) * 2019-09-09 2023-08-07 キオクシア株式会社 メモリシステムおよびガベッジコレクション制御方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750171A (en) * 1986-07-11 1988-06-07 Tadiran Electronics Industries Ltd. Data switching system and method
US20040261101A1 (en) * 2003-06-18 2004-12-23 Sony Corporation And Sony Electronics Method and apparatus for non-centralized network bandwidth management

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Publication number Publication date
BR102022013739A2 (pt) 2023-01-31
US20230013461A1 (en) 2023-01-19
US11886371B2 (en) 2024-01-30
CN115642973A (zh) 2023-01-24
CA3161311A1 (fr) 2023-01-19

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