EP4102559A1 - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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Publication number
EP4102559A1
EP4102559A1 EP21178802.1A EP21178802A EP4102559A1 EP 4102559 A1 EP4102559 A1 EP 4102559A1 EP 21178802 A EP21178802 A EP 21178802A EP 4102559 A1 EP4102559 A1 EP 4102559A1
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EP
European Patent Office
Prior art keywords
power semiconductor
semiconductor module
group
module according
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21178802.1A
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German (de)
English (en)
French (fr)
Inventor
Slavo Kicin
Arne SCHROEDER
Farhad YAGHOUBI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Energy Ltd
Original Assignee
Hitachi Energy Switzerland AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Energy Switzerland AG filed Critical Hitachi Energy Switzerland AG
Priority to EP21178802.1A priority Critical patent/EP4102559A1/en
Priority to CN202210647719.9A priority patent/CN115472594A/zh
Priority to JP2022093745A priority patent/JP2022189793A/ja
Priority to US17/806,337 priority patent/US12293973B2/en
Publication of EP4102559A1 publication Critical patent/EP4102559A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present disclosure relates to a power semiconductor module with a plurality of semiconductor switches arranged in at least two groups, the semiconductor switches having a first terminal and a second terminal of a controlled path and a control terminal.
  • a power semiconductor module is known in which several power semiconductor switches are connected together using separate substrate metallizations which are arranged in a stacked manner.
  • the object is achieved by a power semiconductor module with a plurality of semiconductor switches arranged in at least two groups, the semiconductor switches having a first terminal and a second terminal of a controlled path and a control terminal, each group having a first group contact which is connected to the first terminals, a second group contact which is connected to the second terminals and a control group contact which is connected to the control terminals, an interconnection bridge for connecting the control group contacts and the first group contacts of the at least two groups, the interconnection bridge comprising a layer structure with a first conductive layer and a second conductive layer being separated by an insulating layer.
  • Voltage applied between the control group contacts and between the first group contacts is used to control the state of the semiconductor devices, i.e. the voltage effects a switching of states between open and closed. Therefore, fast change of this voltage without critical oscillations is important for low-loss operation.
  • the described embodiments have an improved gate connection. Because of the very close arrangement within the interconnection bridge where both conductive layers are separated only by a very thin insulating layer, a substantial reduction of the gate control loop inductance can be achieved compared to the conventional wire-bond connection between substrates.
  • the physical reason for the reduced inductance is that for a very close arrangement of two conductors the inductive coupling significantly increases.
  • a current flowing through a the gate connection layer of the interconnection bridge to the gate terminals of the switches of that group mainly charges capacities of the gate electrodes.
  • Related currents flow in the other direction through the source connection layer of the interconnection bridge. Due to the anti-parallel direction of the currents and the mutual inductive coupling, a substantial reduction of the gate inductance can be effected.
  • the proposed embodiment enables that also in power semiconductor modules in which a large number of semiconductor switches are connected in parallel and accordingly the lengths of the connection paths to the different groups of semiconductor switches are very different, the effect of the different lengths on the gate inductances of the different groups of semiconductor switches is attenuated and a better synchronization of the switching behavior and less oscillations can be achieved. This results in an improved switching behavior and less power loss during the switching period.
  • resistors e.g. gate resistors located directly in the module, which are normally used to attenuate the oscillations between switches can be omitted or at least reduced. This additionally improves the switching behavior.
  • resistors are omitted, a direct connection between a module gate contact and control terminals of the plurality of semiconductor switches can be implemented, which mean that there are no electronic elements in between.
  • the layer structure is formed as a "normal" or flexible printed circuit board.
  • both sides of a flexible insulating material are at least partly covered by a conductive material such as a metal.
  • a conductive material such as a metal. Copper or aluminum or an alloy of copper and aluminum is advantageous as conductive material.
  • the layer structure is formed by a ceramic substrate with a two side metallization. It is advantageous if the interconnection bridge has at least two feet on each side, the feet being connected to group contacts of both groups by soldering or welding or by an adhesive connection.
  • Exemplarily MOSFETs or MISFETs or IGBTs are used as semiconductor switches in the embodiments described.
  • the semiconductor switches may be based on Silicon or a wide bandgap material, exemplarily SiC or GaN.
  • the present disclosure comprises an additional aspect of improvements of the gate connection, which is selectively increasing the inductance of certain connections within the module.
  • a compensation structure is provided for shorter gate connection paths. While the total gate inductance is increased by this measure, the differences between the inductances of gate connection paths of different groups within the module can be reduced. This further reduces oscillations and accordingly improves the switching behavior.
  • Compensation structures according to this aspect can be used in combination with the reduction of inductance as described above. This might become necessary or beneficial, because the physical possibilities to reduce the inductance are limited and a complete equalization cannot be achieved in all practical configurations. However, a combination of both aspects, i.e. reduction of the inductance of long connection paths and increase of inductance of short connection paths can lead to complete equalization or at least a substantial reduction of the differences of gate inductances.
  • Figure 1 is a schematic view of a power module 1 comprising two groups 2 and 3 of semiconductor switches 4. Gate terminals 10 of semiconductor switches 4 are connected to a module gate contact 5. The length of the conduction paths between the module gate contact 5 and the gate terminals 10 of the semiconductor switches 4 depends on the geometric arrangement of the components within the module 1. For example, if more than two groups of semiconductor switches are provided, it can be difficult to achieve an equal length of the connection paths for each of the groups of semiconductor switches.
  • the present disclosure it is not the aim to suppress oscillations but to avoid them from the beginning.
  • the approach is not to minimize the total gate inductance of the power semiconductor module 1, but to equalize the gate inductances of different groups of semiconductor switches. While the switching capability of the power semiconductor module 1 also depends on the total inductance of the gate path, oscillations strongly depend on the difference of inductances and the path lengths of two different groups 2 and 3 of semiconductor switches 4.
  • module stray inductance must be sufficiently low to avoid critical voltage overshoots, and inductance imbalance must be low to avoid oscillations between semiconductor switches.
  • the inductance of the gate path of the first group 2 can be described as a shared inductance L_shared + interconnection inductance L_interconnection + inductance L1, while the inductance of the second gate path can be described as shared inductance L_shared + L2.
  • the connection path to the first group 2 is longer than to the second group 3.
  • a part of the gate path to the first group 2 is implemented with an interconnection bridge 6.
  • the inductance of this part of the gate path can be reduced. In practice, a reduction of about 50% of the gate inductance of the gate path to the first group 2 can be achieved.
  • the proposed features can be beneficial especially in design of complex high-power modules based on many silicon carbide or gallium nitride switches located on several substrates and connected in parallel.
  • the concept of this disclosure can be implemented also in smaller power modules as shown in figure 1 .
  • Figure 2 shows the effect of an interconnection bridge in such an embodiment.
  • such two substrates would represent upper or lower side of the module.
  • Another such two substrates, connected in parallel, would form the other switch of this half-bridge module.
  • a resistor in the gate path can be at least reduced to a value of less than 2 ⁇ .
  • Such resistors can be implemented as semiconductor resistors and do not require additional production steps.
  • the disclosure has the advantage that resistors may be omitted to suppress oscillations or at least the implementation as substrate resistor.
  • Figure 3 shows a more detailed view of two groups 2 and 3 of semiconductor switches 4.
  • Semiconductor switches 4 are arranged on a metallization layer.
  • a section 15 of the metallization layer is used as a drain connection.
  • Another section of the metallization layer is separated to form a gate group contact 13, also referenced to as control group contact 13.
  • Further parts of the metallization are separated as source group contact 14 which is also referenced to as first group contact 14. This applies to both substrates of groups 2 and 3.
  • the gate terminals 10 of switches 4 are connected to a first side metallization 11 which appears in Figure 3 as top side metallization and from there to the gate group contact 13 as shown for the left group 2.
  • the first side metallization can also be split in for example two parts connected via a resistor 24 and a bond wire as shown for the right group 3. This way the resistor 24 with a value of less than 2 Qis integrated in the gate path to attenuate oscillations.
  • the source terminals of switches 4 are connected to a further metallization 16 which forms a source interconnection and from there to the first group contact 14.
  • the interconnection bridge 6 is used for the connection between the substrates, that means also between the different groups of switches.
  • Figure 4 shows a more detailed view of the interconnection bridge 6. It comprises two conductive layers 17 and 18. While the layer 18 is used as gate connection, layer 17 is used as source connection. Both layers are separated by an insulating layer which is not shown in this figure. On both sides of the interconnection bridge 6, feet 19 for the gate connection and feet 20 for the source connection are provided. These feet are connected to the control group contacts 13 and the first group contacts 14, for example, by welding or sintering or soldering or an adhesive.
  • Figure 5 shows an even more detailed view of the interconnection bridge 6.
  • the conductive layers 17 and 18 are separated by an insulating layer 21.
  • the interconnection bridge comprises a stacked sequence of layers with an insulating and protecting layer 25, followed by a first metallization 26 for a first potential, a thin insulating layer 27, a second metallization 28 for a second potential and a second insulating and protecting layer 29.
  • layers 25 and 26 and also layers 29 and 28 are provided as PCB.
  • terminals 30 and 36 are arranged which are used for electrical connection of both metallizations, i.e. the first metallization 26 and the second metallization 28.
  • vias can be used to access the metallizations 26 and 28 from the terminal side of the second insulating and protecting layer 29.
  • Figure 7 shows a cross-section of the embodiment of Figure 7 .
  • the terminals 30 and 36 for both potentials which can relate to the gate and source connection, are connected by vias to the first metallization 26 and the second metallization 28, respectively.
  • the mechanical stability is increased. This can be beneficial for very long interconnection bridges and additionally opens the possibility to reduce the thickness of the insulating layer to a minimum because it does not have to provide a mechanical function for mechanically stabilizing the interconnection bridge.
  • Another possibility for mechanically stabilizing the interconnection bridge is to use a glue somewhere between the terminals to support the bridge. This can be implemented for example in connection with all embodiments of this disclosure.
  • FIG. 8 shows a further embodiment of this disclosure.
  • groups 2 and 3 of semiconductor switches are integrated within a submodule 31.
  • Two additional groups of semiconductor switches 32 and 33 are integrated within a second submodule 34.
  • Each of the submodules 31 and 34 comprises a connection between the groups via an interconnection bridge 6 as described in the previous figures.
  • an interconnection bridge 35 is used which is formed similar to the interconnection bridge 6 for the intergroup connection within each submodule 31 and 34.
  • interconnection bridge 35 cannot fully equalize the differences of gate inductances of the gate paths to submodules 31 and 34. Therefore, an additional compensation structure 36 is provided according to the second aspect of this disclosure as described above.
  • the compensation structure effects an increase of the inductance of the gate connection path to the switches of the first submodule 31. Both, the decrease of inductance by interconnection bridge 35 and increase of inductance by compensation structure 36 contributes to more equal inductances in the gate connection paths of both submodules 31 and 34.
  • Figures 9 to 12 show possibilities which can be easily implemented.
  • Figure 9 shows a meander like structure in which the connection between contact point 38 and contact point 39 is increased by the meander structure.
  • islands 40 are formed in a metallization 22 of a substrate 23 and are connected by bond wires 41. Also this way the current path between connection points 38 and 39 is extended.
  • the compensation structure can also be implemented in the metallization 11.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Power Conversion In General (AREA)
EP21178802.1A 2021-06-10 2021-06-10 Power semiconductor module Pending EP4102559A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP21178802.1A EP4102559A1 (en) 2021-06-10 2021-06-10 Power semiconductor module
CN202210647719.9A CN115472594A (zh) 2021-06-10 2022-06-08 功率半导体模块
JP2022093745A JP2022189793A (ja) 2021-06-10 2022-06-09 パワー半導体モジュール
US17/806,337 US12293973B2 (en) 2021-06-10 2022-06-10 Power semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP21178802.1A EP4102559A1 (en) 2021-06-10 2021-06-10 Power semiconductor module

Publications (1)

Publication Number Publication Date
EP4102559A1 true EP4102559A1 (en) 2022-12-14

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US (1) US12293973B2 (enExample)
EP (1) EP4102559A1 (enExample)
JP (1) JP2022189793A (enExample)
CN (1) CN115472594A (enExample)

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WO2025191974A1 (ja) * 2024-03-11 2025-09-18 富士電機株式会社 半導体装置
CN119314974B (zh) * 2024-12-13 2025-04-11 北京怀柔实验室 功率半导体封装结构

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CN115472594A (zh) 2022-12-13
US20220399279A1 (en) 2022-12-15
US12293973B2 (en) 2025-05-06

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