EP4087138A1 - Codes de codage de transition à faible surdébit - Google Patents

Codes de codage de transition à faible surdébit Download PDF

Info

Publication number
EP4087138A1
EP4087138A1 EP21216671.4A EP21216671A EP4087138A1 EP 4087138 A1 EP4087138 A1 EP 4087138A1 EP 21216671 A EP21216671 A EP 21216671A EP 4087138 A1 EP4087138 A1 EP 4087138A1
Authority
EP
European Patent Office
Prior art keywords
bit
value
encoder
values
original
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21216671.4A
Other languages
German (de)
English (en)
Inventor
Aliazam Abbasfar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of EP4087138A1 publication Critical patent/EP4087138A1/fr
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
    • H03M5/12—Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/46—Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/34—Encoding or coding, e.g. Huffman coding or error correction

Definitions

  • aspects of embodiments of the present disclosure relate to systems and methods for implementing low overhead transition encoding in communication links.
  • communications between a sender and a receiver may be synchronized using a clock recovery or clock-data recovery (CDR) process.
  • CDR clock-data recovery
  • a receiver may generate a clock from an approximate frequency reference using a phase-locked loop (PLL) and then phase-align the generated signal to the transitions (between high signal levels and low signal levels) in the data stream using CDR.
  • PLL phase-locked loop
  • recovery of the clock signal can fail if the data run length (e.g., sequence of consecutive 1s or 0s) exceeds a particular length due to there being an insufficient number of transitions for the receiver to detect.
  • an encoder includes a processing circuit configured to: receive original data; partition the original data into a plurality of original q -bit words; assemble a data packet including N original q -bit words from the plurality of original q -bit words; identify a first encoder value D1 and a second encoder value D2 that are absent from the values of the N original q -bit words; encode the N original q -bit words based on a one-to-one mapping from q -bit original values to q -bit encoded values based on the first encoder value D1 and the second encoder value D2; to generate N encoded q -bit payload words, the N encoded q -bit payload words being free of words that are all-zeroes and free of words that are all-ones; generate a key representing the first encoder value D1 and the second encoder value D2; and transmit the key and the N encoded q -bit payload words.
  • a decoder includes a processing circuit configured to: receive a key and N encoded q -bit payload words; decode a first encoder value D1 and a second encoder value D2 from the key; and decode the N encoded q -bit payload words based on a one-to-one mapping from q -bit encoded values to q -bit original values based on the first encoder value D1 and the second encoder value D2 to generate N decoded original q -bit words.
  • aspects of embodiments of the present invention are directed to systems and methods for reducing or minimizing the run length of digital data in a communications system.
  • some aspects of embodiments of the present disclosure relate to systems and methods for encoding digital data to guarantee a limited run length or to guarantee that the run length of a packet of digital data is less than or equal to a particular limit in the form of run-length limited codes.
  • an encoder includes a processing circuit configured to: receive original data; partition the original data into a plurality of original q -bit words; assemble a data packet including N original q -bit words from the plurality of original q -bit words; identify a first encoder value D1 and a second encoder value D2 that are absent from the values of the N original q -bit words; encode the N original q -bit words based on a one-to-one mapping from q -bit original values to q -bit encoded values based on the first encoder value D1 and the second encoder value D2 to generate N encoded q -bit payload words, the N encoded q -bit payload words being free of words that are all-zeroes and free of words that are all-ones; generate a key representing the first encoder value D1 and the second encoder value D2; and transmit the key and the N encoded q -bit payload words.
  • the processing circuit may be configured to encode a q -bit original value x as a q -bit encoded value x' based on a comparison of the q -bit original value x with the first encoder value D1 and the second encoder value D2.
  • the first encoder value D1 and the second encoder value D2 may have matching prefixes of length q - 1, a computed value E may correspond to q - 1 most significant bits of D1, and the processing circuit may be configured to generate the key, the key including the computed value E representing the first encoder value D1 and the second encoder value D2.
  • the processing circuit may be configured to encode a q -bit original value x as a q -bit encoded value x' by computing an exclusive or operation on the original value x and the computed value E.
  • a space of 2 q values of the q -bit original values may be divided into a plurality of groups, each group including a plurality of different consecutive q -bit original values, and the processing circuit may be configured to identify the first encoder value D1 and the second encoder value D2 by: identifying one of the plurality of groups having two q -bit original values that are absent from the values of the N original q- bit words; and identifying one of the two q -bit original values in the identified group as the first encoder value D1 and another of the two q -bit original values in the identified group as the second encoder value D2.
  • the space of 2 q values of the q-bit original values may be divided into G groups, and N may be less than or equal to 2 q - G - 1.
  • each group may include up to three values
  • the processing circuit may be configured to select a middle one of the three values in the identified group as a computed encoder value E representing the first encoder value D1 and the second encoder value D2.
  • the processing circuit may be configured to encode a q -bit original value x as a q-bit encoded value x' based on a comparison of the q-bit original value x and the computed encoder value E.
  • each group may include 2 r values
  • the first encoder value D1 and the second encoder value D2 may share q - r most significant bits
  • the processing circuit may be configured to generate the key representing the first encoder value D1 and the second encoder value D2 by: encoding r least significant bits of D1 and r least significant bits of D2 using 2 r - 1 bits to generate a least significant bits code, the least significant bits code having at least one transition; and concatenating the q - r most significant bits with the least significant bits code.
  • the processing circuit may be configured to generate the key representing the first encoder value D1 and the second encoder value D2 by dividing the q - r most significant bits into a first part and a second part, and the least significant bits code may be concatenated between the first part and the second part of the q - r most significant bits.
  • the processing circuit may be configured to transmit a data packet including: the N encoded q -bit payload words; and a header including the key.
  • a decoder includes a processing circuit configured to: receive a key and N encoded q -bit payload words; decode a first encoder value D1 and a second encoder value D2 from the key; and decode the N encoded q -bit payload words based on a one-to-one mapping from q -bit encoded values to q -bit original values based on the first encoder value D1 and the second encoder value D2 to generate N decoded original q -bit words.
  • the processing circuit may be configured to decode a q- bit encoded value x' to a q-bit decoded value x based on a comparison of the q -bit encoded value x ' with the first encoder value D1 and the second encoder value D2.
  • the key may include a q - 1 bit value E
  • the processing circuit may be configured to decode the first encoder value D1 by setting q - 1 most significant bits of D1 to E and a least significant bit of D1 to 0, and the processing circuit may be configured to decode the second encoder value D2 by setting q - 1 most significant bits of D2 to E and a least significant bit of D2 to 1.
  • the key may include a q - 1 bit value E
  • the processing circuit may be configured to decode a q -bit encoded value x' to a q-bit original value x based on a result of an exclusive or operation performed on the q -bit encoded value x' and the q - 1 bit value E.
  • a space of 2 q values of the q -bit original values may be divided into a plurality of groups, each group including a plurality of different consecutive q -bit original values, each group may include up to three values, and the processing circuit may be configured to decode the first encoder value D1 and the second encoder value D2 based on a result of a modulo operation on the q - 1 bit value E.
  • the processing circuit may be configured to decode a q -bit encoded value x ' to a q -bit original value x based on a comparison of the q -bit encoded value x' and the q - 1 bit value E.
  • a space of 2 q values of the q -bit original values may be divided into a plurality of groups, each group including 2 r different consecutive q -bit original values, the first encoder value D1 and the second encoder value D2 may share q - r most significant bits, and the processing circuit may be configured to decode the first encoder value D1 and the second encoder value D2 from the key by: reading an 2 r - 1 bit least significant bits code from the key; decoding the least significant bits code to first least significant bits and second least significant bits; reading q - r most significant bits from a portion of the key; concatenating the q - r most significant bits with the first least significant bits to decode the first encoder value D1; and concatenating the q - r most significant bits with the second least significant bits to decode the second encoder value D2.
  • the decoder may be configured to receive a data packet including: the N encoded q -bit payload words; and a header including the key.
  • FIG. 1 is a schematic block diagram of a serial link between a sender 1 and a receiver 2, the sender 1 including an encoder 100 in accordance with embodiments of the present disclosure and the receiver 2 including a decoder 200 in accordance with embodiments of the present disclosure.
  • original data 10 is to be transmitted from the sender 1 to the receiver 2, where the original data 10 is reconstructed by the decoder 200 as decoded data 18.
  • the decoded data 18 may then be consumed by a data consumer 20.
  • the encoder 100 encodes the original data 10 into encoded data 30, and the encoded data 30 is transmitted over a data link 50 to the decoder 200.
  • the decoder 200 then decodes the encoded data 30 to reconstruct the decoded data 18.
  • the encoder 100 and the decoder 200 may, respectively, be referred to as an encoder circuit or encoder processing circuit and a decoder circuit or decoder processing circuit and may be implemented using various processing circuits such as a central processing unit (CPU), an application processor (AP) or application processing unit (APU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) such as a display driver integrated circuit (DDIC), and/or a graphics processing unit (GPU) of one or more computing systems.
  • CPU central processing unit
  • AP application processor
  • APU application processing unit
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • DDIC display driver integrated circuit
  • GPU graphics processing unit
  • the encoder 100 and the decoder 200 may be components of the same computer system (e.g., integrated within a single enclosure, such as in the case of a smartphone, tablet computer, or laptop computer), may be separate components of a computer system (e.g., a desktop computer in communication with an external monitor), or may be separate computer systems (e.g., two independent computer systems communicating over the data link 50), or variations thereof (e.g., implemented within special purpose processing circuits such as microcontrollers configured to communicate over the data link 50, where the microcontrollers are peripherals within a computer system).
  • the encoder circuit may be implemented using a different type of processing circuit than the decoder circuit.
  • the various processing circuits may be components of a same integrated circuit (e.g., as being components of a same system on a chip or SoC) or may be components of different integrated circuits that may be connected through pins and lines on a printed circuit board.
  • the sender 1 may include a graphics controller such as a graphics processing unit (GPU) or an application processing unit (APU) of a computer system (e.g., a laptop computer, a smartphone, a tablet computer, or the like) that generates image data as original data.
  • a graphics controller such as a graphics processing unit (GPU) or an application processing unit (APU) of a computer system (e.g., a laptop computer, a smartphone, a tablet computer, or the like) that generates image data as original data.
  • This image data or original data 10 is then transmitted over a data link 50 to a display panel (e.g., a liquid crystal display panel or an organic light emitting diode display panel), which includes a decoder 200 for decoding the encoded data 30 into the decoded image data 18.
  • a display panel e.g., a liquid crystal display panel or an organic light emitting diode display panel
  • the decoded image data 18 may then be supplied to a data consumer 20 such as processing circuits configured to convert the received decoded image data 18 into signals that control the display panel to display images (e.g., graphical user interfaces, video, and other display elements) as represented in the decoded image data 18.
  • a data consumer 20 such as processing circuits configured to convert the received decoded image data 18 into signals that control the display panel to display images (e.g., graphical user interfaces, video, and other display elements) as represented in the decoded image data 18.
  • a sender 1 and a receiver 2 can be synchronized using a clock recovery or clock-data recovery (CDR) process.
  • CDR clock-data recovery
  • a receiver using a CDR process typically operates by detecting the time of transitions between symbols on the physical layer of the data link (e.g., voltage levels of a signal on the link) and phase-aligning the clock of the receiver based on the detected transitions.
  • FIG. 2 is a depiction of binary data transmitted on a data link 50 using a unipolar line code, where logical 1 values are encoded as logic-level high (H) signals and logical 0 values are encoded as logic-level low signals (L).
  • the logic-level high and logic-level low signals may be physically encoded on the data link 50 as a high voltage (e.g., 5 volts or 3.3 volts) and a low voltage (e.g., 0 volts), respectively.
  • the data bit sequence 101001110010 is being transmitted over the data link 50. Transitions between logic-level low (L) and logic level high (H) voltages are shown by arrows 51.
  • FIG. 2 specifically highlights seven different runs labeled 52, 53, 54, 55, 56, 57, and 58 along with their corresponding run-lengths. Based on the data bit sequence 101001110010, runs 52, 53, 54, 55, 56, 57, and 58 have corresponding run-lengths of 1, 1, 1, 2, 3, 2, and 1, respectively.
  • the CDR process can fail due to there being an insufficient number of transitions in the received signal, which can cause problems in the recovery of the clock.
  • a logic-level high value e.g., high voltage
  • a logic-level low value e.g., a low voltage
  • Directly encoding the values of any particular input data can result in arbitrarily long run lengths.
  • a long sequence of words that are all zeroes (0s) or a long sequence of words that are all ones (1s) would result in a signal being continuously at a logic-level low value or a logic-level high value, respectively, with no transitions between bits to use for CDR. While some problems arising from long run lengths are described above in the context of unipolar NRZ encoding, similar problems may occur in other types of modulation that may have more than two signal amplitude levels (e.g., pulse amplitude modulation or PAM, with more than two levels, such as PAM4 which uses four amplitude levels).
  • PAM pulse amplitude modulation
  • aspects of embodiments of the present disclosure relate to systems and methods for encoding input data to generate encoded data bits, where the encoded data bits are guaranteed to have a limited run-length (e.g., a run length that is no longer than a particular limited number of bits). Limiting the run length of the data encoded in this way improves the ability of a decoder to perform CDR, thereby improving the quality of the communication link between the sender and the receiver. Aspects of embodiments of the present disclosure further relate to systems and methods for decoding the encoded data bits to recover the original input data.
  • a limited run-length e.g., a run length that is no longer than a particular limited number of bits
  • aspects of embodiments of the present disclosure relate to guaranteeing a transition every K bits (e.g., limiting the run length) by using a line coding algorithm to encode the raw data or original data such that transitions occur regularly.
  • FIG. 3 is a schematic depiction of a data packet.
  • Each data packet 31 may therefore be viewed as including a payload 32 of qN bits which may be numbered or indexed from 0 to qN - 1, as in: b[0: qN - 1 ].
  • Each q- bit word x may take on any value from 0 to 2 q - 1, and may also be represented as an array of q bits, e.g., b[0: q - 1].
  • the payload 32 can therefore be viewed as N words that are concatenated together into an array of qN bits: x 1 , x 2 , ..., x N x 1 b 0 : q ⁇ 1 , x 2 b q : 2 q ⁇ 1 , ... , x N b q N ⁇ 1 : qN ⁇ 1
  • q is set to 6, such that each word is 6-bits long, with values in the range of 0 to 63.
  • embodiments of the present disclosure are not limited thereto, and q may be set to other values such as 8, 10, 16, or the like, in accordance with design parameters and requirements of the encoding and decoding system and based on the application.
  • the data packet 31 further includes a header 34 (having a length of h bits) representing additional overhead information that is transmitted as part of the encoded data packet 31 and that is used by the decoder 200 to decode the encoded data packet.
  • the header 34 may include a key that contains information for decoding the encoded data packet 31.
  • the discussion herein assumes that all h bits of the header 34 are used by the key (e.g., the header 34 does not also include additional information such as parity bits for error detection or error correction). However, embodiments of the present disclosure are not limited thereto and may also include circumstances where the header 34 includes additional information.
  • the key is transmitted in a header 34 of the data packet 31 containing the N words of data (the qN payload bits) associated with the particular key
  • embodiments of the present disclosure are not limited thereto and, in some embodiments, the key is transmitted in a packet separate from the data packet 31 containing the payload bits.
  • some aspects of embodiments of the present disclosure relate to eliminating all-zero and all-one words from the encoded data 30 or ensuring that the encoded data 30 does not include (e.g., is free of) words that are all-zeroes and does not include any words that are all-ones. By eliminating all-zero words and all-one words from the encoded data, the run length is limited to a worst case of 2( q - 1) bits.
  • FIG. 4 when the 6-bit word 6'b100000 (identified as word x i ) is followed by the 6-bit word 6'b000001 (identified as word x i +1 , then there is a run of ten 0s (2 ⁇ (6 - 1)).
  • the 6-bit word 6'b011111 is followed by the 6-bit word 6'b111110, then there is a run of ten 1s. Because the all-zero and all-one words have been eliminated, any other pairs of consecutive words will result in shorter run lengths than the limited maximum run length of 2( q - 1) bits.
  • aspects of embodiments of the present disclosure will be described in more detail below with respect to systems and methods for encoding original data 10 to generate encoded data 30 where the encoded data 30 is free of words that are all-ones or all-zeroes (e.g., none of the words has q 0s and none of the words has q 1s).
  • aspects of embodiments of the present disclosure relate to systems and methods for decoding encoded data 30 to generate decoded data 18 matching the original data 10, which may include words that are all-ones and/or words that are all-zeroes.
  • FIG. 5 is a flowchart depicting a method 500 for encoding original data to generate a data packet according to one embodiment of the present disclosure.
  • the operations of FIG. 5 are implemented in an encoder 100 configured to perform the operations described herein, such as being implemented in instructions stored in a memory and executed by a processor or processing circuit to implement the encoder 100 where the processor and memory may be components of a microcontroller, an application processor, a central processing unit, a digital signal processor, a field programmable gate array, an application specific integrated circuit, or the like.
  • original data 10 is supplied to the encoder 100 from a data source (e.g., image data generated by a graphics processing unit).
  • the encoder 100 partitions the original data 10 into a plurality of q -bit words.
  • the number of bits q in each word x may be set in accordance with various design considerations, as discussed in more detail below.
  • the variable N will be used to refer to the number of words, such that operation 510 partitions the original data 10 into N words, each word being q bits long for a total of qN bits.
  • the encoder 100 identifies two q -bit words having values that are absent from the values of the N q -bit words that were partitioned from the original data 10 in operation 510.
  • a q -bit word may take on any of 2 q different values in the range from 0 to 2 q - 1.
  • a 6-bit word may take on any of 64 different values in the range from 0 to 63. Limiting the number of words N in a data packet guarantees that there exist at least two q -bit words that do not appear among the N q -bit words.
  • the two selected q- bit words will be referred to herein as encoder values D 1 and D 2, where D 1 ⁇ D 2. Aspects of embodiments of the present disclosure relating to the selection of encoder values D 1 and D 2 will be described in more detail below.
  • the encoder 100 encodes original data 10 based on D 1 and D 2 to generate encoded payload data having N encoded payload words, where the encoded payload data does not include any words that are all-zeros or all-ones (without regard to whether the original N q -bit words contained any words that were all-zeroes or all-ones).
  • the encoded payload data does not include any words that are all-zeros or all-ones (without regard to whether the original N q -bit words contained any words that were all-zeroes or all-ones).
  • the N encoded payload words is b000000 and none of the N encoded payload words is b111111 (the N original words may or may not have included instances of b000000 and/or b111111).
  • the encoder 100 encodes the original data based on a one-to-one mapping function between the original values and the encoded values.
  • FIG. 6 depicts the encoding of original data based on two encoder values D1 and D2 to generate encoded data according to one embodiment of the present disclosure.
  • the encoder 100 encodes the N original words by mapping the values of the words to encoded words in accordance with the following function enc ( x ) to encode original word x as encoded word x' :
  • an original word x is incremented by one when its value is less than D1, kept the same (identity) when its value is between D1 and D2, and decreased by one when its value is greater than D2.
  • q 4 (e.g., each word is 4 bits long), and the values 4 (4b0100), 5 (4b0101), 10 (4b1010), and 13 (4b1101) are absent from the original input data, which may be the bit sequence: 0001 0011 0110 1001 1000 0111 1111 1111 1111 0000 1110 1100 0010 1011
  • FIG. 6 shows a table of all possible 4-bit values of the words in decimal representations 601 and binary representations 602 and indicates values that appear in the original data with white backgrounds while values that are absent from the original data are shown with shaded backgrounds.
  • the value 4b0101 is selected as D1
  • the value 4b1010 is selected as D2 from among the four candidate values.
  • the encoding function or encoding mapping enc maps from the values of the original data 602 to corresponding encoded values 630, as indicated by the arrows 610.
  • the all-zeros value (4b0000) and the all-ones value (4b1111) is not used in the encoded version of the data.
  • the encoded version of the above example original data would be: 0010 0100 0110 1001 1000 01111110 1110 1110 0001 1101 1011 0011 1010
  • the encoded version of this original data does not include any all-zero values and does not include any all-ones values.
  • the maximum run-length has decreased from 12 in the original data to the worst-case maximum run-length of 6 (e.g., 2( q - 1)) in the encoded data.
  • x is mapped to D 1 if it is the all-ones value and mapped to D 2 if it is the all-zeroes value.
  • the encoded word x' has the same value as it had in the original word x. Accordingly, the original bit sequence above:
  • the encoder 100 In operation 570, the encoder 100 generates a header 34 (i.e. key) representing the encoder values (e.g., D1 and D2), and in operation 590, the encoder 100 generates a data packet 31 including the header 34 and the N encoded payload words 32. The resulting data packet 31 may then be transmitted as encoded data 30 over data link 50 to decoder 200.
  • a header 34 i.e. key
  • the encoder 100 generates a data packet 31 including the header 34 and the N encoded payload words 32.
  • the resulting data packet 31 may then be transmitted as encoded data 30 over data link 50 to decoder 200.
  • FIG. 7 is a flowchart depicting a method 700 for decoding an encoded data packet according to one embodiment of the present disclosure.
  • the data packet 31 may include a header 34 and encoded payload words 32.
  • the decoder 200 reads the header from a received data packet (e.g., the data packet encoded by the encoder 100) to decode encoder values (e.g., D1 and D2) from the header.
  • the encoder values D1 and D2 are used to determine a mapping from the encoded values of the encoded payload words to the decoded values of the original data in operation 750.
  • the decoder 200 decodes the N encoded words by mapping the values of the encoded words to decoded words in accordance with the following function dec ( x' ) to decode encoded word x' to original word x :
  • This mapping restores any all-zeroes values and any all-ones values that appeared in the original data.
  • FIG. 8 shows a mapping of 4-bit values of encoded words to corresponding decoded words or original words based on encoder values according to one embodiment of the present disclosure.
  • a decoding function or decoding mapping dec computes a mapping 820 from encoded values 830 to reconstructed or decoded original values in binary representation 818 and also shown in decimal representation 819.
  • aspects of embodiments of the present disclosure relate to systems and methods for encoding original data to limit the run-length in encoded data based on identifying unused values within the original data, selecting unused values as encoder values, and encoding the original data based on the encoder values.
  • aspects of embodiments of the present disclosure further relate to decoding encoded data based on the encoder values. Additional details regarding the selection of encoder values, the choice of the number N of words x in the data packet, and the number of bits q per word will be described in more detail below.
  • Some aspects of embodiments of the present disclosure relate to the selection of the number of words N in a data packet and the number of bits q in a word that enables further improvements in efficiency, such as by decreasing the number of header bits (or overhead bits) that are used to represent the encoder value or encoder values for decoding the encoded values per word in the N -word data packet 31.
  • some aspects of embodiments of the present disclosure relate to reducing the number of overhead bits used to transmit the encoder values (e.g., D1 and D2) through compression to fewer than 2 q bits. For example, if D1 and D2 are chosen so that they have common prefixes (or most significant bits), then both values can be transmitted in the header using fewer bits. More generally, some aspects relate to grouping the 2 q possible values of q -bit words based on common prefixes (or common most significant bits) and choosing a number of words N in a data packet such that two unused values (e.g., values that are absent from the original data to be encoded) are in the same group.
  • two unused values e.g., values that are absent from the original data to be encoded
  • a data packet of N words will have two unused values that fall in the same group when N ⁇ 2 q - G - 1, where the space of 2 q values of the q-bit words is divided into G groups.
  • the space of possible values for q-bit original words x is divided into groups of two consecutive values (pairs of values).
  • group 0 may include values 0 and 1
  • group 1 may include values 2 and 3
  • group 2 may include values 4, and 5 (in general, group k includes values 2 k and 2 k + 1).
  • group k includes values 2 k and 2 k + 1).
  • each group contains consecutive values having shared prefixes e.g., may share q - 1 most significant bits, the two values of each group differ only in their least significant bit. Therefore, when D1 and D2 fall within the same group, then both the first encoder value D1 and the second encoder value D2 can be encoded using q - 1 bits. This is guaranteed to be true in the case where N ⁇ 2 q G - 1. Accordingly, in these embodiments of the present disclosure, in operation 530 the encoder 100 identifies two encoder values D1 and D2 that fall within the same group.
  • all of the 5-bit overhead or key representing the groups include at least one transition, with the exception of group 0, which can be represented either as 00-000 or 11-111 (the '-' characters are included for readability).
  • an encoder determines whether to represent group 0 using 00-000 or 11-111 based on the value of the bit transmitted immediately before the key in order to result in a transition. For example, if the bit that is to be transmitted immediately before the key is a 1, then the encoder uses 00-000 as the key indicating group 0, whereas if the bit transmitted prior to the key is 0, then the encoder uses 11-111 to indicate group 0.
  • the encoder 100 may implement an encoding function or a mapping from original values to encoded values in operation 550 using the techniques described above (e.g., based on Equation (2) or Equation (3)) or equivalents thereof.
  • the ( q - 1)-bit value E is generated in the header 34 in operation 570, where the ( q - 1)-bit value E represents the group that contains both selected encoder values D1 and D2.
  • the encoder 100 then generates a data packet 31 including the header 34 (containing the ( q - 1)-bit value E ) and the encoded payload data 32 in operation 590.
  • the resulting data packet 31 may then be transmitted to a receiver 2 which uses a decoder 200 configured to decode the encoded payload data 32 in the data packet 31.
  • the decoder 200 determines a group based on the ( q - 1)-bit value E in the header 34 of the data packet 31. Because the group contains only two values, these values are taken by the decoder 200 as the encoder values D1 and D2, and thereby used to determine the mapping used by the decoder 200 (e.g., in accordance with Equations (4) or (5) as discussed above) to decode the encoded payload words in operation 750.
  • a similar XOR operation is performed at the decoder 200 in operation 750 based on the group identifier E transmitted in the header 34:
  • x dec
  • x ′ XOR XOR x ′ q ⁇ 1 : 1 , E , q ⁇ 1 x ′ 0 , x ′ 0
  • q 6
  • x XOR XOR x ′ 5 : 1 , E , 5 x ′ 0 , x ′ 0
  • the values of the words are arranged into groups of three consecutive values. For example: group 0 may identify values 0, 1, and 2; group 1 may identify values 3, 4, and 5; and so forth.
  • the encoder 100 may be configured to perform the mapping or encoding from the original words x to the encoded words x' in operation 550 using, for example, Equation (2) or Equation (3), above.
  • the decoder 200 may then decode encoded values into original values as described above with respect to Equations (4) and (5).
  • the space of possible values of the q -bit words is divided into groups of 2 r values, such that the values in each group share a common prefix up until the r least significant bits (e.g., the values may share the q - r most significant bits such that the q - r most significant bits are the same in each of the values).
  • the space of possible values of the q -bit words is divided into groups of four values, such that the values in each group share a common prefix up until the two least significant bits (e.g., the first q - 2 bits are the same).
  • the two selected values from the group are encoded using 2 r - 1 additional bits.
  • a group can be identified using the q - 2 bits (e.g., the q - 2 most significant bits or MSB) that are unique to each group.
  • the two values within a group that correspond to D1 and D2 differ at the remaining 2 bits (e.g., the 2 least significant bits or LSB) and this pair of values is identified in some embodiments using three additional bits, such as by using the below Table 4: Table 4 D1, D2 (2 LSBs decimal) D1, D2 (2 LSBs binary) LSBs code (3 bits) 0,1 00, 01 001 0,2 00, 10 010 0,3 00, 11 011 1,2 01, 10 100 1,3 01, 11 101 2,3 10, 11 110
  • the codes used to encode the least significant bits of the encoder values D1 and D2 within a group are designed such that each of the codes includes at least one transition (e.g., none of these codes is a string of three consecutive 0s or a string of three consecutive 1s). This is possible because the number of possible pairings of D1 and D2 is smaller than the number of bits used to encode this pair (e.g., 3 bits are used to encode 6 different possibilities, where 3 bits is capable of encoding 2 3 possible values).
  • q - 2 bits used to identify the groups may contain, for example, q - 2 consecutive 0s or q - 2 consecutive 1s.
  • merely concatenating the q - 2 bits used to identify a group with the 3 bits used to identify the encoder values D1 and D2 within the group can cause a run of q consecutive 0s or q consecutive 1s.
  • q 6
  • the group identifier is 0000
  • the LSBs code is 001 (identifying D1 and D2 as the values with LSBs 00 and 01, per Table 4)
  • concatenating 0000 with 001 results in the header 0000001, which includes a run of 6 consecutive 0s.
  • a similar problem may occur when the group identifier is 1111 and the LSBs code is 110, resulting in a run of 6 consecutive 1s.
  • the group identifier is split into two parts and the LSBs code is placed between the two parts.
  • the higher order bits that are common to D1 and D2 may be identified as D1[5:2] (e.g., the bits in positions 5 through 2 of D1 or, equivalently, of D2 as in D2[5:2]).
  • These four higher order bits may be divided into a first part: D1 [5:4] and a second part D1[3:2], and the LSBs code may be placed between these two parts, as in: ⁇ D 1[5:4], LSBs code, D 1[3:2] ⁇
  • the LSBs codes are designed such that each includes at least one transition. Therefore, by placing the LSBs code in between the two parts, the maximum run length of the header 34 is (( q - 2))/2 + 2. For example, in the case of a group identifier of 0000 and the LSBs code of 001 above, the header is encoded as 0000100, which results in a run of four consecutive 0s.
  • the decoder 200 decodes the first encoder value D1 and the second encoder value D2 in operation 710 by reading the most significant bits (e.g., D1[5:4] concatenated with D1[3:2]) from the header 34 and reading the least significant bits code (LSBs code) from the header 34, then decoding the LSBs code (e.g., based on the table, above) to determine the least significant bits of D1 and the least significant bits of D2.
  • the most significant bits e.g., D1[5:4] concatenated with D1[3:2]
  • LSBs code least significant bits code
  • the most significant bits read from the header 34 are then concatenated with the decoded least significant bits of D1 to decode the full first encoder value D1, and the most significant bits read from the header 34 are then concatenated with the decoded least significant bits of D2 to decode the full second encoder value D2.
  • the overhead is 7 bits.
  • the encoder and the decoder may be implemented in a manner similar to that described above.
  • the decoder 200 is configured to decode the encoder values from the header 34 containing the q -bit values D 1 and D 2 in accordance with Equations (2) or (3). Similarly, the decoder 200 may then decode encoded values into original values as described above with respect to Equations (4) or (5).
  • the space of possible values is divided into groups of eight consecutive values.
  • group 0 may include the values 0 through 7
  • group 1 may include the values 8 through 15, and so on.
  • the values within each group share a common prefix of q - 3 bits and may differ only in their three least significant bits.
  • the values D1 and D2 are encoded using the code: ⁇ LSBs code, MSBs ⁇
  • the MSBs are split into two parts and the LSBs code is placed between the two parts of the MSBs, in a manner similar to that described above.
  • the MSBs may be split into a first part with the first three bits (D1[7:5]) and a second part with the next two bits (D1[4:3]).
  • this may be expressed as: ⁇ D 1[7:5], LSBs code, D 1[4:3] ⁇
  • the encoder 100 may implement an encoding function or a mapping from original values to encoded values in operation 550 using the techniques described above (e.g., based on Equation (2) or Equation (3)) or equivalents thereof.
  • the decoder 200 may implement a decoding function or mapping from the encoded values in operation 750 using the techniques described above (e.g., based on Equation (4) or Equation (5)) or equivalents thereof.
  • the encoder 100 implements a two-stage mapping from the original values to encoded values in operation 550 using XOR ( ⁇ ) operations.
  • the word x to be encoded is XORed with D1 to compute an intermediate value y.
  • one or more bits of y are XORed with one of the bits of y .
  • x' is computed by selecting any single bit location z of the value of y calculated for D2 having a value of 1 and XORing the value at this bit location z with the bits of y at locations other than z and copying the bit at bit location z to the same location z of x'.
  • Table 5 shows a specific example where D1 and D2 correspond to the values 9 and 11, respectively.
  • aspects of embodiments of the present disclosure provide systems and methods for encoding data to reduce a maximum run length, thereby increasing the frequency of transitions on a data link.
  • Increasing the frequency of transitions can, for example, improve a clock-data recovery process, thereby improving the quality of the connection between a sender and a receiver communicating over the data link.
  • some aspects of embodiments of the present disclosure relate to partitioning original data into data packets of N words, each word being q -bits long, encoding original data such that the encoded data is free of words that are all-zeroes or all-ones, thereby ensuring that a transition occurs at least once every q -bits.
  • the encoding is performed based on a one-to-one mapping defined by two encoder values corresponding to two values that do not appear in the original data, where the two encoder values are transmitted as overhead for use by the decoder in defining a mapping for decoding the encoded data. Further improvements to efficiency result from decreasing the data overhead associated with the encoding process by compressing the encoder values.
  • embodiments of the present disclosure are not limited thereto and may also be applied in other types of serial data links and serial data buses for connecting to other types of peripherals and computing devices, such as data storage devices (e.g., volatile or non-volatile memories, mass storage devices, and the like), external co-processing devices (e.g., external graphics processing units, artificial intelligence accelerators, and the like), network controllers, other computer systems, smartphones and other portable computing devices, and the like.
  • data storage devices e.g., volatile or non-volatile memories, mass storage devices, and the like
  • external co-processing devices e.g., external graphics processing units, artificial intelligence accelerators, and the like
  • network controllers e.g., other computer systems, smartphones and other portable computing devices, and the like.
  • Embodiments of the present invention can be implemented in a variety of ways as would be appreciated by a person of ordinary skill in the art, and the term "processor” as used herein may refer to any computing device capable of performing the described operations, such as a programmed general purpose processor (e.g., an ARM processor) with instructions stored in memory connected to the general purpose processor, a field programmable gate array (FPGA), and a custom application specific integrated circuit (ASIC).
  • a serial communications controller e.g., a universal serial bus or USB controller
  • GPU graphical processing unit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Probability & Statistics with Applications (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Optical Communication System (AREA)
  • Liquid Crystal (AREA)
EP21216671.4A 2021-05-06 2021-12-21 Codes de codage de transition à faible surdébit Pending EP4087138A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163185190P 2021-05-06 2021-05-06
US17/389,146 US11967973B2 (en) 2021-05-06 2021-07-29 Low overhead transition encoding codes

Publications (1)

Publication Number Publication Date
EP4087138A1 true EP4087138A1 (fr) 2022-11-09

Family

ID=79270049

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21216671.4A Pending EP4087138A1 (fr) 2021-05-06 2021-12-21 Codes de codage de transition à faible surdébit

Country Status (6)

Country Link
US (1) US11967973B2 (fr)
EP (1) EP4087138A1 (fr)
JP (1) JP2022173081A (fr)
KR (1) KR20220152513A (fr)
CN (1) CN115314185A (fr)
TW (1) TW202245428A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4131875A1 (fr) * 2021-08-04 2023-02-08 Samsung Display Co., Ltd. Procédé de codage et/ou décodage de données et appareil associé

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2357408A (en) * 1996-07-11 2001-06-20 4Links Ltd Codeword substitution in dependance upon run-lengths
US20010040518A1 (en) * 2000-05-10 2001-11-15 Coene Willem Marie Julia Marcel Method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, device for encoding, signal comprising a stream of databits of a constrained binary channel signal, record carrier, method for decoding, device for decoding
US6897793B1 (en) * 2004-04-29 2005-05-24 Silicon Image, Inc. Method and apparatus for run length limited TMDS-like encoding of data

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906485A (en) 1973-06-13 1975-09-16 Ibm Data coding circuits for encoded waveform with constrained charge accumulation
US4027335A (en) 1976-03-19 1977-05-31 Ampex Corporation DC free encoding for data transmission system
JPS57176866A (en) 1981-04-24 1982-10-30 Sony Corp Encoder of binary signal
US4501000A (en) 1981-07-27 1985-02-19 Sony Corporation Method of coding binary data
US5297185A (en) 1992-02-13 1994-03-22 North American Philips Corporation Pattern detection and synchronization circuit
US5550864A (en) 1993-12-01 1996-08-27 Broadband Communications Products Bit rate-insensitive mechanism for transmitting integrated clock and data signals over digital communication link
CA2183355C (fr) 1994-02-15 2006-05-30 Kornelis Antonie Schouhamer Immink Procede de conversion d'une serie de mots d'information de m-bits en un signal modulee, procede de production d'un support d'enregistrement, dispositif de codage, dispositif de decodage, dispositif d'enregistrement, dispositif de lecture et support d'enregistrement
US5589829A (en) * 1994-10-26 1996-12-31 Intel Corporation Decoding variable-length encoded signals
US5859601A (en) 1996-04-05 1999-01-12 Regents Of The University Of Minnesota Method and apparatus for implementing maximum transition run codes
US6124811A (en) * 1998-07-02 2000-09-26 Intel Corporation Real time algorithms and architectures for coding images compressed by DWT-based techniques
KR100565046B1 (ko) * 1999-04-21 2006-03-30 삼성전자주식회사 개선된 ｄｃ 억압 능력을 갖는 ｒｌｌ 코드 배치 방법, 변복조 방법 및 복조 장치
US6516035B1 (en) * 2000-04-07 2003-02-04 Actisys Corporation Intelligent encoding method for wireless data communication and control
JP3709818B2 (ja) 2000-10-31 2005-10-26 日本ビクター株式会社 符号化テーブル及びそれを用いた変調装置、伝送装置並びに記録媒体
US7084788B2 (en) 2001-04-20 2006-08-01 Samsung Electronics Co., Ltd. Code generation and allocation method
CN100456640C (zh) 2001-06-07 2009-01-28 日本胜利株式会社 调制和解调方法与装置、信息传输方法和装置
CN100428633C (zh) 2001-06-29 2008-10-22 日本胜利株式会社 数字信号的调制方法及调制装置
WO2003088501A2 (fr) * 2002-04-18 2003-10-23 Koninklijke Philips Electronics N.V. Signal, support de stockage, procede et dispositif de codage, procede et dispositif de decodage
US6765511B2 (en) 2002-06-27 2004-07-20 Victor Company Of Japan, Ltd. Method and apparatus for encoding digital data
FR2857811A1 (fr) 2003-07-16 2005-01-21 St Microelectronics Sa Methode de chiffrage d'un flux audio ou video compresse a tolerance d'erreurs
US7330137B2 (en) 2003-12-12 2008-02-12 Mediatek Inc. Method and apparatus for RLL code encoding and decoding
US7142135B1 (en) 2005-09-06 2006-11-28 Media Tek Inc. Modulation methods and systems
US7436331B1 (en) * 2006-04-12 2008-10-14 Marvell International Ltd. Rate-28/30 DC-free RLL code
US9419749B2 (en) * 2009-08-19 2016-08-16 Qualcomm Incorporated Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes
US7667626B1 (en) * 2007-04-27 2010-02-23 Marvell International Ltd. Enumerative DC-RLL constrained coding
US7432834B1 (en) * 2007-07-05 2008-10-07 International Business Machines Corporation RLL encoding for LTO-5 tape
KR101235696B1 (ko) 2012-09-28 2013-02-21 주식회사 아나패스 데이터 전송 방법 및 데이터 복원 방법
US9729681B2 (en) 2012-09-28 2017-08-08 Anapass Inc. Data transmission method and data restoration method
US9860560B2 (en) * 2014-07-02 2018-01-02 Qualcomm Incorporated Method for palette mode coding
US10972125B2 (en) * 2016-06-20 2021-04-06 Anacode Labs, Inc. Storage access interface to an encoded storage system
US9654140B1 (en) * 2016-08-27 2017-05-16 Scured2 Corporation Multi-dimensional run-length encoding
US10389385B2 (en) 2017-01-19 2019-08-20 Samsung Electronics Co., Ltd. BM-based fast chase decoding of binary BCH codes through degenerate list decoding
US10476664B2 (en) 2017-10-27 2019-11-12 Quantropi Inc. Methods and systems for data protection
CN111201749B (zh) 2017-10-27 2021-09-28 量子熵有限公司 用于安全数据通信的方法和系统
US11323247B2 (en) 2017-10-27 2022-05-03 Quantropi Inc. Methods and systems for secure data communication
TWI757609B (zh) 2018-08-03 2022-03-11 日商索尼股份有限公司 用於通訊的傳輸設備和方法、接收設備和方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2357408A (en) * 1996-07-11 2001-06-20 4Links Ltd Codeword substitution in dependance upon run-lengths
US20010040518A1 (en) * 2000-05-10 2001-11-15 Coene Willem Marie Julia Marcel Method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, device for encoding, signal comprising a stream of databits of a constrained binary channel signal, record carrier, method for decoding, device for decoding
US6897793B1 (en) * 2004-04-29 2005-05-24 Silicon Image, Inc. Method and apparatus for run length limited TMDS-like encoding of data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4131875A1 (fr) * 2021-08-04 2023-02-08 Samsung Display Co., Ltd. Procédé de codage et/ou décodage de données et appareil associé
US11632127B2 (en) 2021-08-04 2023-04-18 Samsung Display Co., Ltd. Near-optimal transition encoding codes

Also Published As

Publication number Publication date
JP2022173081A (ja) 2022-11-17
CN115314185A (zh) 2022-11-08
TW202245428A (zh) 2022-11-16
KR20220152513A (ko) 2022-11-16
US20220368342A1 (en) 2022-11-17
US11967973B2 (en) 2024-04-23

Similar Documents

Publication Publication Date Title
US10355815B2 (en) Bitwise operations and apparatus in a multi-level system
US6747580B1 (en) Method and apparatus for encoding or decoding data in accordance with an NB/(N+1)B block code, and method for determining such a block code
JP3737204B2 (ja) 誤り訂正方法及び装置
US6504493B1 (en) Method and apparatus for encoding/decoding data
US11075652B2 (en) Polar code transmission method and apparatus
Deng et al. DC-free coset codes
EP0824817A1 (fr) Appareil et procede de transmission de donnees a multi-niveaux
JP3283097B2 (ja) 通信システム
WO2019053555A1 (fr) Correction d'erreurs sans voie de retour grâce à un codage par compression
RU2310273C2 (ru) Способ кодирования-декодирования информации в системах передачи данных
US20090276683A1 (en) Data transmission equipment and generating method for transmission code
EP4087138A1 (fr) Codes de codage de transition à faible surdébit
US6895546B2 (en) System and method for encoding and decoding data utilizing modified reed-solomon codes
US5938773A (en) Sideband signaling with parity bit schemes
EP4216442A1 (fr) Codage généralisé de paquets quasi optimal
US5574448A (en) Method and apparatus for encoding data with variable block lengths
US6438181B1 (en) Efficient metric memory configuration for a Viterbi decoder
US8301962B2 (en) Apparatus and method for generating a linear code
CN114303320A (zh) 使用逆crc生成器多项式进行解码的循环冗余校验crc
Kasami et al. Decoding of linear delta-decodable codes for a multiple-access channel (Corresp.)
US20030044075A1 (en) Block coding/decoding method and apparatus for increasing code rate
CN110289863B (zh) 译码设备、方法及信号传输系统
US11671198B2 (en) Processing problematic signal modulation patterns as erasures using wireless communication devices
Fujiwara et al. A class of optimal fixed-byte error protection codes for computer systems
CN116488669A (zh) 发射器、接收器以及通信系统

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20230330

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230516

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS