Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/402—Field plates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
  • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L29/2003—Nitride compounds
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular

Definitions

• the invention lies in the field of high electron mobility field effect transistors called HEMT transistors (acronym of the English expression "High Electron Mobility Transistor”) in GaN technology and for microwave applications, typically at frequencies up to 40 GHz, see 80 GHz in the near future.
• HEMT transistors analog of the English expression "High Electron Mobility Transistor”
• the invention relates to improving the reliability and the gain of the HEMT transistor.
• the invention applies to RF power HEMT transistors and transistors for switching.
• FIG. 1 diagrammatically represents a section of the structure of a conventional elementary HEMT transistor, in an XZ plane, produced on a substrate 11.
• an insulating or semiconductor substrate 11 is used, for example comprising silicon ( Si), silicon carbide (SiC), gallium nitride (GaN) or sapphire (Al 2 0 3 ), on which is produced a stack along the Z axis of at least two semiconductor layers which extend in the XY plane.
• a first layer 12 called buffer layer, or "buffer” (term used in the English literature), has a wide band gap (semiconductor material called large gap) comprising a material of the III family -N, a family of semiconductors composed of elements from Mendeleiev's column 3 and nitrogen, which may for example be a binary compound such as GaN or a ternary compound such as AIGaN, or more precisely Al x Ga- i- x N.
• barrier layer 13 has a greater forbidden band than that of the buffer layer 12.
• This layer comprises a material based on a quaternary, ternary or binary compound of nitride of elements from column III, called III-N, based on Al, Ga, In, B or Sc.
• the barrier layer comprises Al x Ga-i- x N, I ⁇ h-
• the thickness of the barrier layer 13 is typically between 3 nm and 40 nm, the thickness of the buffer layer 12 is typically between 0.2 ⁇ m and 3 ⁇ m.
• the buffer layer 12 and the barrier layer 13 are conventionally produced by epitaxy by MOCVD or by MBE.
• GaN-based buffer layer with a barrier layer based on AIGaN or InAIN, and more precisely based on Al x Ga-i- c N or ln z Al-
• Additional layers may be present either on the surface or between the buffer layer and the barrier layer.
• the junction between the buffer layer and the barrier layer constitutes a heterojunction 15 which also extends in the XY plane.
• a two-dimensional gas of electrons 9 (called 2DEG for “two-Dimensional Electron Gas”) is located in the vicinity of the heterojunction 15.
• a HEMT transistor conventionally comprises a source S, a drain D and a gate G.
• the source S and the drain D are in electrical contact with 2DEG.
• the X axis is defined as the alignment axis of S, G and D.
• the gate G is deposited on the upper face 14 of the barrier layer 13 between the source S and the drain D, and makes it possible to control the transistor .
• the gate-source distance is between 0.4 and 1 ⁇ m and the gate-drain distance is between 0.6 and 3 ⁇ m.
• We define the grid length Lg as the dimension of the grid along the X axis.
• the conductance between the source S and the drain D is modulated by the electrostatic action of the gate G, conventionally of the Schottky type or of the MIS type for (metal / insulator / semiconductor), and the voltage V G s applied between the gate and the source controls the transistor.
• the electrons of 2DEG are mobile in the OXY plane and have a high electronic mobility pe, typically greater than 1000cm 2 / Vs. In normal operation of the transistor these electrons cannot flow in the Z direction because they are confined in the potential well forming in the OXY plane in the vicinity of the heterojunction 15.
• the electron gas 9, confined in what is called the channel of the transistor, is therefore able to transport a current U s flowing between the drain and the source.
• a potential difference V ds is applied between the source S and the drain D, typically with a source S at the mass, and the value of the current bs is a function of the applied voltage V gs between the gate G and the source S.
• the transistor effect is based on the modulation of the number of free carriers in the channel between the contacts S and D (and therefore of the current flowing between the source and the drain) by the electrostatic action of the control electrode G.
• the voltage amplitude V gs to be applied is inversely to the transconductance gm of the transistor, this transconductance itself being itself inversely proportional to the thickness of the barrier. It is the transistor amplification effect which makes it possible to transform a weak signal applied to the gate into a stronger signal recovered on the drain.
• the grid G has a T-shape and consists of a trunk surmounted by at least one cap (there may be several on top of the other ).
• the two branches of the cap are not necessarily symmetrical, and the branch on the drain or source side may even be non-existent (so-called G gate).
• the base of the trunk is commonly referred to as the grid foot.
• the face 14 is covered with a dielectric layer PL, called passivation layer, because the upper face 14 of the barrier layer 13 must be protected from contact with the outside.
• the dielectric materials used are: Al 2 0 3 , Si 3 N 4 , Si0 2 , SiOxNy, BN or AIN.
• HEMT transistors used for applications of interest have a source S connected to the electrical ground, typically to a ground plane conventionally produced by a metallization layer arranged on the side of the substrate 11 opposite to layer 12 (bottom side of 11 in Figure 1).
• the connection is for example made using connection holes also called “via hole” which pass through the substrate from the source to the ground plane.
• the particularly intense electric field in these materials can locally reach an intensity greater than several MV / cm.
• the transistor is used as a voltage amplifier (common source assembly) the maximum electric field is located at the foot of the gate, on the drain side (it is between the gate and the drain that the voltage drop is located. higher, the potential difference between these two electrodes being able to reach several tens of volts).
• GaN substrates Due to the absence of large GaN substrates (greater than 3 ”), it is necessary to achieve the growth of semiconductor materials on host substrates such as Al 2 0 3 , SiC or silicon. However, the latter have a lattice parameter different from that of GaN, which generates a high density of defects oriented perpendicular to the current flowing in the channel. These defects pass through the entire structure and the density of defects emerging at the surface is typically of the order of 10 8 to a few 10 9 / cm 2 . These faults constitute points of weakness of the transistor which, under the action of a high electric field and the mechanical stresses induced by the reverse piezoelectric effect, will be at the origin of a degradation of the performances (increase of the gate current in particular. ) or even component failure.
• Another solution consists in reducing the distance between the grid cap and the surface 14.
• the grid profiles making it possible to sufficiently reduce the electric field at the base of the grid are accompanied by an increase in the Cgd and Cgs capacities of the transistor when the electron density in the channel is greater than 1 0x10 13 / cm 2 .
• This increase is all the more marked as the electron density is high and results in a degradation of the power gain.
• the electron density in the channel can reach values close to 2x10 13 / cm 2 .
• the latter solution therefore has a limit for the high electron densities in the channel.
• Another parameter of interest for the transistor is its gain.
• two approaches are implemented: either the gate length is reduced, but this is done to the detriment of the confinement of the electrons in the channel, hence a reduction in the transconductance gm and therefore of the gain in power which requires to modify the epitaxy so as not to degrade this last characteristic. or we reduce the thickness of the barrier but this leads to a decrease in the density of electrons in the channel and ultimately to a decrease in the gain.
• a modification of the epitaxy (at the level of the barrier) is necessary to compensate for this reduction.
• Document JP2011 -210752 describes a HEMT transistor comprising a first set of field plates or "field plate" FAi associated with a second set of field plate FBi.
• the association of these two assemblies makes it possible to reduce the electric field in the transistor by a capacitive effect obtained between these two rows of electrodes via passivation between the two rows.
• This approach is well suited for power components used for energy conversion (switching) operating at low frequency and high voltage (> 600V) but is not applicable for an RF (high frequency) power component.
• the small distance between the gate and the drain of these RF components does not allow two rows of “field plate” optimally (due to lack of space between the grid and the drain).
• the presence of these two rows would add capacitive couplings (between gate and drain) which would degrade the gain of the transistor.
• An object of the present invention is to remedy the aforementioned drawbacks by providing a HEMT transistor having an electric field at the foot of the gate reduced while maintaining an acceptable gain, compatible with high frequency operation.
• a stack along a Z axis deposited on a substrate comprising:
• a buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first forbidden band
• barrier layer comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second forbidden band, the second forbidden band being greater than the first forbidden band
• a first dielectric layer deposited at least on an upper surface of the barrier layer between the gate and the drain and between the gate and the source, exhibiting a relative permittivity er and thickness e such that:
• the relative permittivity of the first dielectric layer is between 3 and 10.
• the operating frequency is between 10 and 80 GHz.
• the metal pad is electrically connected to the grid by a first metal connection.
• a sum of a section of the grid, of a section of the pad and of a section of said first metal connection connecting the grid and the PM pad is greater than or equal to twice a section of the grid.
• the first metal connection is in electrical contact with the metal pad
• the transistor further comprises a second dielectric layer deposited at least on the metal pad, the first metal connection being in contact with said second dielectric layer deposited on the metal pad, so as to make a connection capacitive between the metal pad and the grid.
• the first metal connection is in electrical contact with the grid.
• the second dielectric layer is also deposited on the gate, and the first metal connection is in contact with a part of the second dielectric layer deposited on the gate.
• the grid is connected to a grid bus and the metal pad is connected to said grid bus.
• a sum of a section of the grid and a section of the pad is greater than or equal to twice a section of the grid.
• the transistor further comprises a second metal connection connecting the gate and the metal pad on the side opposite to the gate bus.
• the invention relates to an assembly comprising a plurality of transistors according to the invention, in which a transistor shares with an adjacent transistor alternately a source and a drain and in which the sources are interconnected by a bridge source.
• Figure 1 already cited schematically shows a section of the structure of a conventional elementary HEMT transistor.
• FIG. 2 already cited represents a conventional HEMT transistor with a gate having a T-shape.
• Figure 3 illustrates a high mobility field effect transistor according to the invention.
• FIG. 4 illustrates the effect of the metal pad on the electric field in the channel for a transistor operating at the point of polarization (in this example Vds of 15V and Ids of 0.2A / mm).
• the upper part illustrates the gate of the transistor and the pad deposited on the passivation layer.
• the lower part illustrates the value of the component along x of the electric field in the channel F x (x) _Canal as a function of x, and as a function of different thicknesses of the passivation layer.
• FIG. 5 illustrates the effect of the metal pad on the electric field in the channel for a transistor operating at a voltage V ds A x of 40V and V gs A x of - 9V.
• the upper part illustrates the gate of the transistor and the pad deposited on the passivation layer.
• the lower part illustrates the value of the component along x of the electric field in the channel F x (x) _Canal as a function of x, and as a function of different thicknesses of the passivation layer.
• FIG. 6 illustrates the evolution of the component of the electric field along z in the barrier Fz (z) _Bar as a function of z.
• FIG. 7 illustrates a first preferred option of grid-pad connection "from above” in which the first metallic connection electrically connects the grid and the metallic pad by making a direct connection.
• FIG. 8 illustrates a first alternative of a second option in which the connection between the gate and the pad is capacitive, in which the connection is made through the passivation layers.
• FIG. 9 illustrates a second alternative of the second option in which the connection between the gate and the pad is capacitive, in which the connection is made through the layer PL2 on the metal pad side, the contact on the gate side being direct therewith.
• FIG. 10 illustrates a “planar” grid-pad connection mode in which the metal pad is connected to the grid bus.
• Figure 11 illustrates a variant of the grid-pad connection mode of Figure 10 in which a second metal connection connects the gate and the metal pad on the side opposite to the gate bus.
• the high mobility field effect transistor 100 is illustrated in Figure 3. It comprises a stack 10 along a Z axis deposited on a substrate 11 which comprises:
• a buffer layer 12 comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first forbidden band (typically GaN),
• a barrier layer 13 comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second forbidden band, the second forbidden band being greater than the first forbidden band (typically of IhAIN, or of AIGaN or InAIGaN),
• a thin layer 15 of AIN (typically 1 to 2 nm thick) is added between the buffer layer 12 and the barrier 13 to increase the electron density and the electronic mobility in the channel.
• the transistor also conventionally comprises a source S, a drain D, and a gate G deposited on an upper face 14 of the barrier layer 13 between the source S and the drain D.
• the S / G / D alignment defines the X axis of interest for the component.
• the gate has for example a rectangular, or T, or G shape.
• the transistor according to the invention is configured to operate at high frequency, typically between 10 and 80 GHz.
• the distance between the source and the drain ds D (along the X axis) must be less than or equal to 4 miti, with a gate length Lg (along the X axis) less than or equal to 0.5 pm.
• the transistor comprises a first dielectric layer PL1 (passivation layer) deposited at least on the upper surface 14 of the barrier layer 13 between the gate G and the drain D and between the gate G and the source S.
• this passivation layer has a particular thickness in the transistor according to the invention.
• the transistor according to the invention also comprises a metal pad PM arranged between the gate G and the drain D.
• the metal PM pad is arranged between the gate G and the drain D, and deposited on the first dielectric layer PL1.
• the metal pad is electrically connected to the grid. As described below, this pad has an effect on the electric field located at the foot of the grid on the drain side.
• the source, the drain and the gate are commonly referred to as an electrode, and the PM pad can be assimilated according to this designation to a fourth electrode.
• the PM stud is made of metal, typically Au.
• the passivation layer PL1 In relation to the presence of the pad, the passivation layer PL1 according to the invention has a relative permittivity er and a thickness e such: 0.5 nm ⁇ e / er ⁇ 2 nm (1)
• the upper limit of the parameter e / 8r is determined by simulation (see below).
• the ratio e / e r cannot either have a value less than 0.5 nm because the electric field in this passivation under the PM pad would exceed the breakdown field of the material, which would degrade this passivation PL1.
• the relative permittivity er is between 3 and 10.
• these permittivity values correspond to the most technologically mature materials.
• These preferential permittivity values then lead to a thickness of the passivation layer e of between 1.5 nm and 20 nm.
• zone 30 is the critical zone of the component.
• the electric field is intense there, and, since there is a high density of dislocations in this barrier 13, due to the phenomenon of reverse piezoelectricity, it is a zone of component failure.
• the component of the field along x in the channel is called Fx_canal.
• the channel is located in the buffer layer (Buffer) a few nm from the interface with the barrier or layer 15 when it is present.
• zone 31 illustrates the location of a new electric field at the foot of the PM pad.
• a 4th electrode (PM) very close to the barrier and separated from it by a PL1 passivation, makes it possible to reduce the intensity of the electric field at the base of the grid, in the channel and the barrier, by deporting it to the foot of this 4th electrode which, being isolated from the barrier and its defects by passivation, eliminates this cause of failure.
• the distance from the gate to the source is 0.7 ⁇ m and the distance from the gate to the drain 1.4 ⁇ m, the length of the gate Lg is 110 nm.
• the PM pad has a length Lp of 75 nm and is located 800 nm from the gate foot located on the drain side (see scale along x in Figures 4 and 5).
• FIG. 4 corresponds to the behavior of the field when the component is at the point of polarization (point of rest) with the parameters:
• the charge density ns (fixed by the materials used) imposes the maximum operating voltage V ds A x which can be applied to the transistor, this operating voltage V ds having to be less than V ds A x ⁇
• a layer PL1 of Si 3 N 4 (usual case) of relative permittivity equal to 7.5 and of variable thickness e is chosen.
• the two curves C1 and CT illustrate the field F x (x) _Channel without pad (the thickness e of the layer PL1 is then without influence).
• the following curves integrate the presence of a PM stud.
• Curves C5 and C5 ′ correspond to a thickness e of PL1 of 5 nm
• curves C15 and C15 ′ correspond to a thickness of PL1 of 15 nm
• curves C25 and C25 ′ to a thickness of PL1 of 25 nm.
• the length of the Lg gate determines the maximum operating frequency of the transistor. In order not to degrade too much the performance of the transistor (particularly the gain), the PM pad must not have too great a length Lp because this would lead to a degradation of the power gain of the transistor.
• Lp was appropriate for Lp to be less than or equal to 2 times the gate length Lg (along the X alignment axis). The criterion is that beyond this length of the stud of 2 times Lg we lose more than 1dB on the gain.
• FIG. 6 illustrates an additional beneficial effect of the torque (PM pad, PL1 with low R).
• Figure 6 illustrates the evolution of the component of the field electrical according to z in barrier 13 Fz (z) _Bar as a function of z (point 0 corresponds to the start of additional layer 15).
• An excessive value of the Fz (z) _Bar field is the cause of component failures, following the deformation of the crystal lattice via the stresses induced by the inverse piezoelectric effect. These failures result in the creation of parasitic conduction paths between the gate and the 2DEG channel leading to a degradation of the microwave performance of the transistor.
• the PM pad is not too stuck to the gate or to the drain. If the PM pad is too close to the drain contact this results in an increase in Cgd and therefore a reduction in the gain and if it is placed too close to the gate, this becomes difficult to achieve. In addition, if the bridge connecting the grid and the PM pad is not long enough, this will result in a grid resistance that is too large.
• the pad-drain distance is greater than or equal to 300 nm and the pad-gate distance is greater than or equal to 200 nm.
• the metal pad PM is electrically connected to the gate G via a metal connection. Different connection mode examples are described below.
• a first connection mode "from above” is illustrated in Figures 7 to 9.
• the metal pad is electrically connected to the grid by a first metal connection.
• the first metal connection 60 electrically connects the gate G and the metal pad PM by making a direct connection (of the resistive type with as low a resistance as possible).
• a direct connection of the resistive type with as low a resistance as possible.
• the transistor further comprises a second dielectric layer PL2 deposited at least on the metal pad PM, the first metal connection 61 being in contact with said second dielectric layer PL2 deposited on the pad PM .
• the metal pad and the grid are then connected by a capacitive connection.
• the PL1 layer typically covers the grid and the PL2 layer covers the pad and the grid as illustrated in Figures 8 and 9.
• the capacitive connection between G and PM is made through PL1 and PL2 on the gate side G and through PL2 on the metal pad side PM.
• the first metal connection 61 is in contact with the part of the second dielectric layer PL2 deposited on the gate.
• the capacitive connection between G and PM is made through PL2 on the metal pad side, the contact on the gate side being direct therewith, an opening having been made on the gate cap.
• the first metal connection 61 is then in electrical contact with the grid.
• the pad have a relatively low resistance, typically comparable to the electrical resistance of the grid or less.
• the sum of the sections ⁇ S is defined equal to the sum of the section of the grid SQ, of the section of the PM SPM pad and of the section of the connection 60 or 61.
• the section of these different elements is defined in the OXZ plane, plane perpendicular to the flow of the grid current.
• ⁇ S must be greater than or equal to 2 times the section of the grid. If these different elements are made of the same metal, this guarantees that the resistance of the assembly (grid + bridge / connection 60 or 61 + PM pad) is at least less than or equal by a factor of 2 to that of the grid alone (case reference without PM stud).
• the gates are connected together via a G-bus grid bus and the drains are connected together via a G-bus.
• D-bus drain located in a plane P1.
• the sources are interconnected with a “source bridge” PS passing over a passivation layer and located in a plane P2 above P1.
• the metal pad PM is connected to the gate bus G-Bus by one of its ends, PM and G are thus both connected to the gate bus.
• FIG. 10 illustrates this mode of connection for a set 100 of transistors in which a transistor shares with the adjacent transistor alternately a source and a drain. This connection is easy to make technologically, it can be resistive or capacitive.
• a second metal connection 62 connects the gate and the metal pad on the side opposite the gate bus G-bus through the end of the PM pad opposite the gate bus. This allows the gate resistance to be reduced by a factor of 2 which is advantageous for the gain of the transistor.

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• 2019
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