EP4052393A2 - Mesures permettant une poursuite de canal lors de transmissions numériques - Google Patents

Mesures permettant une poursuite de canal lors de transmissions numériques

Info

Publication number
EP4052393A2
EP4052393A2 EP20796542.7A EP20796542A EP4052393A2 EP 4052393 A2 EP4052393 A2 EP 4052393A2 EP 20796542 A EP20796542 A EP 20796542A EP 4052393 A2 EP4052393 A2 EP 4052393A2
Authority
EP
European Patent Office
Prior art keywords
bits
block
sequence
error correction
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20796542.7A
Other languages
German (de)
English (en)
Inventor
Gerd Kilian
Jakob KNEISSL
Raimund Meyer
Frank Obernosterer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP4052393A2 publication Critical patent/EP4052393A2/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0086—Unequal error protection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0224—Channel estimation using sounding signals
    • H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
    • H04L25/023—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols
    • H04L25/0236—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols using estimation of the other symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03286—Arrangements for operating in conjunction with other apparatus with channel-decoding circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03292—Arrangements for operating in conjunction with other apparatus with channel estimation circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes

Definitions

  • Embodiments of the present invention relate to a data transmitter, a data receiver, a communication system and corresponding methods which enable channel tracking during the transmission of data. Some exemplary embodiments relate to measures to enable channel tracking in the case of digital transmission.
  • the present invention is therefore based on the object of improving the existing situation.
  • Embodiments create a data transmitter of a [eg wireless] communication system, wherein the data transmitter is configured to receive a data bit sequence [eg N data bits] [eg generate or receive from a device connected to the data transmitter [eg a sensor]], the The data transmitter is configured to carry out forward error correction coding based on the data bit sequence in order to generate a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits [eg a sequence of error correction bits; eg M error correction bits], the data bit sequence and the sequence of systematic bits being identical, wherein the data transmitter is configured to transmit a signal, the signal having a first transmit bit block and a second transmit bit block, the first transmit bit block [e.g.
  • the block of systematic bits comprises a real subset of the systematic bits of the sequence of systematic bits.
  • the at least one block of contiguous error correction bits each comprises a real subset of the error correction bits.
  • the data transmitter is configured to take over the sequence of systematic bits unchanged and coherent in the order in the first transmission bit block.
  • the sequence of reference bits is known to the data transmitter, the data transmitter being configured to transfer the sequence of reference bits unchanged in the sequence and coherently into the first transmission bit block.
  • the first transmission bit block is structured in accordance with a communication protocol or communication standard.
  • the communication protocol / communication standard can be the wireless M-Bus.
  • the Wireless M-Bus is defined in the European standard EN 13757.
  • the wireless M-Bus is defined in the German standard DIN EN 13757-4 "Communication systems for meters and their remote reading - Part 4: Meter reading via radio (remote reading of meters in the SRD band").
  • the first transmission bit block can be received independently of the second transmission bit block by a data receiver that operates in accordance with the communication protocol or communication standard.
  • the second block of transmit bits goes beyond the communication protocol or standard.
  • the second transmit bit block follows the first transmit bit block [e.g. temporal].
  • the first transmit bit block and the second transmit bit block [e.g. temporally] arranged immediately adjacent to one another.
  • the forward error correction coding is turbo coding, LDPC coding or convolutional coding.
  • the second transmission bit block has at least one sequence of additional reference bits.
  • a sequence of additional reference bits [e.g. in addition to the sequence of reference bits of the first transmission bit block] the at least one sequence of additional reference bits is arranged in the second transmission bit block in such a way that the sequence of additional reference bits is arranged adjacent to the first transmission bit block.
  • the sequence of additional reference bits can be arranged at a start or end of the second transmission bit block, so that the sequence of additional reference bits is arranged adjacent to the first transmission bit block.
  • the data transmitter is configured to carry out a first forward error correction coding for a first block of the data bit sequence [e.g. first block of contiguous data bits] [e.g. wherein the first block of the data bit sequence comprises part of the data bit sequence] to a first block of systematic bits and at least one block of contiguous error correction bits assigned to the first block of systematic bits, wherein the data transmitter is configured to provide a second forward error correction coding for a second block of the data bit sequence [e.g.
  • the data transmitter is configured to take over the respective blocks of contiguous error correction bits in the order unchanged and contiguous in the second transmission bit block.
  • the respective blocks are contiguous
  • the respective blocks are contiguous
  • Error correction bits are only nested within themselves.
  • the second transmit bit block comprises a sequence of additional reference bits [e.g. in addition to the sequence of reference bits of the first transmission bit block], the sequence of additional reference bits being arranged immediately adjacent to a block of contiguous error correction bits which is assigned to a block of the data bit sequence which is arranged at the beginning of the data bit sequence.
  • the data transmitter is configured to transmit a third forward error correction coding for a third block of the data bit sequence [e.g. third block of contiguous data bits] to obtain a third block of systematic bits and at least one block of contiguous error correction bits associated with the third block of systematic bits, the first forward error correction coding and the second forward error correction Coding and the third forward error correction coding are carried out independently of one another, blocks of contiguous error correction bits that are assigned to immediately adjacent blocks of the data bit sequence being arranged immediately adjacent or with only a block of reference bits in between in the second transmit bit block.
  • a third forward error correction coding for a third block of the data bit sequence [e.g. third block of contiguous data bits] to obtain a third block of systematic bits and at least one block of contiguous error correction bits associated with the third block of systematic bits
  • the first forward error correction coding and the second forward error correction Coding and the third forward error correction coding are carried out independently of one another, blocks of contiguous error correction bits that are assigned to immediately adjacent blocks
  • the at least one block of contiguous error correction bits that is assigned to the first block of systematic bits is a first block of contiguous error correction bits
  • the at least one block of contiguous error correction bits that is assigned to the second block of systematic bits is a second Block of contiguous error correction bits.
  • the first forward error correction coding for the first block of the data bit sequence the first block of systematic bits and a first block of contiguous error correction bits, which is assigned to the first block of systematic bits, arise, with the second forward error correction Coding for the second block of the data bit sequence, the second block of systematic bits and a second block of contiguous error correction bits, which is assigned to the second block of systematic bits, can arise.
  • the at least one block of contiguous error correction bits associated with the first block of systematic bits comprises a first block of contiguous error correction bits and a second block of contiguous error correction bits
  • the at least one block of contiguous error correction bits corresponding to the second block of systematic Bits is assigned comprises a third block of contiguous error correction bits and a fourth block of contiguous error correction bits.
  • the first block of systematic bits and a first block of contiguous error correction bits and a second block of contiguous error correction bits that are assigned to the first block of systematic bits can arise, wherein in the second forward error correction coding for the second block of the data bit sequence, the second block of systematic bits and a third block of contiguous error correction bits and a fourth block of contiguous error correction bits, which are assigned to the second block of systematic bits, can arise.
  • blocks of contiguous error correction bits which are assigned to immediately adjacent blocks of systematic bits, are arranged in the second transmission bit block in the second transmission bit block, or with only one block of reference bits in between, are arranged in the second transmission bit block.
  • a block of reference bits is arranged in the second transmit bit block between blocks of contiguous error correction bits which are assigned to the same block of the data bit sequence [e.g. brought in].
  • the blocks of contiguous error correction bits assigned to a respective block of the data bit sequence are arranged in the second transmission bit block in such a way that each of these blocks of contiguous error correction bits is directly adjacent to a sequence of additional reference bits or another block of contiguous error correction bits corresponding to one of the respective block of Data bit sequence is assigned to the preceding block of the data bit sequence, is arranged.
  • the first block of contiguous error correction bits in the second transmission bit block is arranged immediately adjacent to a first sequence of additional reference bits
  • the third block of contiguous error correction bits is arranged immediately adjacent to the first block of contiguous error correction bits
  • the second block of contiguous Error correction bits is arranged in the second transmission bit block immediately adjacent to a second sequence of additional reference bits
  • the fourth block of contiguous error correction bits is arranged immediately adjacent to the second block of contiguous error correction bits.
  • a sequence of additional reference bits is arranged in the second transmission bit block between the first block of contiguous error correction bits and the second block of contiguous error correction bits, the third block of contiguous error correction bits being arranged directly adjacent to the first block of contiguous error correction bits, the fourth Block of contiguous error correction bits is arranged immediately adjacent to the second block of contiguous error correction bits.
  • a first sequence of additional reference bits is arranged in the second transmission bit block between the first block of contiguous error correction bits and the second block of contiguous error correction bits, with a second sequence of additional reference bits between the third block of contiguous error correction bits and the fourth in the second transmission bit block Block of contiguous error correction bits is arranged.
  • the first block of contiguous error correction bits and the second block of contiguous error correction bits are arranged immediately adjacent to spaced-apart sequences of additional reference bits in the second transmit bit block
  • the third block of contiguous error correction bits and the fourth block of contiguous error correction bits immediately in the second transmit bit block are arranged adjacent to spaced apart sequences of additional reference bits.
  • a data transmitter of a [eg wireless] communication system that is configured to receive a data bit sequence [eg N data bits] [eg to generate or from a device connected to the data transmitter [eg a sensor]], wherein the data transmitter is configured to divide the data bit sequence into at least two blocks, wherein the data transmitter is configured to carry out an independent forward error correction coding based on a respective block of the data bit sequence in order to in each case one block of systematic bits and in each case at least one block of contiguous error correction bits which is assigned to the respective block of systematic bits, the respective block of systematic bits being identical to the respective block of the data bit sequence, the data transmitter being configured to transmit a signal , wherein the signal comprises a first transmission bit block and a second transmission bit block, wherein the first transmission bit block comprises a sequence of reference bits and the data bit sequence or a concatenated version of the respective blocks of systematic bits, the concatenated version of the respective blocks of systematic bits and the data bit sequence are identical, the second transmission bit block block
  • a data transmitter of a [e.g. wireless] communication system wherein the data transmitter is configured to transmit a data bit sequence [e.g. N data bits] [e.g. or from a device connected to the data transmitter [e.g. a sensor]], wherein the data transmitter is configured to perform forward error correction coding based on the data bit sequence to generate a sequence of systematic bits and error correction bits associated with the sequence of systematic bits [e.g. a sequence of error correction bits; e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical, the data transmitter being configured to transmit a signal, the signal comprising a first transmission bit block and a second transmission bit block, the first transmission bit block being a [e.g.
  • the block of systematic bits comprises a real subset of the systematic bits of the sequence of systematic bits.
  • the at least one group of error correction bits each comprises a real subset of the error correction bits.
  • the data transmitter is configured to carry out the forward error correction coding step by step, so that a respective group of error correction bits of the error correction bits is produced in each step of the forward error correction coding.
  • a block of systematic bits of the sequence of systematic bits together with a first group of error correction bits, which arises in a first step of the forward error correction coding can be decoded, independently of another group of error correction bits in one of the subsequent steps the forward error correction coding arises.
  • groups of error correction bits following the first group of error correction bits which arise in the steps of the forward error correction coding following the first step of the forward error correction coding, are only possible together with groups of error correction bits that were used in the preceding steps of the forward error correction.
  • Error correction coding was created and, together with the blocks of systematic bits assigned to the respective groups of error correction bits, can be decoded independently of another group of error correction bits that arise in one of the subsequent steps of the forward error correction coding.
  • the forward error correction coding is convolutional coding or LDPC coding.
  • a respective group of error correction bits is arranged in the second transmission bit block adjacent to a sequence of additional reference bits or adjacent to a group of error correction bits, which in a step of the forward direction immediately preceding the step in which the respective group of error correction bits arose. Error correction coding came into being.
  • error correction bits of a respective group of error correction bits are arranged in the second transmission bit block in such a way that each of these error correction bits is arranged immediately adjacent to reference bits or immediately adjacent to another error correction bit of the same group of error correction bits or directly adjacent to an error correction bit of another group of error correction bits in a step of the forward error correction coding immediately preceding the step in which the respective group of error correction bits was created.
  • a data transmitter of a [eg wireless] communication system configured to receive a data bit sequence [eg N data bits] [eg generate or receive from a device connected to the data transmitter [eg sensor]], the data transmitter is configured to perform forward error correction coding based on the data bit sequence in order to generate a sequence of systematic bits and error correction bits associated with the sequence of systematic bits [eg a sequence of error correction bits; eg M error correction bits], the data bit sequence and the sequence of systematic bits being identical, the data transmitter being configured to transmit a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block being a first sequence of Reference bits, the sequence of systematic bits and a second sequence of reference bits, wherein the sequence of systematic bits is interrupted by the second sequence of reference bits, so that a first part of the sequence of systematic bits [eg temporally] before the second sequence of reference bits is arranged and a second part of the sequence of systematic bits [eg temporally] is arranged
  • the data transmitter is configured to take over the respective parts of the sequence of systematic bits in the order unchanged and coherently in the first transmission bit block.
  • a data receiver of a [eg wireless] communication system the data receiver being configured to receive a signal which has a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, wherein the sequence of systematic bits is identical to a data bit sequence to be transmitted with the signal, the second transmission bit block having error correction bits assigned to the sequence of systematic bits, the data receiver being configured to carry out a channel estimation based on the received sequence of reference bits, the Data receiver is configured to send a sequence containing a received block of [e.g.
  • the data receiver is configured to carry out a forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits assigned to the reencoded block of systematic bits, wherein the data receiver is configured to carry out the channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.
  • a data receiver of a [wireless] communication system the data receiver being configured to receive, in a first mode, a first signal having a first transmission bit block, the first transmission bit block having a sequence of reference bits and a data bit sequence
  • the data receiver is configured to receive, in a second mode, a second signal comprising a first transmit bit block and a second transmit bit block, the first transmit bit block comprising a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits is identical to a data bit sequence to be transmitted with the second signal, the second transmission bit block having error correction bits assigned to the sequence of systematic bits
  • the data receiver being configured to carry out a channel estimation based on the received sequence of reference bits
  • the data reception r is configured to be a sequence comprising a received block of [e.g.
  • the data receiver is configured to carry out a forward error coding for the block of the data bit sequence to a reencoded block of systematic bits and at least one to obtain reencoded block of error correction bits associated with the reencoded block of systematic bits, wherein the data receiver is configured to generate a channel estimate based on the reencoded block of systematic bits and the at least one reencoded Blo ck to track error correction bits.
  • the received block of systematic bits comprises a real subset of the systematic bits of the received sequence of systematic bits.
  • the at least one received block of contiguous error correction bits each comprises a real subset of the received error correction bits.
  • the first transmission bit block is according to a communication protocol or communication standard [e.g. Wireless-M-Busj established.
  • the second transmission bit block goes beyond the communication protocol or the communication standard.
  • the second transmit bit block follows the first transmit bit block [e.g. temporal].
  • the first transmit bit block and the second transmit bit block [e.g. temporally] arranged immediately adjacent to one another.
  • the forward error correction coding is turbo coding, LDPC coding or convolutional coding.
  • the sequence of systematic bits comprises a first block of systematic bits and a second block of systematic bits, the error correction bits at least one block of contiguous error correction bits assigned to the first block of systematic bits and at least one block of related error correction bits assigned to the second block of systematic bits contiguous error correction bits.
  • the second transmission bit block comprises at least one sequence of additional reference bits
  • the data receiver is configured to update or restart the channel estimation based on the sequence of additional reference bits
  • the data receiver is configured to perform the channel estimation based on at least one of the blocks of error correction bits, which is arranged immediately adjacent to the sequence of additional reference bits, to be tracked
  • a data receiver of a [e.g. wireless] communication system wherein the data receiver is configured to receive a signal comprising a first transmission bit block and a second transmission bit block, the first transmission bit block comprising a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to a data bit sequence to be transmitted with the signal, the second transmission bit block having error correction bits assigned to the sequence of systematic bits, the data receiver being configured to carry out a channel estimation based on the received sequence of reference bits, the data receiver being configured to generate a sequence, which received a block of [eg contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits, which is assigned to the received block of systematic bits, independently of other received error correction bits or received groups of error correction bits to decode to a block of the data bit sequence the data receiver is configured to carry out a forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and a
  • Further exemplary embodiments create a communication system with a data transmitter according to one of the exemplary embodiments described herein and a data receiver according to one of the exemplary embodiments described herein. Further exemplary embodiments provide a communication system with a first data transmitter which is configured to receive a data bit sequence and to transmit a first signal which has only a first transmission bit block, the first transmission bit block being a sequence of reference bits and the data bit sequence received from the first data transmitter having; a second data transmitter like one of the exemplary embodiments described herein, which is configured to transmit a second signal; and a data receiver like one of the exemplary embodiments described herein.
  • the first data transmitter does not transmit a second transmission bit block with error correction bits for the data bit sequence received.
  • the respective first transmission bit block is structured in accordance with a communication protocol or communication standard, the second transmission bit block going beyond the communication protocol or the communication standard.
  • the second transmission bit block is not taken into account by the data receiver.
  • the data receiver operates in accordance with a communication protocol or communication standard, the respective first transmission bit block being structured in accordance with the communication protocol or communication standard, the second transmission bit block going beyond the communication protocol or the communication standard.
  • the data receiver is a first data receiver, the communication system having a second data receiver like one of the exemplary embodiments described herein.
  • the method includes a step of obtaining a data bit sequence.
  • the method further comprises a step of performing, based on the data bit sequence, forward error correction coding in order to generate a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits [e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical.
  • the method further comprises a step of transmitting a signal, the signal comprising a first block of transmit bits and a second block of transmit bits, the first block of transmit bits [e.g. known to a data receiver] comprises a sequence of reference bits and the sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of [e.g. contiguous] systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the error correction bits, which is assigned to the block of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits.
  • the method includes a step of obtaining a data bit sequence.
  • the method further comprises a step of performing, based on the data bit sequence, forward error correction coding in order to generate a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits [e.g. Error correction bits], the data bit sequence and the sequence of systematic bits being identical.
  • the method further comprises a step of transmitting a signal, the signal comprising a first block of transmit bits and a second block of transmit bits, the first block of transmit bits [e.g. known to a data receiver] comprises a sequence of reference bits and the sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of [e.g. related] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits can be decoded from the error correction bits, independently of other error correction bits or other groups of error correction bits.
  • the method includes a step of obtaining a data bit sequence. It also includes The method includes a step of performing, based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and the sequence of systematic bits associated with error correction bits [eg M error correction bits], the data bit sequence and the sequence of systematic bits being identical are.
  • error correction bits eg M error correction bits
  • the method further comprises a step of transmitting a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits is interrupted by the second sequence of reference bits, so that a first part of the sequence of systematic bits is arranged before the second sequence of reference bits and a second part of the sequence of systematic bits is arranged after that of the second Sequence of reference bits is arranged, the second transmission bit block having the error correction bits, wherein a block of [eg contiguous] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits from the error correction bits can be decoded, regardless of other error correction turbits or other groups of error correction bits.
  • the method comprises a step of receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block comprising a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to one to be transmitted with the signal Is a data bit sequence, the second transmission bit block having error correction bits assigned to the sequence of systematic bits.
  • the method further comprises a step of performing a channel estimation based on the received sequence of reference bits.
  • the method further comprises a step of decoding a sequence which contains a received block of [e.g.
  • contiguous] systematic bits of the received sequence of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits that is assigned to the received block of systematic bits comprises decoding independently of other received error correction bits or received blocks of error correction bits in order to obtain a block of the data bit sequence.
  • the method further comprises a step of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and at least one reencoded block of systematic bits and error correction bits assigned to the reencoded block of systematic bits, Tracking the channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.
  • the method comprises a step of receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to one to be transmitted with the signal Is a data bit sequence, the second transmission bit block having error correction bits assigned to the sequence of systematic bits.
  • the method further comprises a step of performing a channel estimation based on the received sequence of reference bits.
  • the method further comprises a step of decoding a sequence comprising a received block of [e.g.
  • the method further comprises a step of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits.
  • the method further comprises a step of updating the channel estimation based on the reencoded block of systematic bits and the reencoded group of error correction bits.
  • the method comprises a step of receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits being through the second sequence of reference bits is interrupted, so that a first part of the sequence of systematic bits is arranged before the second sequence of reference bits and a second part of the sequence of systematic bits is arranged after that of the second sequence of reference bits is arranged, the second transmission bit block having the error correction bits.
  • the method further comprises a step of performing a channel estimation based on the received first sequence of reference bits and the received second sequence of reference bits.
  • the method further comprises a step of decoding a sequence which to decode a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits, which is assigned to the received block of systematic bits, independently of other received error correction bits or received groups of error correction bits to get a block of the data bit sequence.
  • the method further comprises a step of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits.
  • the method further comprises a step of updating the channel estimation based on the reencoded block of systematic bits and the reencoded group of error correction bits.
  • FIG. 1 shows a schematic block diagram of a system with one or more
  • FIG. 2 shows a schematic view of an arrangement of a sequence of reference bits and a data bit sequence with the data bits as it is used as a transmission bit sequence to be transmitted in a simple transmission system without forward error correction;
  • FIG. 3 shows a schematic view of a generation of a transmission signal with the transmission bit sequence to be transmitted without forward error correction (coding) from FIG. 2;
  • FIG. 4 shows a schematic view of a generation of a transmission signal with a transmission bit sequence to be transmitted with forward error correction and interleaving
  • FIG. 5 shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence;
  • Fig. 6 is a schematic view of an internal structure of turbo coding; 7 shows a schematic view of a generation of a to be transmitted
  • Transmission bit sequence with error correction bits based on turbo coding the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence
  • FIG. 8 shows a schematic view of a generation of a to be transmitted
  • Blocks of coded bits e.g. coded partial sequences which are individually coded, as well as an iterative channel tracking based on the blocks of coded bits;
  • FIG. 11 shows a schematic view of a generation of a to be transmitted
  • FIG. 12 shows a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block from FIG. 11 and a second transmission bit block which, compared to FIG. 11, has a different arrangement of the blocks of error correction bits and which has a sequence 320 of additional reference bits;
  • FIG. 13 shows a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block from FIG. 11 and a second transmission bit block which precedes the first transmission bit block;
  • Transmission bit sequence only the step of inserting a sequence of additional reference bits in the second transmission bit block of the transmission bit sequence being shown in FIG. 15 which differs from the step of inserting a sequence of additional reference bits shown in FIG. 14;
  • 16 shows a schematic view of a generation of a to be transmitted
  • Transmission bit sequence only the step of inserting a plurality of sequences of additional reference bits in the second transmission bit block of the transmission bit sequence being shown in FIG. 16, which step differs from the step of inserting a sequence of additional reference bits shown in FIG. 14;
  • FIG. 17 shows a schematic view of a resulting transmission bit sequence after the introduction of three sequences of additional reference bits, a distance between blocks of error correction bits which are assigned to the same block of the transmission bit sequence being enlarged compared with FIG. 16;
  • 19 is a schematic view of an iterative forward error correction coding of a data bit sequence
  • Transmission bit sequence with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence;
  • 21 shows a schematic view of a generation of a to be transmitted
  • Transmission bit sequence with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence; 22 shows a schematic view of a generation of a to be transmitted
  • Transmission bit sequence with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence;
  • FIG. 24 shows a flow diagram of a method for transmitting a signal, according to a first exemplary embodiment
  • 25 shows a flow diagram of a method for sending a signal, according to a second exemplary embodiment
  • 26 shows a flow diagram of a method for transmitting a signal, according to a third exemplary embodiment
  • FIG. 27 shows a flow diagram of a method for receiving a signal, according to a first exemplary embodiment
  • 29 shows a flow diagram of a method for receiving a signal, according to a third exemplary embodiment.
  • FIG. 1 shows a schematic block diagram of a communication system with one or more data transmitters 100_1-100_n, n s 1, and a data receiver 110.
  • a data transmitter for example the data transmitter 100_1
  • a data transmitter 100_1 can be designed to send a signal 120 (for example a first signal) with data to be transmitted (for example a data packet) to the data receiver 110.
  • the Data receiver 110 can be configured to receive signal 120 in order to receive the data.
  • a further data transmitter e.g. the data transmitter 100_2
  • the data receiver 110 can be designed to receive the further signal 122 in order to receive the data.
  • a data transmitter such as the data transmitter 100_1, for example, can have a transmission device (or transmission module or transmitter) 102 which is designed to transmit the signal 120.
  • the transmission device 102 can be connected to an antenna 104 (or an antenna array) of the data transmitter 100_1.
  • the data transmitter 100_1 can also have a receiving device (or receiving module, or receiver) 106 which is designed to receive a signal.
  • the receiving device 106 can be connected to the antenna 104 or a further (separate) antenna (or a (separate) antenna array) of the data transmitter 100_1.
  • the data transmitter 100_1 can also have a combined transceiver.
  • the data receiver 110 can have a receiving device (or receiving module, or receiver) 116, which is designed to receive the signal 120.
  • the receiving device 116 can be connected to an antenna 114 (or an antenna array) of the data receiver 110.
  • the data receiver 110 can furthermore have a transmission device (or transmission module, or transmitter) 112, which is designed to transmit a signal.
  • the transmitting device 112 can be connected to the antenna 114 or a further (separate) antenna (or a (separate) antenna array) of the data receiver 110.
  • the data receiver 110 can also have a combined transceiver.
  • the data transmitter 100_1 can be a participant in the communication system, such as an end point or a sensor node (eg heating meter), while the data receiver 110 can be a base station of the communication system.
  • a communication system comprises at least one data receiver 110 (eg base station) and a multiplicity of data transmitters 100_1-100_n (eg subscribers).
  • the data transmitter 100_1 is a base station of the communication system, while the data receiver 110 is a subscriber in the communication system.
  • both the data transmitter 100_1 and the data receiver 110 can be participants in the communication system. Further it is possible that both the data transmitter 100_1 and the data receiver 110 are base stations of the communication system.
  • a data packet with useful data to be transmitted is often transmitted without error protection, ie without coding introducing redundancy.
  • di, d2, ... d N denote a sequence of N data bits to be transmitted (or a data bit sequence).
  • This sequence can, among other things, already contain check bits of a cyclic redundancy check (also CRC bits), which are not included in the forward error correction coding in the context of this description.
  • the data bits are preceded by a reference sequence (also preamble, training sequence or synchronization sequence) which the receiver knows in advance, as described in Fig. 2 is shown.
  • a reference sequence also preamble, training sequence or synchronization sequence
  • Fig. 2 shows a schematic view of an arrangement of a sequence 201 of reference bits ri, r2, ... ri. And a data bit sequence 202 with the data bits di, d2, ... d N , as they are to be transmitted as a transmission bit sequence (e.g. Data packet) is used in a simple transmission system without forward error correction (coding).
  • a transmission bit sequence e.g. Data packet
  • the receiver detects the transmitted reference sequence 201 (e.g. sequence of reference bits), it interprets the subsequent received signal section as the signal belonging to the data bits (e.g. the data bit sequence 202) and demodulates this in order to recover the transmitted data bits.
  • the reference sequence 201 serves, on the one hand, to detect (locate) a transmission signal; in the case of coherent demodulation, the reference sequence 201 also allows channel estimation (which is the prerequisite for coherent demodulation).
  • FIG. 3 shows a schematic view of the generation of a transmission signal with the transmission bit sequence to be transmitted without forward error correction (coding) from FIG. 2.
  • a first step 210 the sequence 201 of reference bits is mapped (for example bit-to-symbol assignment) to reference symbols 212 and the data bit sequence 201 to data symbols 214.
  • the reference symbols 212 and data symbols 214 are modulated in order to obtain a reference signal 218 and a data signal 220.
  • a reference signal 218 can also be generated “directly” without it being able to be derived from a sequence of explicitly specified reference bits.
  • the user data to be transmitted (e.g. data bit sequence 202) is therefore subjected to coding in the form of forward error correction (FEC) before being transmitted.
  • FEC forward error correction
  • the coded bits are usually subjected to an interleaving. After interleaving, originally adjacent coded bits are usually further apart in the sequence than originally. 4 shows the corresponding method steps of such an efficient transmission system.
  • FIG. 4 shows a schematic view of the generation of a transmission signal with a transmission bit sequence to be transmitted with forward error correction and interleaving.
  • a first step 208 based on a data bit sequence 202 (e.g. sequence of data bits), forward error coding takes place in order to obtain a sequence 203 of coded bits.
  • the coded bits of the sequence 203 of coded bits are interleaved in order to obtain a sequence 204 of interleaved, coded bits.
  • a sequence 201 of reference bits is mapped (for example, bit-to-symbol assignment) to reference symbols 212 and the sequence 204 of interleaved, coded bits to data symbols 214.
  • reference symbols 212 and 212 are modulated Data symbols 214 to obtain a reference signal 218 and a data signal 220.
  • turbo codes [2] and LDPC codes with the actually achievable channel utilization, are close to the theoretically possible channel capacity, the so-called “Shannon limit” and are therefore of enormous practical importance for highly efficient transmission systems.
  • convolutional codes are established as forward error correction, but with less efficiency. Further development of existing standards with backwards compatibility
  • the aim is to significantly increase the efficiency of data transmission systems with the help of modern processes.
  • this can advantageously be done by coding the data bits 202 to be transmitted (e.g. data bit sequence) on the basis of forward error correction. While such procedures are mostly used in the development of new standards (e.g. communication standards), backward compatibility may have to be taken into account when developing existing standards, as there is often a large number of old devices in circulation that are not impaired in their function should.
  • new standards e.g. communication standards
  • backward compatibility may have to be taken into account when developing existing standards, as there is often a large number of old devices in circulation that are not impaired in their function should.
  • FIG. 5 shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.
  • a forward error correction coding
  • M error correction bits e.g. redundancy bits
  • the sequence 306 of M error correction bits can be interleaved in order to obtain a sequence 310 of M interleaved error correction bits.
  • a sequence 201 of reference bits, the data bit sequence 202 and the sequence 310 of M interleaved error correction bits form the transmission bit sequence to be transmitted, with a first transmission bit block 200 of the transmission bit sequence comprising the sequence 201 of reference bits and the data bit sequence 202 is backwards compatible with an “existing” communication system (or communication protocol), while a second transmission bit block 300 of the transmission bit sequence, which comprises the sequence 310 of M interleaved error correction bits, extends the “existing” communication system by a forward error correction.
  • FIG. 5 schematically shows a system with coding which is backward compatible with an “old” system without coding.
  • the N data bits e.g. data bit sequence 202
  • the encoder generates the original N data bits (e.g. data bit sequence 202) in the same sequence as at the encoder input as a partial result of this coding process.
  • M redundancy bits 306 also called parity bits or error correction bits
  • the subsequent interleaving must be designed in such a way that only the redundancy bits are interleaved, while the order of the data bits (e.g. data bit sequence 202) is left unchanged. It can be seen that, according to this method according to FIG. 5, the first N bits after the reference bits correspond exactly to those of the uncoded method according to FIG. 3.
  • a receiver according to the old (uncoded) method processes the first N data bits 202 after the detection of the reference sequence and ignores the following interleaved redundancy bits 310.
  • a receiver processes according to the new method after the detection of the reference sequence 201, the entire sequence consisting of N data bits and M redundancy bits. Decoding this sequence of length M + N results in a significantly higher error tolerance in the event of faulty demodulation (bit errors) of a part of the receive sequence.
  • the concept of backward compatibility is to be understood as meaning that a new, longer sequence is transmitted (sent), the first part of which (corresponding to the reference sequence and the first N data bits) is identical to that of the original system without coding.
  • the first N bits of the coded sequence correspond exactly to the input bits of the encoder (i.e. the N data bits 202).
  • the interleaver leaves the first N bits of the coded sequence, which correspond to the N data bits 202, unchanged in their positions and only interleaves the following redundancy bits 306.
  • Any coding in which the coded bit sequence contains the data bit sequence as a subset can therefore be considered as forward error correction. This is particularly the case with turbo codes and LDPC codes.
  • Some of the exemplary embodiments described below relate to a turbo coding representative of a coding, at the output of which systematic bits and parity bits are generated. It should be noted, however, that the present invention is not limited to such exemplary embodiments. Rather, all codes that contain systematic bits as part of the coded bit sequence come into consideration, such as, inter alia. the important and practice-relevant group of LDPC codes.
  • FIG. 6 shows a schematic view of an internal structure of the turbo coding 240.
  • the so-called “systematic bits” 304 which are identical to the data bits 202 are.
  • a first sequence 306_1 of parity bits which are generated from the data bits 202 by means of a recursive convolutional code based on a first generator polynomial 242.
  • a third path produces a second sequence 306_2 of parity bits.
  • the data bits on the input side are subjected to an internal turbo code interleaving 246, whereby their order is scrambled.
  • turbo coding in contrast to the usual fading codings is that the data bits 202 on the input side represent part of the coded bit sequence on the output side (where they are referred to as systematic bits 304). This feature makes the use of turbo coding suitable for the method shown in FIG.
  • FIG. 7 shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on turbo coding, the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.
  • turbo coding can be carried out in order to obtain a sequence 304 of systematic bits and two sequences 306_1 and 306_2 of error correction bits (e.g. parity bits) assigned to the sequence 304 of systematic bits.
  • the sequence 304 of systematic bits is identical to the data bit sequence 202.
  • the two sequences 306_1 and 306_2 of error correction bits can be interleaved in order to obtain a sequence 310 of interleaved error correction bits (e.g. parity bits).
  • a sequence 201 of reference bits, the sequence 304 of systematic bits and the sequence 310 of interleaved error correction bits form the transmission bit sequence to be transmitted, with a first transmission bit block 200 of the transmission bit sequence, the sequence 201 of reference bits and the Sequence 304 comprises systematic bits, is backwards compatible with an "existing" communication system (or communication protocol), while a second transmission bit block 300 of the transmission bit sequence, which comprises the sequence 310 of interleaved error correction bits, extends the "existing" communication system by a forward error correction.
  • FIG. 7 shows an expansion of an uncoded system into an efficient system with turbo coding, the N systematic bits 304, which correspond to the data bits 202, being arranged after the reference sequence 201. Only then are the nested parity bits 310 of the turbo encoder appended. This means that on the one hand “old” receivers can continue to be used which only take into account the first N data bits 304 after the reference sequence and ignore the following bits 310. New, more powerful receivers (eg data receivers), on the other hand, process the entire sequence shown.
  • the turbo decoding used ensures a significantly increased transmission security even with heavily disturbed channels. Receivers (e.g. data receivers) with low complexity often demodulate the input signal incoherently.
  • Differential detection can be used here, depending on the modulation method used. This does not require any explicit channel estimation or channel tracking and is very robust against changes in the transmission channel, such as those that occur due to a frequency offset between transmitter (e.g. data transmitter) and receiver (e.g. data receiver) or with time-variant fading channels.
  • Forward error correction coding e.g. turbo coding or LDPC coding
  • forward error correction coding enables the data to be transmitted much more efficiently, but only develops its benefits with coherent demodulation of the received signal. This requires that channel estimation be performed. If the coherence time of a transmission channel is shorter than the duration of the transmitted transmission signal, i.e. if the channel changes significantly from the receiver's point of view during the transmission duration of the received signal, a one-time channel estimation (e.g. based on the preceding reference symbols) is no longer sufficient. Rather, a channel tracking, i.e. an update of the channel estimate at sufficiently short time intervals, is then required. The maximum permissible update period depends directly on the coherence time of the transmission channel, i.e. the time in which the channel can be viewed as approximately unchanged.
  • the channel is time-variant.
  • a frequency offset between transmitter and receiver also known as a frequency offset.
  • the physical channel itself does not necessarily have to be time-variant, but from the point of view of the receiver it is due to the frequency offset.
  • forward error correction coding e.g. turbo coding or LDPC coding
  • forward error correction coding which requires coherent demodulation to achieve the desired coding gain
  • an existing transmission standard without forward error correction e.g. according to FIG. 3
  • forward error correction coding e.g. turbo coding or LDPC coding
  • the updating of an (initial) channel estimate is referred to as channel tracking.
  • the initial channel estimation is based on a transmission symbol sequence known in advance in the receiver (referred to here as a reference (symbol) sequence or sequence of reference bits) which, for example, precedes the data sequence (preamble).
  • the channel estimation is updated in principle according to the same method, but instead of or in addition to the known reference symbols, further symbols are included in the channel estimation.
  • the exemplary embodiments described below show how a digital transmission system without forward error correction of the data can be expanded by forward error correction coding (e.g. turbo coding, LDPC coding, convolutional coding) so that the new transmission system
  • forward error correction coding e.g. turbo coding, LDPC coding, convolutional coding
  • the coding per se e.g. Turbo or LDPC
  • the basic methods of how a channel estimation is carried out in the receiver on the basis of known or estimated transmission symbols are known to the person skilled in the art, so that a detailed description of this is dispensed with.
  • one or more sequences with additional reference bits can be inserted into the sequence of interleaved error correction bits (e.g. parity bits). It is essential here to leave the area of the data bits or symbols and the preceding reference bits or symbols unchanged, as is illustrated in FIG. 8.
  • a forward error correction (coding) e.g. turbo coding
  • a forward error correction (coding) can be carried out to generate a sequence 304 of systematic bits and two sequences 306_1 and 306_2 of error correction bits assigned to the sequence 304 of systematic bits (e.g. parity bits).
  • the sequence 304 of systematic bits is identical to the data bit sequence 202.
  • a second step 308 the two sequences 306_1 and 306_2 of error correction bits can be interleaved in order to obtain a sequence 310 of interleaved error correction bits (eg parity bits).
  • a third step 312 two sequences 320_1 and 320_2 of additional reference bits can be inserted in the area of the sequence 310 of interleaved error correction bits.
  • a first sequence 320_1 of additional reference bits can be placed in front of the sequence 310 of interleaved error correction bits (eg parity bits), while a second sequence 320_2 of additional reference bits is inserted between the sequence 310 of interleaved error correction bits can be so that the sequence 310 of interleaved error correction bits is interrupted by the second sequence 320_2 of additional reference bits.
  • a first part 310_1 of the sequence 310 of interleaved error correction bits can be arranged before the second sequence 320_2 of additional reference bits, while a second part 310_2 of the sequence 310 of interleaved error correction bits can be arranged after the second sequence 320_2 of additional reference bits.
  • a first transmission bit block 200 of the transmission bit sequence to be transmitted can comprise the sequence 201 of reference bits and the sequence 304 of systematic bits
  • the second transmission bit block 300 comprises the first sequence 320_1 of additional reference bits, the first part 310_1 of the Sequence 310 of interleaved error correction bits, the second sequence 320_2 of additional reference bits and the second part 310_2 of the sequence 310 of interleaved error correction bits.
  • two sequences 320_1 and 320_2 of additional reference bits are thus inserted into the sequence 310 of the interleaved parity bits by way of example.
  • These additional reference sequences significantly shorten the maximum distance between data or parity bits and the respectively closest reference sequence compared to the case where only the preamble is used as the only reference sequence, as shown in FIG. 9.
  • FIG. 9 shows a schematic representation of the sequences of reference bits assigned for the channel estimation for the transmission bit sequence to be transmitted from FIG. 8.
  • a channel estimation for a first part of the systematic bits 304 based on the Sequence 201 of reference bits of the first send bit block 200 take place, while a channel estimation for a second part of the systematic bits 304 based on the first sequence 320_1 of additional reference bits of the second send bit block 300 can be carried out.
  • a channel estimate for a first part of the first part 310__1 of the sequence 310 of interleaved error correction bits can be based on the first sequence 320_1 of additional reference bits of the second transmission bit block 300, while a channel estimate for a second part of the first part 310_1 of the sequence 310 is based on interleaved error correction bits can take place on the second sequence 320_2 of additional reference bits of the second transmission bit block 300.
  • a channel estimation for the second part 310_2 of the sequence 310 of interleaved error correction bits can be carried out based on the second sequence 320_2 of additional reference bits of the second transmission bit block 300. The example shown in FIG.
  • FIG. 9 shows the addition and insertion of two additional reference sequences 320_1 and 320_2 in front of or in the area of the interleaved parity bits 310, as a result of which three chronologically different positions are now available in the receiver for a channel estimation.
  • the receiver can now permanently assign one of the three available channel estimates, advantageously the closest, to each unknown data or parity bit, as shown in FIG. 9, or the receiver can interpolate between the three available channel estimates and each data or parity bit assign an interpolated and thus individual channel estimate.
  • an additional reference sequence can of course also be inserted.
  • the length of the reference sequences can be the same or different.
  • An additional reference sequence can also be transmitted after the interleaved parity bits, i.e. as the end of the transmitted sequence.
  • one or more additional reference sequences can be inserted into the sequence of the interleaved parity bits and / or added to the beginning or end thereof.
  • the area of the preamble and the data symbols can remain unchanged compared to uncoded transmission (preservation of backward compatibility). This takes place in that the systematic bits occurring during the coding are arranged directly one behind the other in an unchanged sequence in relation to the data bit sequence.
  • the bits or symbols of the reference sequences are known in advance in the receiver or can be determined from information previously transmitted and recovered in the receiver (e.g. from header information).
  • the channel estimation or channel update considered in the exemplary embodiments is based on the knowledge of transmitted bits or symbols in the receiver.
  • Section 1 shows how additional reference bits known in advance can be introduced into the transmission sequence, on the basis of which the channel estimation can take place. Due to the required backward compatibility, however, no additional reference sequence can be included in the Area of the uncoded data bits are introduced, so that in the case of long data packets there is a comparatively large distance between the data bits located in the middle of this area and the closest reference sequence.
  • one of the data transmitters shown in FIG. 1, for example the data transmitter 100_1 can be configured to carry out forward error correction coding based on the data bit sequence 202 in order to obtain a sequence 304 of systematic bits and the sequence 304 of systematic bits associated with error correction bits 310, the data bit sequence 202 and the sequence 304 of systematic bits being identical, the data transmitter being configured to transmit a signal 120, the signal 120 having a first transmission bit block 200 and a second transmission bit block 300, the first transmission bit block 200 a sequence 201 of reference bits and the sequence 304 of systematic bits, and wherein the second transmission bit block 300 has the error correction bits 3 0, wherein a block of systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the sequence of error correction bits, the block v on is assigned to systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits.
  • the data receiver shown in FIG. 1 can be configured to receive a signal 120 having a first transmission bit block 200 and a second transmission bit block 300, the first transmission bit block 200 having a sequence 201 of reference bits and a sequence 304 of systematic bits , the sequence of systematic bits 304 being identical to a data bit sequence 202 to be transmitted with the signal, the second transmission bit block 300 having error correction bits 310 assigned to the sequence 304 of systematic bits, the data receiver 110 being configured to use the received sequence 201 to perform a channel estimation of reference bits, the data receiver 110 being configured to generate a sequence that includes a received block of systematic bits of the received sequence 304 of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits 310 that the received A block of systematic bits is allocated, regardless of other error correction bits received or received To decode blocks of error correction bits in order to obtain a block of the data bit sequence, wherein the data receiver 110 is configured to carry out forward error coding for the block of the data bit sequence in order to obtain a block of the data bit
  • Fig. 10 shows a schematic view of a generation of a sequence of coded bits with blocks of coded bits (e.g. coded partial sequences) which are individually coded, as well as iterative channel tracking based on the blocks of coded bits.
  • blocks of coded bits e.g. coded partial sequences
  • parts (e.g. blocks) 202_1, 202_3 and 202_3 of a data bit sequence 202 can be encoded individually in order to obtain individually encoded blocks 206_1, 206_2 and 206_3 of encoded data bits (encoded partial sequences).
  • a channel estimation for a demodulation of the first block 206_1 of coded data bits can be carried out. Furthermore, in the first receiver-side step 332, the first block 206_1 of encoded data bits based on the channel estimate can be demodulated, decoded and reencoded (German: newly encoded) in order to obtain a first reencoded (German: reencoded) block 206__1 of encoded data bits.
  • a channel estimation for demodulation of the second block 206_2 of coded data bits can be carried out.
  • the second block 206_2 of encoded data bits based on the channel estimate can be demodulated, decoded and reencoded (German: newly encoded) in order to obtain a second reencoded (German: reencoded) block 206_2 of encoded data bits.
  • the data bits 202 are first broken down into blocks 202_1, 202_2 and 202_3 of data bits (e.g. data bit partial sequences), which are each encoded separately.
  • data bits e.g. data bit partial sequences
  • “Cod. Operaquenz” the already coded and interleaved bits of a data bit partial sequence.
  • step 1a The initial channel estimation in the first step 330 (step 1a) takes place exclusively on the basis of the reference bits. This channel estimate is used for the coherent demodulation of the bits of the first block 206_1 of coded data bits (coded partial sequence 1).
  • the bits of the first block 206_1 of coded bits are decoded and then reencoded (step 1b), which now gives estimated values for the first block 206_1 of coded data bits (coded partial sequence 1) including a coding gain .
  • step 1b an extended sequence of known bits is now available in the receiver, comprising the block 201 of reference bits and the first reencoded block 206_1 of coded bits (coded partial sequence 1).
  • the channel estimate for demodulation, decoding and re-encoding (step 2b) of the second block 206_2 of coded data bits (coded partial sequence 2), which can then be regarded as known, is updated . It is easy to see that in this way the entire transmission sequence, consisting of any number of partial sequences, can be processed iteratively, with the channel estimate being updated again and again after each iteration step (channel tracking).
  • a transmission bit sequence to be transmitted can have a first transmission bit block, which is backward compatible with an “existing” communication system (or communication protocol), and a second transmission bit block, which extends the “existing” communication system by a forward error correction based on one or more the following steps:
  • the data bit sequence 202 (for example sequence of data bits) can be divided into a suitable number of blocks of data bits (for example data bit partial sequences).
  • Each block of data bits (e.g. each data bit partial sequence) can be coded with forward error correction coding (e.g. turbo coding) separately and independently of the other blocks of data bits.
  • forward error correction coding e.g. turbo coding
  • the systematic bits of all blocks of coded data bits can be grouped, appended directly to one another and arranged immediately after the sequence 201 of reference bits (e.g. reference sequence).
  • the systematic bits are not interleaved, so that after grouping they are identical to the entire data bit sequence 202.
  • error correction bits e.g. parity bits
  • all blocks of coded data bits e.g. coded partial sequences
  • the error correction bits can be grouped, appended to one another and arranged according to the sequence of all systematic bits.
  • error correction bits e.g. parity bits
  • any interleaving of the error correction bits is carried out separately, part-sequence for part-sequence and not across part-sequence.
  • error correction bits e.g. parity bits
  • additional reference sequences e.g. according to Section 1
  • FIG. 11 shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.
  • coding forward error correction
  • the data bit sequence 202 can be divided into at least two blocks 202_1-202_i, i> 2.
  • FIG. 11 it is assumed, by way of example, that the data bit sequence 202 is divided into three blocks 202_1, 202_2 and 202_3.
  • the following description of FIG. 11 is applicable in a corresponding manner when the data bit sequence is divided into a different number of blocks.
  • a first forward error correction coding can be carried out in order to add a first block 304_1 of systematic bits and a first block 310_1 of contiguous error correction bits, which corresponds to the first block 304_1 of systematic Bits assigned to get. Furthermore, in the second step 342, based on the second block 202_2 of the data bit sequence, a second forward error correction coding can be carried out in order to a second block 304_2 of systematic bits and a second block 310_2 of contiguous error correction bits associated with the second block 304_2 of systematic bits.
  • a third forward error correction coding can be carried out in order to generate a third block 304_3 of systematic bits and a third block 310_3 of contiguous error correction bits, which corresponds to the third block 304_3 of systematic bits assigned.
  • the blocks 304_1, 304_2 and 304_3 of systematic bits can be grouped (e.g. concatenated) in order to obtain a sequence 304 of systematic bits which is identical to the data bit sequence 202.
  • the first transmission bit block thus comprises the sequence 201 of reference bits and the sequence 304 of systematic bits
  • the second transmission bit block 300 comprises the blocks 310_1, 310_2 and 310_3 of error correction bits.
  • one or more blocks of additional reference bits can (optionally) be inserted into the second transmission bit block 300.
  • the second transmission bit block comprises, for example, a sequence 320 of additional reference bits which is arranged at the beginning of the second transmission bit block 300.
  • the first block 310_1 of error correction bits is arranged directly adjacent to the sequence 320 of additional reference bits
  • the second block 310_2 of error correction bits being arranged directly adjacent to the first block 310_1 of error correction bits
  • the third block 310_3 of error correction bits is arranged immediately adjacent to the second block 310_2 of error correction bits.
  • FIG. 11 illustrates the method schematically for the case of a division of the data sequence (e.g. data bit sequence 202) into three data partial sequences 202_1, 202_2 and 202_3 and with the insertion of an additional reference sequence 320 in the area between data and parity bits.
  • a division of the data sequence e.g. data bit sequence 202
  • three data partial sequences 202_1, 202_2 and 202_3 and with the insertion of an additional reference sequence 320 in the area between data and parity bits.
  • the data bit sequence (data bit sequence 202) is divided into three data partial sequences (eg blocks 202_ 1, 202_2 and 202_3) which are coded separately.
  • the systematic bits of each partial sequence are then added to one another and these are placed after the reference bits.
  • the three sequences of the parity bits for example blocks 310_1, 310J2 and 310J3 error correction bits.
  • an additional reference sequence 320 (see section 1) is inserted between the area of the systematic bits 304 and the area of the parity bits 310_1, 310_2 and 310_3.
  • Embodiments enable the receiver to estimate or update the transmission channel multiple times within the entire data packet. This is done using the example chosen as follows:
  • the first channel estimate is made
  • systematic bits 1 • for the first block 304_1 of systematic bits (“systematic bits 1”) z. B. on the basis of the sequence 201 of reference bits (e.g. preamble),
  • parity bits 1 • for the first block 310_1 of error correction bits (“parity bits 1”) e.g. on the basis of the previously known sequence 320 of additional reference bits (e.g. additional reference sequence).
  • the first block 304_1 of systematic bits (“systematic bits 1”) and the first block 310_1 of error correction bits (“parity bits 1”) are then demodulated and the associated block 202_1 of the data bit sequence (e.g. data bit partial sequence 1) is decoded. If the decoding result is correct, the first block 304_1 of systematic bits (“systematic bits 1”) and the first block 310_1 of error correction bits (“parity bits 1”) can be determined by re-encoding.
  • the decoding gain is used here, i.e. the reliability of the estimated values for the above bits is significantly higher after decoding than before decoding (i.e. directly after demodulation).
  • the second channel estimate valid for the second block 304_2 of systematic bits (“systematic bits 2”) and for the second block 310_2 of error correction bits (“parity bits 2”), is based on the now known first block 304_1 (in addition to the first channel estimate) of systematic bits (“systematic bits 1”) and the first block 310_1 of error correction bits (“parity bits 1”), which were still unknown in the first step.
  • the second block 304_2 of systematic bits (“systematic bits 2”) and the second block 310_2 of error correction bits (“parity bits 2”) are then demodulated, and the associated second block 202_2 of the data bit sequence (data bit partial sequence 2) is decoded, etc.
  • the channel estimation can be successively updated in this way and the distance between the respectively known bits on the basis of which the channel estimation is made and the area in which the channel estimation is used in the context of the demodulation does not keep increasing , but rather, for example, can be kept constant.
  • a time variant channel can therefore be used with (compared to entire Data packet length) with a low delay by continuously updating the channel estimate, especially if a division into a larger number of data bit partial sequences takes place.
  • the above exemplary embodiment shows the idea according to the invention for dividing the data sequence into three data bit partial sequences.
  • This example is for illustrative purposes only.
  • the data sequence can be divided into any number of partial data sequences.
  • the length of a partial data sequence depends on the expected coherence time of the channel, e.g. on an expected frequency offset or a maximum assumed movement speed of the transmitter and / or receiver and / or scattered objects.
  • FIG. 12 shows a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block 200 from FIG. 11 and a second transmission bit block which, compared to FIG. 11, has a different arrangement of the blocks 310_1, 310_2 and 310_3 of error correction bits and the one sequence 320 of has additional reference bits.
  • FIG. 12 shows a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block 200 from FIG. 11 and a second transmission bit block which, compared to FIG. 11, has a different arrangement of the blocks 310_1, 310_2 and 310_3 of error correction bits and the one sequence 320 of has additional reference bits.
  • the sequence 320 of additional reference bits can be arranged at one end of the second transmission bit block 300, wherein the first block 310_1 of error correction bits can be arranged immediately adjacent to the sequence 320 of additional reference bits, the second block 310_2 of error correction bits can be arranged immediately adjacent to the first block 310_1 of error correction bits, and wherein the third block 310_3 of error correction bits can be arranged immediately adjacent to the second block 310_2 of error correction bits.
  • the additional reference sequence 320 is arranged at the end of the transmitted data and the blocks 310_1, 310_2 and 310_3 of error correction bits (parity bit sequences) in reverse order with respect to the indexing of the blocks 202_1, 202_2 and 202_3 of the data bit sequence (data bit Partial sequences).
  • the channel estimate would be updated in the receiver in the direction from outside to inside. This is indicated at the bottom in FIG. 12 by corresponding directional arrows 350 and 352.
  • the additional reference sequence 320 could instead be arranged after the first block 310_1 of error correction bits (“parity bits 1”) between the first block 310_1 of error correction bits (“parity bits 1”) and the second block 310_2 of error correction bits (“parity bits 2”).
  • the blocks of error correction bits e.g. parity bits
  • the parity bit sequences (blocks of error correction bits) were arranged in such a way that the first parity bit sequence (first block 310_1) adjoins an additional reference sequence 320.
  • the first parity bit sequence can also be placed in front of the reference bits already present in the original (uncoded) system. This is shown in FIG. 13.
  • FIG. 13 shows a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block 200 from FIG. 11 and a second transmission bit block 300 which precedes the first transmission bit block 200.
  • the first block 310_1 of error correction bits can be arranged such that the first block 310_1 of error correction bits is arranged directly adjacent to the sequence 201 of reference bits of the first transmission bit block 200.
  • the second block 310_2 of error correction bits can be arranged directly adjacent to the first block 310_1 of error correction bits, wherein the third block 310_3 of error correction bits can be arranged directly adjacent to the second block 310_2 of error correction bits.
  • the parity bit sequences (blocks of error correction bits) can then, as is shown in FIG. 13, in chronologically reversed order before the reference bits 201 be arranged so that a successive channel estimation from “inside” to “outside” 350, 352, starting with reference bits 201, can take place in the receiver.
  • a sequence is punctured after coding in order to achieve a desired coding rate with high granularity.
  • Such puncturing is also possible in exemplary embodiments, but the systematic bits should in principle be excluded from puncturing in order to meet the requirement for backward compatibility.
  • the number of parity bits can be significantly higher than the number of systematic bits, e.g. at least twice as large.
  • the step size when updating the channel estimate can be significantly larger in the area of the parity bits than in the area of the systematic bits, as can also be seen in the schematic illustration according to FIG. 11.
  • the distance between the range of the known bits on the basis of which the channel estimation takes place and the range in which this estimated value is used for the demodulation is different in the range of the systematic bits and the parity bits.
  • this circumstance can lead to a loss of performance, since the channel estimation “lags too far behind” the respective demodulation time.
  • parity bit sequences can be subdivided into several parity bit partial sequences. This is illustrated in the following exemplary embodiment, in which a subdivision into two partial sequences takes place, as is explained below with reference to FIG.
  • the data bit sequence 202 can be divided into at least two blocks 202_1-202J, i-2.
  • FIG. 14 for illustration purposes, it is assumed by way of example that the data bit sequence 202 is divided into three blocks 202_1, 202_2 and 202_3. However, the following description of FIG. 14 is applicable in a corresponding manner when the data bit sequence is divided into a different number of blocks.
  • a first forward error correction coding can be carried out in order to generate a first block 304_1 of systematic bits and two blocks 310_1 and 310_2 of contiguous error correction bits that correspond to the first block 304_1 of systematic bits are assigned. Furthermore, in the second step 342, based on the second block 202_2 of the data bit sequence, a second forward error correction coding can be carried out in order to generate a second block 304_2 of systematic bits and two blocks 310_3 and 310_4 of contiguous error correction bits which the second block 304_2 of systematic bits assigned to get.
  • a third forward error correction coding can be carried out in order to add a third block 304_3 of systematic bits and two blocks 310_5 and 310_6 of contiguous error correction bits which the third block 304_3 of systematic bits assigned to get.
  • the blocks 304_1, 304_2 and 304J3 of systematic bits can be grouped (e.g. concatenated) in order to obtain a sequence 304 of systematic bits which is identical to the data bit sequence 202.
  • the first transmission bit block thus comprises the sequence 201 of reference bits and the sequence 304 of systematic bits
  • the second transmission bit block 300 comprises the six blocks 310_1 -310_6 of error correction bits.
  • one or more blocks of additional reference bits can (optionally) be inserted into the second transmission bit block 300.
  • the second transmission bit block 300 comprises, for example, a first sequence 320_1 of additional reference bits, which is arranged at the beginning of the second transmission bit block 300, and a second sequence 320_2 of additional reference bits, which is in the middle between the six blocks 310_1 -310_6 of error correction bits is arranged.
  • the first block 310_1 of error correction bits can be arranged directly adjacent to the first sequence 320_1 of additional reference bits, the third block 310_3 of error correction bits directly adjacent to the The first block 310_1 of error correction bits is arranged, the second block 310_2 of error correction bits being arranged directly adjacent to the second sequence 320_2 of additional reference bits, and the fourth block 310_4 of error correction bits being arranged directly adjacent to the second block 310_2 of error correction bits.
  • FIG. 14 shows how the parity bits generated by coding a data bit partial sequence (block of the data bit sequence) are divided into, for example, two partial sequences (“a” and “b”), which in FIG 1a ”and“ parity bits 1b ”,“ parity bits 2a ”and“ parity bits 2b ”etc. are identified (ie two (or more) blocks of error correction bits are generated for each block of the data bit sequence during forward error correction coding).
  • a further, second additional reference sequence 320_2 (additional reference sequence 2) has been inserted.
  • the parity bits belonging to a data bit partial sequence (block of the data bit sequence), e.g.
  • parity bits 1a (first block 310_1 of error correction bits) and parity bits 1b (second block 310_2 of error correction bits), are not transmitted directly one after the other, but are grouped in such a way that initially all parity bits Partial sequences “a” (1a, 2a, 3a) are arranged and subsequently all partial sequences “b” (1b, 2b, 3b).
  • the receiver carries out initial channel estimates based on preamble 201, additional reference sequence 1 (first sequence 320_1 of additional reference bits) and additional reference sequence 2 (second sequence 320_2 of additional reference bits). This is followed by demodulation of the “systematic bits 1” (first block 304_1 of systematic bits), “parity bits 1a” (first block 310_1 of error correction bits) and “parity bits 1b” (second block 310_2 of error correction bits), which are immediately after the reference sequences known in advance (first and second block of additional reference bits).
  • the data bit partial sequence 1 (first block 202_1 of the data bit sequence) can be decoded.
  • the "systematic bits 1 ”(first block 304_1 of systematic bits),“ parity bits 1a ”(first block 310_1 of error correction bits) and“ parity bits 1b ”(second block 310_2 of error correction bits) are now known and can be used as a basis for further channel estimates.
  • an additional reference sequence e.g. sequence of additional reference bits (in addition to the reference bits of the first transmission bit block)
  • parity bits error correction bits
  • FIG. 15 shows a schematic view of the generation of a transmission bit sequence to be transmitted, FIG. 15 only showing step 346 of inserting a sequence of additional reference bits into the second transmission bit block of the transmission bit sequence, which is different from that shown in FIG Step of inserting a sequence of additional reference bits.
  • the first block 310_1 of error correction bits and the second block 310_2 of error correction bits can each be arranged directly adjacent to the sequence 320 of additional reference bits.
  • Blocks of error correction bits that are assigned to a block of the data bit sequence that immediately follows the block of the data bit sequence that is arranged at the beginning of the data bit sequence can be directly adjacent (or each with only one further sequence of additional reference bits in between) to the first block 310_1 of error correction bits and the second block 310_2 of error correction bits, etc. That is, the third block 310_3 of error correction bits can be arranged immediately adjacent to the first block 310_1 of error correction bits, the fifth block 310J5 of error correction bits can be arranged immediately adjacent to the third block 310_3 of error correction bits.
  • the fourth block 310_4 of error correction bits can be arranged directly adjacent to the second block 310_2 of error correction bits, wherein the sixth block 310_6 of error correction bits can be arranged directly adjacent to the fourth block 310_4 of error correction bits.
  • the respective parity bit partial sequences “a” for example blocks of error correction bits with odd indices
  • “B” for example blocks of error correction bits with even indices
  • the steps up to the generation of the coded bits are not shown in FIG. 15 for reasons of clarity.
  • only one additional reference sequence for example a sequence of additional reference bits
  • several sequences of additional reference bits can also be introduced into the second transmission bit block.
  • the steps of iterative channel estimation are carried out in the area of the systematic bits (e.g. blocks 304_1-304_3 of systematic bits) in a positive temporal direction (e.g. based on the sequence 201 of reference bits), while in the area of the parity bits (e.g. blocks 31CM- 310_6 of error correction bits) is estimated on both sides away from the additional reference sequence (sequence 320 of additional reference bits) (both in the positive as well as in the negative direction in time). This is illustrated by the three direction arrows 350, 352, 354 in the lower part of FIG. 15.
  • additional reference sequences e.g. sequences of additional reference bits
  • one of the additional reference sequences between the parity bit partial sequences a "(e.g. blocks of error correction bits with odd indices) and" b "(e.g. Blocks of error correction bits with even indices) can be incorporated (or arranged) in the second transmission bit block, as shown in FIG.
  • FIG. 16 shows a schematic view of a generation of a transmission bit sequence to be transmitted, only step 346 of the insertion of several sequences of additional reference bits in the second transmission bit block of the transmission bit sequence, which differs from that in FIG. 14, being shown in FIG shown step of inserting a sequence of additional reference bits differs.
  • three sequences 320__1, 320_2 and 320_3 of additional reference bits can be introduced into the second transmission bit block 300 between the blocks 310_1-310_6 of error correction bits, one of the three sequences 320_1, 320_2 and 320_3 of additional reference bits can be arranged between two blocks of error correction bits which are assigned to the same block of the data bit sequence.
  • a first sequence 320_1 of additional reference bits between the first block 310_1 of error correction bits and the second block 310_2 of error correction bits, a second sequence 320_2 of additional reference bits between the third block 310_3 of error correction bits and the fourth block 310_4 of error correction bits, and a third sequence 320_3 of additional reference bits can be arranged between the fifth block 310J5 of error correction bits and the sixth block 310_6 of error correction bits.
  • Error correction bits with odd indices and "b" e.g. blocks of error correction bits with even indices
  • further additional reference sequences can be arranged. These can each lie between the two parity bit partial sequences “a” and “b”, advantageously (but not necessarily) also in the middle, as is shown by way of example in FIG. 16.
  • the steps of iterative channel estimation take place in the area of the systematic bits (e.g. blocks 304_1-304_3 of systematic bits) in a positive temporal direction (e.g. starting from the sequence 201 of reference bits), while in the area of the parity bits (blocks 310_1-310_6 of error correction bits) on both sides starting from the respective additional reference sequences (sequences 320_1, 320_2 and 320_3 of additional reference bits) away (in both the positive and negative direction in time).
  • This is illustrated by the seven direction arrows 350-362 in the lower part of FIG. 16.
  • additional reference sequences e.g. sequences of additional reference bits
  • enlarged (e.g. maximized) distances between the respective associated parity bit partial sequences "a" e.g. blocks of
  • Error correction bits with odd indices and "b" (e.g. blocks of error correction bits with even indices) can be introduced, as shown in FIG.
  • FIG. 17 shows a schematic view of a resulting transmission bit sequence after the introduction of three sequences 320_1, 320_2 and 320J3 of additional reference bits, a distance between blocks of error correction bits assigned to the same block of the transmission bit sequence being enlarged compared with FIG is.
  • a first block 310_1 of error correction bits and a second block 310_2 of error correction bits can be arranged immediately adjacent to spaced-apart sequences 320_1 and 320_2 of reference bits
  • a third block 310_3 of error correction bits and a fourth block 310_4 of Error correction bits can be arranged immediately adjacent to spaced-apart sequences 320_2 and 320_3 of reference bits
  • a fifth block 310_5 of error correction bits and a sixth block 310_6 of error correction bits directly may be arranged adjacent to spaced-apart sequences 32CM and 320_3 of reference bits.
  • FIG. 17 shows a further advantageous arrangement of the parity bit partial sequences (e.g. blocks of error correction bits) in the presence of fading channels.
  • an additional reference sequence e.g. sequence of additional reference bits
  • each parity bit partial sequence e.g. block of error correction bits
  • the sequence of parity bit partial sequences does not matter.
  • the parity bit partial sequences can in principle be arranged in any order.
  • N P 2 parity bit partial sequences (“a” and “b”) (eg blocks of error correction bits) .
  • the parity bits belonging to each data bit partial sequence can also be divided into more than two parity bit partial sequences (eg blocks of error correction bits). In the case of fading channels, these can be positioned in such a way that the parity bit partial sequences belonging to the same coded data bit partial sequence are arranged as far apart in time as possible from one another.
  • FIG. 18 shows a schematic view of a generation of a transmission bit sequence to be transmitted based on forward error correction (coding) Error correction bits, the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.
  • coding forward error correction
  • the data bit sequence 202 can be divided into at least two blocks 202_1-202J, i 2: 2, it being assumed in the exemplary embodiment shown in FIG. 18 that the data bit sequence 202 is divided into three blocks 202_1, 202_2 and 202_3 is divided. However, the following description can be applied in a corresponding manner if the data bit sequence is divided into a different number of blocks.
  • a first forward error correction coding can be carried out in order to add a first block 304_1 of systematic bits and four blocks 310_1-310_4 of error correction bits that correspond to the first block 304_1 of systematic Bits are assigned to get.
  • a second forward error correction coding can be carried out in order to generate a second block 304_2 of systematic bits and four blocks 310_5-310_8 of error correction bits which the second block 304_2 of systematic bits are assigned.
  • a third forward error correction coding can be carried out in order to generate a third block 304_3 of systematic bits and four blocks 310__9-310__12 of error correction bits, which the third block 304_3 of systematic bits are assigned.
  • the blocks 304_1, 304_2 and 304_3 of systematic bits can be grouped (e.g. concatenated) in order to obtain a sequence 304 of systematic bits which is identical to the data bit sequence 202.
  • the first transmission bit block 200 thus comprises a sequence 201 of reference bits and the sequence 304 of systematic bits (shown as a series of blocks 304_1, 304_2 and 304_3 of systematic bits), while the second transmission bit block 300 comprises the comprises twelve blocks 310_1 -310_12 of error correction bits.
  • one or more sequences 320_1 and 320_2 of additional reference bits can (optionally) be inserted into the second transmission bit block 300.
  • two sequences 320_1 and 320_2 of additional reference bits are introduced into the second transmission bit block 300 by way of example.
  • be arranged immediately adjacent to the sequences 320_1 and 320_2 of additional reference bits e.g. blocks 310_1 and 310_3 of error correction bits immediately adjacent to the first sequence 320_1 of additional reference bits and blocks 310_2 and 310_4 of error correction bits immediately adjacent to the second sequence 320_2 of additional reference bits.
  • Blocks of error correction bits that are assigned to a block of the data bit sequence that follows the block of the data bit sequence that is arranged at the beginning of the data bit sequence can be arranged immediately adjacent to the blocks of the error correction bits that correspond to the Block of the data bit sequence are assigned, which is arranged at the beginning of the data bit sequence.
  • the parity bit partial sequences belonging to a respective data bit partial sequence (e.g. block of the data bit sequence) can be arranged with the greatest possible distance from one another, whereby the requirement is met that in the receiver, successive decoding can take place starting directly from a reference sequence (for example a sequence of additional reference bits).
  • a reference sequence for example a sequence of additional reference bits.
  • a transmission bit sequence to be transmitted [e.g. with a first transmission bit block, which is backwards compatible with an "existing" communication system (or communication protocol), and a second transmission bit block, which extends the "existing" communication system by a forward error correction], based on one or more of the following steps:
  • Division of the data bit sequence e.g. data bit sequence 202 into directly successive data bit partial sequences (blocks of the data bit sequence), which are coded separately (e.g. forward error correction coded (e.g. turbo / LDPC / convolution coded)) (coding of the partial sequences (blocks the data bit sequence) independently of each other).
  • forward error correction coded e.g. turbo / LDPC / convolution coded
  • parity bits e.g. blocks of error correction bits
  • the parity bit sequence e.g. block of error correction bits belonging to the first data bit partial sequence (e.g. first block of the data bit sequence) is directly attached to a reference sequence (preamble or additional Reference sequence, see Section 1) adjoins, as well as o the parity bit sequences (for example blocks of error correction bits) directly following one another data bit partial sequences (for example blocks of the data bit sequence) are directly adjacent to one another or there are only additional reference sequences between them (see, for example, FIGS. 11, 12 and 13).
  • additional reference sequences e.g. sequences of additional reference bits
  • the two parity bit partial sequences e.g. blocks of error correction bits
  • the number of additional reference sequences corresponds to the number of data bit partial sequences (e.g. blocks of the data bit sequence) ( see Fig. 16).
  • the exact arrangement of the parity bit partial sequences relative to one another is arbitrary, since each of them is always directly adjacent to an additional reference sequence. For fading channels an arrangement is advantageous in which the two parity bit partial sequences "a” (e.g. blocks of error correction bits with odd indices) and "b" (e.g. blocks of error correction bits with even indices) (which each belong to the same coded data bit partial sequence) be positioned as far apart from each other as possible.
  • parity bit partial sequences e.g. blocks of error correction bits belonging to a data bit partial sequence (e.g. block of the data bit sequence) in such a way that each of these parity bit partial sequences is either attached to an additional reference sequence (e.g. sequence of additional reference bits) or to any (any) parity bit Partial sequence of one of the data bit partial sequences preceding (the data bit partial sequence under consideration) directly adjoins (see, for example, FIGS. 17 and 18).
  • the data bits to be transmitted e.g. data bit sequence 202
  • data bit partial sequences e.g. blocks
  • the coherence time of the radio channel is correspondingly short, so that very short block lengths are required for sufficiently frequent updating of the channel estimate would be.
  • the block length cannot be reduced at will, since, on the one hand, with many common coding methods, a fixed number of so-called tail bits must be added to each block regardless of its length, which means that the relative transfer overhead is increased as the block length decreases continues to grow in a disadvantageous manner due to a large number of tail bits.
  • the power efficiency continues to decrease in the case of short block lengths, as a result of which the coding gain is reduced.
  • the exemplary embodiments described in the following thus basically follow the illustration according to FIG. 5, ie the coding of the data bit sequence (e.g. data bit sequence 202) is carried out in such a way that systematic bits are generated and these are transmitted in an unchanged order after the reference bits 201 (requirement of backward compatibility) , only the parity bits (which are transmitted after the systematic bits, for example) are subject to interleaving.
  • the data bit sequence e.g. data bit sequence 202
  • the parity bits which are transmitted after the systematic bits, for example
  • n s + i bits of the data bit sequence 202 are already coded, so that m s + C s + i coded bits are present for the n s + i bits of the data bit sequence 202.
  • a group 310 s + i of C s + i error correction bits is accordingly generated.
  • a data bit sequence (for example data bit sequence 202) consisting of N bits is considered.
  • the coding requirement mentioned furthermore includes that, at the receiver end, partial decoding of the first n s data bits in each time step s is possible with a coding gain if at least m s coded parity bits and n s systematic bits have been estimated in the receiver. An improvement in the performance can possibly be achieved if in the receiver m s , dec> m s coded parity bits can be estimated.
  • the requirements mentioned can be met, for example, by the group of convolutional codes and by the group of LDPC codes.
  • the exemplary embodiment described here relates to the design of the interleaver in such a way that iterative decoder-supported decoding in the receiver is possible.
  • the group of C s parity bits e.g. error correction bits
  • the group of C s parity bits generated in the coding in step s (with s> 1) is arranged for the transmission in such a way that it is directly linked to the group with C 3 generated in the previous step s-1 -i parity bits (e.g. error correction bits) are added.
  • s 1, i.e. the In the first step of the coding process, the first group of the generated parity bits is positioned directly adjacent to an additional reference sequence.
  • 20 shows a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.
  • coding forward error correction
  • groups 310_1, 310_2, 310_3 of error correction bits are present, which in successive steps of the iterative forward error correction Coding were generated.
  • the error correction bits of groups 310_1, 310_2, 310_3 of error correction bits can each be interleaved within a group (i.e. not across groups) in a step 380 and then introduced into the second send bit block.
  • the groups 310_1, 310_2, 310_3 of error correction bits can be arranged in the second transmission bit block 300 in such a way that a group of error correction bits that were generated in a first step of the iterative forward error correction coding , can be arranged directly adjacent to the sequence 320 of additional reference bits, wherein a second group of 310_2 of error correction bits, which were generated in a second step of the iterative forward error correction coding, can be arranged directly adjacent to the first group 310_1 of error correction bits wherein a third group of 310J3 of error correction bits, which were generated in a third step of the iterative forward error correction coding, can be arranged immediately adjacent to the second group 310_2 of error correction bits.
  • the structure of the first transmission bit block 200 naturally corresponds to the first transmission bit block from the previous exemplary embodiments (see, for example, FIGS. 8, 11-18).
  • the digits describe the indices of the parity bits (eg error correction bits).
  • an interleaver can also use a different index sequence, such as the index sequence ⁇ 3 , 2,1, 6,5,4, 9,8,7, ... ⁇ , without reducing the performance of the iterative channel tracking.
  • the order of the parity bits can be reversed by the interleaver if the additional reference sequence (e.g. sequence 320 of additional reference bits) is at the end of the transmitted bits, as shown in FIG.
  • 21 shows a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits based on iterative forward error correction (coding), the transmission bit sequence being backward compatible with an uncoded transmission bit sequence.
  • the sequence 320 of additional reference bits is introduced into the same at one end of the second transmission bit block 300.
  • the order in which the groups 310_1, 310_2 and 310_3 of error correction bits are arranged in the second transmission bit block 300 changes accordingly.
  • the interleaver reverses the order of the parity bits, since the additional reference sequence (e.g. sequence 320 of additional reference bits), from which the channel estimation for the range of parity bits starts in the receiver, is at the end of the transmitted bits.
  • the order of the bits within the respective groups of three can additionally be selected as desired by the interleaver, without reducing the performance of the iterative channel tracking.
  • the essential feature of the nesting can be seen that the C 3 -3 parity bits of a (triple) group “s” (310s) are directly connected to the previous and / or subsequent triple group “s-1 “(310s-i) or“ s + 1 ”(31 Os + adjoins.
  • the first group 310_1 can be directly adjacent to an additional reference sequence (for example a sequence 320 of additional reference bits). Insertion of several additional reference sequences with cancellation of the parity bit
  • FIG. 22 shows a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.
  • coding forward error correction
  • groups 310_1 and 310_2 of error correction bits are present, which in successive steps of the iterative forward error correction coding were generated.
  • the error correction bits of the groups 310_1 and 310_2 of error correction bits can be interleaved in a step 380 within the respective group and then introduced into the second transmission bit block.
  • error correction bits of a group of error correction bits that were generated in a first step of the iterative forward error correction coding can each be immediately adjacent to a respective sequence 320_1 and 320_2 of additional Be arranged reference bits
  • error correction bits of a second group of 310_2 of error correction bits that were generated in a second step of the iterative forward error correction coding, each immediately adjacent to one of the error correction bits of the group of error correction bits that were generated in a first step of the iterative forward Error correction coding generated can be arranged.
  • the groups 310__1 and 310_2 of error correction bits can each have four error correction bits, as is indicated in FIG.
  • two error correction bits of the first group 310_1 of error correction bits can be arranged immediately adjacent to one of two sequences 320_1 of additional reference bits, with one error correction bit of the second group 310_1 of error correction bits being arranged immediately adjacent to one error correction bit of the first group 310_1 of error correction bits can be.
  • the arrangement of the four parity bits (in the example) per parity bit group is advantageously carried out in the exemplary embodiment before and after each of the two additional reference sequences (e.g. sequences 320_1 and 320_2 of additional reference bits).
  • the bits within each parity bit group can be arranged as desired by the interieaver.
  • the parity bits (e.g. error correction bits) of a group (of error correction bits) can be arranged in such a way that each of these parity bits (e.g. error correction bits) is linked either to any additional reference sequence (e.g. sequence of additional reference bits) or to any one another parity bit (e.g. error correction bit) of the same group (of error correction bits) or to any parity bit (e.g. error correction bit) from a parity bit group (e.g. group of error correction bits) generated in a previous coding step.
  • any additional reference sequence e.g. sequence of additional reference bits
  • any one another parity bit e.g. error correction bit
  • any parity bit e.g. error correction bit
  • one of the data transmitters shown in FIG. 1, for example the data transmitter 100_1 can be configured to carry out forward error correction coding based on the data bit sequence 202 in order to obtain a sequence 304 of systematic bits and the sequence 304 of systematic bits associated with error correction bits 310, the data bit sequence 202 and the sequence 304 of systematic bits being identical, the data transmitter being configured to transmit a signal 120, the signal 120 having a first transmission bit block 200 and a second transmission bit block 300, the first transmission bit block 200 a sequence 201 of reference bits and the sequence 304 of systematic Having bits, and wherein the second transmission bit block 300 has the error correction bits 310, wherein a block of systematic bits from the sequence 304 of systematic bits can be decoded together with a group of error correction bits assigned to the block of systematic bits from the sequence of error correction bits, independently of others Error correction bits or other groups of error correction bits.
  • the data receiver shown in FIG. 1 can be configured to receive a signal 120 having a first transmission bit block 200 and a second transmission bit block 300, the first transmission bit block 200 having a sequence 201 of reference bits and a sequence 304 of systematic bits , the sequence of systematic bits 304 being identical to a data bit sequence 202 to be transmitted with the signal, the second transmission bit block 300 having error correction bits 310 assigned to the sequence 304 of systematic bits, the data receiver 110 being configured to use the received sequence 201 to perform a channel estimation of reference bits, the data receiver 110 being configured to generate a sequence that includes a received block of systematic bits of the received sequence 304 of systematic bits and at least one group of error correction bits of the received sequence of error correction bits that correspond to the received block of systemati is assigned to each other, comprises decoding independently of other received error correction bits or received groups of error correction bits in order to obtain a block of the data bit sequence, the data receiver 110 being configured to carry out forward error coding based on the block of the data bit sequence to obtain a
  • a transmission bit sequence to be transmitted [e.g. with a first transmission bit block, which is backwards compatible with an "existing" communication system (or communication protocol), and a second transmission bit block, which extends the "existing" communication system by a forward error correction], based on one or more of the following steps:
  • an interleaver e.g. parity bit interleaver
  • Receiver an iterative decoder-based channel tracking can be carried out.
  • a suitable coding is required. Step-by-step implementation of the coding of the data bits (e.g. data bit sequence) so that groups of parity bits (e.g. error correction bits) (group size: at least 1 bit) are created in each coding step. o Variant 1: arrangement while maintaining the grouping.
  • data bits e.g. data bit sequence
  • groups of parity bits e.g. error correction bits
  • group size at least 1 bit
  • the groups of error correction bits can be arranged in such a way that a group of error correction bits generated in one step is either directly adjacent to an additional reference sequence (e.g. sequence of additional reference bits) or to the group of error correction bits generated in the previous coding step (see e.g. FIGS 21).
  • o Variant 2 arrangement without retaining the grouping.
  • the contiguous arrangement of the error correction bits within a group of error correction bits can be canceled.
  • the parity bits of a group are arranged in such a way that each of these parity bits is linked either to any additional reference sequence (e.g. sequence of additional reference bits) or to any other error correction bit of the same group of error correction bits or to any error correction bit from a group of error correction bits generated in a previous coding step adjoins (see e.g. Fig. 22).
  • parity bits e.g. error correction bits
  • the positions of the parity bits (e.g. error correction bits) within each parity bit group can be interchanged as required.
  • first transmission bit block 200 first transmission bit block 200
  • reference bits and data bits reference bits and data bits
  • one or more additional reference sequences can be inserted into the area of the systematic bits after this weaker condition.
  • the sequence of the systematic bits is divided into two or more partial sequences and one or more additional reference sequences are inserted between them.
  • the area of the parity bits is unaffected by this measure and can advantageously be designed in accordance with the ideas described above.
  • a forward error correction (coding) can be carried out in order to obtain a sequence 304 of systematic bits and a sequence 306 of error correction bits (e.g. parity bits) assigned to the sequence 304 of systematic bits.
  • the sequence 304 of systematic bits is identical to the data bit sequence 202.
  • the sequence 306 of error correction bits can be interleaved in order to obtain a sequence 310 of interleaved error correction bits (e.g. parity bits).
  • a sequence 321 of additional reference bits can be inserted between the sequence 304 of systematic bits, so that the sequence 304 of systematic bits is interrupted by the sequence of additional reference bits, so that a first part 305_1 of the sequence 304 of systematic Bits is arranged before the sequence 321 of additional reference bits and a second part 305_2 of the sequence of systematic bits is arranged after the sequence 321 of additional reference bits.
  • the first transmission bit block 200 of the transmission bit sequence to be transmitted accordingly comprises the sequence 201 of reference bits, the sequence 321 of further reference bits and the sequence 304 of systematic bits, which is divided into two by the sequence 321 of further reference bits.
  • the second transmission bit block 300 of the transmission bit sequence to be transmitted comprises the sequence 310 of interleaved error correction bits and optionally one or more sequences of additional reference bits.
  • FIG. 23 shows, by way of example, the insertion of an additional reference sequence into the area of the systematic bits.
  • one of the data transmitters shown in FIG. 1, for example the data transmitter 100_1 can be configured to carry out forward error correction coding based on the data bit sequence 202 in order to obtain a sequence 304 of systematic bits and the sequence 304 of systematic bits associated with error correction bits 310, the data bit sequence 202 and the sequence 304 of systematic bits being identical, the data transmitter being configured to transmit a signal 120, the signal 120 having a first transmission bit block 200 and a second transmission bit block 300, the first transmission bit block 200 a first sequence 201 of reference bits, the sequence 304 of systematic Bits and a second sequence 321 of reference bits, the sequence 304 of systematic bits being interrupted by the second sequence 321 of reference bits, so that a first part 305_1 of the sequence 304 of systematic bits is arranged before the second sequence of reference bits and a second Part 304_2 of the sequence of systematic bits is arranged [e.g.
  • the second transmission bit block 300 having the error correction bits 310, a block of systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits the sequence of error correction bits assigned to the block of systematic bits can be decoded independently of other error correction bits or blocks of error correction bits.
  • one or more additional reference sequences can be inserted into the area of the systematic bits.
  • the order of the systematic bits can be retained (apart from the inserts).
  • the exemplary embodiments described in the other sections can be used in the area of the parity bits (e.g. error correction bits) regardless of this.
  • the method 600 comprises a step 602 of obtaining a data bit sequence.
  • the method 600 further comprises a step 604 of performing, based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and the sequence of systematic bits assigned error correction bits [eg M error correction bits], the data bit sequence and the Sequence of systematic bits are identical.
  • the method 600 further comprises a step 606 of transmitting a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and the sequence of systematic bits, and the second transmission bit block has the error correction bits, wherein a block of [eg contiguous] systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the error correction bits belonging to the block of systematic bits is assigned, is decodable independently of other error correction bits or blocks of error correction bits.
  • the method 620 includes a step 622 of obtaining a data bit sequence.
  • the method 620 further comprises a step 624 of performing, based on the data bit sequence, forward error correction coding to generate a sequence of systematic bits and error correction bits associated with the sequence of systematic bits [e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical.
  • the method 620 further comprises a step 626 of sending a signal, the signal comprising a first send bit block and a second send bit block, the first send bit block being a [e.g.
  • the second transmission bit block comprises the error correction bits
  • a block of [e.g. related] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits can be decoded from the error correction bits, independently of other error correction bits or other groups of error correction bits.
  • the method 640 includes a step 642 of obtaining a data bit sequence.
  • the method 640 further comprises a step 644 of performing, based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and error correction bits [eg M error correction bits] assigned to the sequence of systematic bits, the data bit sequence and the Sequence of systematic bits are identical.
  • the method 640 further comprises a step 646 of transmitting a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the Sequence of systematic bits is interrupted by the second sequence of reference bits, so that a first part of the sequence of systematic bits [eg temporally] is arranged before the second sequence of reference bits and a second part of the sequence of systematic bits [eg temporally] after the the second sequence of reference bits is arranged, the second transmission bit block having the error correction bits, wherein a block of [e.g.
  • FIG. 27 shows a flow diagram of a method 700 for receiving a signal.
  • the method 700 includes a step 702 of receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to one with the signal is to be transmitted data bit sequence, wherein the second transmission bit block has the sequence of systematic bits assigned to error correction bits.
  • the method 700 further comprises a step 704 of performing a channel estimation based on the received sequence of reference bits.
  • the method 700 further comprises a step of decoding 706 a sequence which is associated with a received block of [eg contiguous] systematic bits of the received sequence of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits associated with the received block of systematic bits is comprised, independently of other received error correction bits or received blocks of error correction bits, in order to obtain a block of the data bit sequence.
  • the method 700 further comprises a step 708 of performing, based on the block of the data bit sequence, forward error coding in order to assign a reencoded block of systematic bits and at least one reencoded block of systematic bits and error correction bits assigned to the reencoded block of systematic bits receive.
  • the method 700 further comprises a step 710 of updating the channel estimation based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.
  • the method 720 includes a step 722 of receiving a signal comprising a first transmit bit block and a second transmit bit block, the first transmit bit block comprising a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to one with the signal is to be transmitted data bit sequence, wherein the second transmission bit block has the sequence of systematic bits assigned to error correction bits.
  • the method 720 further comprises a step of performing 724 a channel estimation based on the received sequence of reference bits.
  • the method 720 further comprises a step 726 of decoding a sequence which comprises a received block of [e.g.
  • the method 720 further comprises a step 728 of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits .
  • the method 720 further comprises a step 730 of updating the channel estimate based on the reencoded block of systematic bits and the reencoded group of error correction bits.
  • the method 740 includes a step 742 of receiving a signal having a first transmit bit block and a second transmit bit block, the first transmit bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic Bits is interrupted by the second sequence of reference bits, so that a first part of the sequence of systematic bits [e.g. temporal] is placed before the second sequence of reference bits and a second part of the sequence of systematic bits [e.g. temporally] is arranged after the second sequence of reference bits, the second transmission bit block having the error correction bits.
  • the method 740 further comprises a step 744 of performing a channel estimation based on the received first sequence of reference bits and the received second sequence of reference bits.
  • the method 740 further includes a step 746 of decoding a sequence comprising a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits that is assigned to the received block of systematic bits, regardless of other received error correction bits or received groups of error correction bits, in order to obtain a block of the data bit sequence .
  • the method 740 further comprises a step 748 of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits .
  • the method 740 further comprises a step 750 of updating the channel estimate based on the reencoded block of systematic bits and the reencoded group of error correction bits.
  • Embodiments of the present invention are used in a system for the packet-wise transmission of data from a transmitter to a receiver.
  • the concepts described herein apply to any transmission in which there is a potentially time-variant transmission channel between sender and receiver, an update of the estimate of this channel within a transmitted data packet is necessary or advantageous, especially in the case of coherent demodulation, coding is used as forward error correction, which among other things outputs so-called systematic bits (e.g. turbo Codes, LDPC codes), and / or backward compatibility of part of the data to be transmitted to uncoded transmission (without forward error correction) is required.
  • systematic bits e.g. turbo Codes, LDPC codes
  • a typical area of application is, for example, the transmission of a message in a digital radio communication system in which the transmission channel can be time-variant due to the movement of the transmitter and / or receiver and / or due to a frequency offset between the transmitter and receiver and in which, e.g. by using coherent demodulation, a ongoing estimation of the transmission channel is required.
  • Embodiments modify an existing transmission system, which so far has worked comparatively inefficiently without coding the data bits, by using e.g. turbo or LDPC codes, so that the efficiency of the transmission system can be increased considerably.
  • Additional redundancy information (parity bits) is transmitted, which, for reasons of backward compatibility, is sent after the bit sequence generated by the original system, for example.
  • Embodiments create data transmitters, data receivers, a communication system and corresponding methods, which
  • Enable data packets and thus the use of e.g. Turbo or LDPC codes, whereby
  • aspects have been described in connection with a device, it goes without saying that these aspects also represent a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Analogously, aspects that have been described in connection with or as a method step also represent a description of a corresponding block or details or features of a corresponding device.
  • Some or all of the method steps can be carried out by a hardware device (or using a hardware device). Apparatus), such as a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some or more of the most important process steps can be performed by such an apparatus.
  • embodiments of the invention can be implemented in hardware or in software.
  • the implementation can be carried out using a digital storage medium such as a floppy disk, a DVD, a Blu-ray disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or other magnetic memory or optical memory, on which electronically readable control signals are stored, which can interact with a programmable computer system or cooperate in such a way that the respective method is carried out. Therefore, the digital storage medium can be computer readable.
  • Some exemplary embodiments according to the invention thus comprise a data carrier which has electronically readable control signals which are able to interact with a programmable computer system in such a way that one of the methods described herein is carried out.
  • exemplary embodiments of the present invention can be implemented as a computer program product with a program code, the program code being effective to carry out one of the methods when the computer program product runs on a computer.
  • the program code can, for example, also be stored on a machine-readable carrier.
  • exemplary embodiments include the computer program for performing one of the methods described herein, the computer program being stored on a machine-readable carrier.
  • an exemplary embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer.
  • a further exemplary embodiment of the method according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the methods described herein is recorded.
  • the data carrier, the digital storage medium or the computer-readable medium are typically tangible and / or non-perishable or non-transitory.
  • a further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents or represents the computer program for performing one of the methods described herein.
  • the data stream or the sequence of signals can, for example, be configured to be transferred via a data communication connection, for example via the Internet.
  • Another exemplary embodiment comprises a processing device, for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.
  • a processing device for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.
  • Another exemplary embodiment comprises a computer on which the computer program for performing one of the methods described herein is installed.
  • Another exemplary embodiment according to the invention comprises a device or a system which is designed to transmit a computer program for performing at least one of the methods described herein to a receiver.
  • the Transmission can take place electronically or optically, for example.
  • the receiver can be, for example, a computer, mobile device, storage device, or similar device.
  • the device or the system can, for example, comprise a file server for transmitting the computer program to the recipient.
  • a programmable logic component for example a field-programmable gate array, an FPGA
  • a field-programmable gate array can interact with a microprocessor in order to carry out one of the methods described herein.
  • the methods are performed by any hardware device. This can be hardware that can be used universally, such as a computer processor (CPU), or hardware specific to the method, such as an ASIC, for example.
  • the devices described herein can be implemented, for example, using a hardware apparatus, or using a computer, or using a combination of a hardware apparatus and a computer.
  • the devices described herein, or any components of the devices described herein, can be implemented at least partially in hardware and / or in software (computer program).
  • the methods described herein can be implemented using hardware apparatus, or using a computer, or using a combination of hardware apparatus and a computer.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne des exemples de modes de réalisation permettant de réaliser un émetteur de données de système de communication, l'émetteur de données étant configuré de sorte à obtenir une suite de bits de données, l'émetteur de données étant configuré de sorte à effectuer un codage à correction d'erreurs sans voie de retour sur la base de la suite de bits de données, de sorte à obtenir une suite de bits systématiques et de bits de correction d'erreurs associés à la suite de bits systématiques, la suite de bits de données et la suite de bits systématiques étant identiques, l'émetteur de données étant configuré de manière à émettre un signal, le signal présentant un premier bloc de bits d'émission et un second bloc de bits d'émission, le premier bloc de bits d'émission comportant une suite de bits de référence et la suite de bits systématiques, et le second bloc de bits d'émission présentant les bits de correction d'erreurs, un bloc de bits systématiques de la suite de bits systématiques pouvant être décodé conjointement avec au moins un bloc de bits de correction d'erreurs cohérents de la suite de bits de correction d'erreurs, lequel est associé au bloc de bits systématiques, indépendamment des autres bits de correction d'erreurs ou des blocs de correction d'erreurs.
EP20796542.7A 2019-10-28 2020-10-21 Mesures permettant une poursuite de canal lors de transmissions numériques Pending EP4052393A2 (fr)

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DE102019216557.5A DE102019216557A1 (de) 2019-10-28 2019-10-28 MAßNAHMEN ZUR ERMÖGLICHUNG EINER KANALNACHFÜHRUNG BEI DIGITALER ÜBERTRAGUNG
PCT/EP2020/079541 WO2021083748A2 (fr) 2019-10-28 2020-10-21 Mesures permettant une poursuite de canal lors de transmissions numériques

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US6421387B1 (en) * 1998-05-15 2002-07-16 North Carolina State University Methods and systems for forward error correction based loss recovery for interactive video transmission
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US7317735B1 (en) * 2002-06-27 2008-01-08 Broadcom Corporation Scrambler initialization in a wireless local area network
GB2424805B (en) * 2005-03-30 2007-02-28 Toshiba Res Europ Ltd Efficient channel tracking in packet based OFDM systems
KR101522033B1 (ko) * 2006-10-05 2015-05-20 코다 와이어리스 피티와이 리미티드 통신 네트워크에서 수신기 성능 향상
TWI581578B (zh) * 2010-02-26 2017-05-01 新力股份有限公司 編碼器及提供遞增冗餘之編碼方法
DE102010043151A1 (de) * 2010-10-29 2012-05-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Datensender und Datenempfänger
ES2625528T3 (es) * 2011-10-31 2017-07-19 Huawei Technologies Co., Ltd. Dispositivo de envío de datos, dispositivo de recepción de datos y método de sincronización de tramas
NO3072308T3 (fr) * 2013-11-22 2018-06-30
DE102016220886B3 (de) * 2016-10-24 2018-03-08 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Interleaving für die Übertragung von Telegrammen mit variabler Subpaketanzahl und sukzessiver Decodierung
DE102018206132B4 (de) * 2018-04-20 2019-11-21 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Decodergestützte iterative Kanalschätzung

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