EP4052294A4 - Integrierte anordnungen mit abschirmungsleitungen zwischen benachbarten aktiven transistorbereichen - Google Patents
Integrierte anordnungen mit abschirmungsleitungen zwischen benachbarten aktiven transistorbereichen Download PDFInfo
- Publication number
- EP4052294A4 EP4052294A4 EP20881766.8A EP20881766A EP4052294A4 EP 4052294 A4 EP4052294 A4 EP 4052294A4 EP 20881766 A EP20881766 A EP 20881766A EP 4052294 A4 EP4052294 A4 EP 4052294A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- active regions
- transistor active
- shield lines
- integrated assemblies
- neighboring transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000000712 assembly Effects 0.000 title 1
- 238000000429 assembly Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/667,289 US11636882B2 (en) | 2019-10-29 | 2019-10-29 | Integrated assemblies having shield lines between neighboring transistor active regions |
| PCT/US2020/056173 WO2021086646A1 (en) | 2019-10-29 | 2020-10-16 | Integrated assemblies having shield lines between neighboring transistor active regions |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP4052294A1 EP4052294A1 (de) | 2022-09-07 |
| EP4052294A4 true EP4052294A4 (de) | 2022-12-21 |
Family
ID=75586177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP20881766.8A Withdrawn EP4052294A4 (de) | 2019-10-29 | 2020-10-16 | Integrierte anordnungen mit abschirmungsleitungen zwischen benachbarten aktiven transistorbereichen |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US11636882B2 (de) |
| EP (1) | EP4052294A4 (de) |
| KR (1) | KR20220079658A (de) |
| CN (1) | CN114616667A (de) |
| TW (1) | TWI763102B (de) |
| WO (1) | WO2021086646A1 (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11600535B2 (en) | 2020-05-06 | 2023-03-07 | Micron Technology, Inc. | Integrated assemblies having conductive material along three of four sides around active regions, and methods of forming integrated assemblies |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030072172A1 (en) * | 2000-10-17 | 2003-04-17 | Dinesh Somasekhar | Noise suppression for open bit line DRAM architectures |
| US20130320433A1 (en) * | 2012-05-31 | 2013-12-05 | Heung-Jae Cho | Vertical channel transistor with self-aligned gate electrode and method for fabricating the same |
| US20180331029A1 (en) * | 2017-05-10 | 2018-11-15 | Micron Technology, Inc. | Assemblies Which Include Wordlines Over Gate Electrodes |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004040042A (ja) * | 2002-07-08 | 2004-02-05 | Fujitsu Ltd | 半導体記憶装置 |
| KR20040059014A (ko) | 2002-12-27 | 2004-07-05 | 주식회사 하이닉스반도체 | 쉴드 라인을 구비한 임베디드 디램 |
| US8368137B2 (en) | 2007-06-26 | 2013-02-05 | Sandisk Technologies Inc. | Dual bit line metal layers for non-volatile memory |
| KR101669261B1 (ko) | 2010-06-14 | 2016-10-25 | 삼성전자주식회사 | 수직 채널 트랜지스터를 구비한 반도체 소자 및 그 제조 방법 |
| KR101850536B1 (ko) | 2010-10-27 | 2018-04-19 | 삼성전자주식회사 | 반도체 메모리 장치 및 반도체 메모리 시스템 |
| US9773888B2 (en) | 2014-02-26 | 2017-09-26 | Micron Technology, Inc. | Vertical access devices, semiconductor device structures, and related methods |
| US9773728B1 (en) * | 2016-12-27 | 2017-09-26 | Micron Technology, Inc. | Memory arrays |
| US10008504B1 (en) | 2016-12-27 | 2018-06-26 | Micron Technology, Inc. | Memory arrays |
| US10229874B1 (en) | 2018-03-22 | 2019-03-12 | Micron Technology, Inc. | Arrays of memory cells individually comprising a capacitor and a transistor and methods of forming such arrays |
| WO2020056173A1 (en) | 2018-09-13 | 2020-03-19 | Pact Pharma, Inc. | Antigen specific tcr identification using single-cell sorting |
-
2019
- 2019-10-29 US US16/667,289 patent/US11636882B2/en active Active
-
2020
- 2020-10-16 WO PCT/US2020/056173 patent/WO2021086646A1/en unknown
- 2020-10-16 KR KR1020227015854A patent/KR20220079658A/ko not_active Application Discontinuation
- 2020-10-16 CN CN202080075116.5A patent/CN114616667A/zh active Pending
- 2020-10-16 EP EP20881766.8A patent/EP4052294A4/de not_active Withdrawn
- 2020-10-28 TW TW109137376A patent/TWI763102B/zh active
-
2023
- 2023-02-27 US US18/114,692 patent/US20230206959A1/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030072172A1 (en) * | 2000-10-17 | 2003-04-17 | Dinesh Somasekhar | Noise suppression for open bit line DRAM architectures |
| US20130320433A1 (en) * | 2012-05-31 | 2013-12-05 | Heung-Jae Cho | Vertical channel transistor with self-aligned gate electrode and method for fabricating the same |
| US20180331029A1 (en) * | 2017-05-10 | 2018-11-15 | Micron Technology, Inc. | Assemblies Which Include Wordlines Over Gate Electrodes |
Non-Patent Citations (1)
| Title |
|---|
| See also references of WO2021086646A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20210125642A1 (en) | 2021-04-29 |
| EP4052294A1 (de) | 2022-09-07 |
| US11636882B2 (en) | 2023-04-25 |
| KR20220079658A (ko) | 2022-06-13 |
| WO2021086646A1 (en) | 2021-05-06 |
| TW202135287A (zh) | 2021-09-16 |
| US20230206959A1 (en) | 2023-06-29 |
| TWI763102B (zh) | 2022-05-01 |
| CN114616667A (zh) | 2022-06-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
| 17P | Request for examination filed |
Effective date: 20220527 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
| A4 | Supplementary search report drawn up and despatched |
Effective date: 20221121 |
|
| RIC1 | Information provided on ipc code assigned before grant |
Ipc: G11C 7/02 20060101ALI20221115BHEP Ipc: G11C 5/06 20060101ALI20221115BHEP Ipc: G11C 5/02 20060101ALI20221115BHEP Ipc: H01L 27/108 20060101AFI20221115BHEP |
|
| DAV | Request for validation of the european patent (deleted) | ||
| DAX | Request for extension of the european patent (deleted) | ||
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20230620 |