EP4046278A1 - Convertisseur numérique-analogique à grande vitesse - Google Patents

Convertisseur numérique-analogique à grande vitesse

Info

Publication number
EP4046278A1
EP4046278A1 EP19794475.4A EP19794475A EP4046278A1 EP 4046278 A1 EP4046278 A1 EP 4046278A1 EP 19794475 A EP19794475 A EP 19794475A EP 4046278 A1 EP4046278 A1 EP 4046278A1
Authority
EP
European Patent Office
Prior art keywords
digital
transistor
analogue converter
output
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19794475.4A
Other languages
German (de)
English (en)
Inventor
Denise LEE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of EP4046278A1 publication Critical patent/EP4046278A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
    • H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators

Definitions

  • the present invention relates to digital analogue converters.
  • a digital to analogue converter receives a digital signal and outputs an analogue signal in dependence on the digital signal.
  • the voltage of the analogue signal is dependent on a numeric value represented by the digital signal.
  • DAC digital to analogue converter
  • a digital to analogue converter comprising: a plurality of segments each comprising a first output stage and a second output stage, each output stage of a segment being configured to receive a digital input signal and the output stages being configured to cooperatively form a differential output in dependence on the input signal; wherein: each output stage of a segment comprises a first transistor device configured to operate as a regulated current source for driving a part of the differential output and to be switched in a source degenerate manner in dependence on the state of a second transistor of the respective output stage; and each segment is configured to form a unary segment and the plurality of segments cooperatively implement the digital to analogue converter.
  • the first transistor may have a first gate oxide layer and the second transistor may have a second gate oxide layer and the first gate oxide layer may be thicker than the second gate oxide layer. This may permit the relative behaviour of the transistors to be controlled advantageously.
  • the second transistor may be configured so that its state is dependent on a state of the input signal. That may permit the second transistor to control other circuit components in dependence on the input signal.
  • the digital to analogue converter may comprise a capacitor configured for charge pumping the gate capacitance of the second transistor. This may be a convenient way of controlling the state of the second transistor.
  • the capacitor may be reset under the control of a switching arrangement cross-coupled between the output stages of a segment operating in the opposite phase. This may be a convenient way of controlling the state of the second transistor.
  • the digital to analogue converter may be implemented as an integrated circuit and the capacitor may at least partially overlie one or both of the first transistor and second transistors. This may be a convenient way to package the circuit.
  • the source and drain of the second transistor may be coupled between a first voltage reference and a first node; the source and drain of a third transistor may be coupled between the first node and a second node; the source and drain of the first transistor may be coupled between the second node and a third node; the source and drain of a fourth transistor may be coupled between the third node and a second voltage reference; and a part of the differential output may be coupled to the second node.
  • This may be a convenient architecture to generate a suitable analogue output signal.
  • the first transistor and the third transistor may be configured to receive complementary bias voltages at their gates. This may provide a convenient mechanism for controlling the behaviour of those transistors.
  • the second transistor and the fourth transistor may be configured to be switched in complementary fashion in dependence on the input. This may provide a convenient mechanism for controlling the behaviour of those transistors.
  • One of the second and fourth transistors may be a P-type transistor and the other of the second and fourth transistors may be an N-type transistor. Transistors arranged in this way may provide good performance in a DAC of the type described herein.
  • the digital to analogue converter may be arranged to be subject to closed loop compensating control whereby gain of a transfer function of each segment over temperature is maintained. This may provide temperature invariant performance.
  • a data processing circuit comprising a digital to analogue converter as claimed in any preceding claim and a digital signal processor configured to form a digital signal as the input to the digital to analogue converter, wherein the digital to analogue converter and the digital signal processor are configured to operate in the same voltage domain.
  • Figure 1 shows a unary segment of a DAC circuit.
  • Figure 2 shows a golden unary segment identical to the output unary segment utilized to generate the static voltage biasing which sets the output switched current.
  • Figure 3(a) illustrates a simplified schematic view of the half circuit of a prior art current mode DAC output, where an ON’ state switch is represented as a resistor, Rds.
  • Figure 3(b) illustrates, in a similar state of operation, the DAC described herein.
  • Figures 4(a) and 4(b) illustrate the headroom limitation of a prior art design compared to the DAC described herein, respectively.
  • Figure 4(b) highlights the reduced operating headroom, as indicated by the required overdrive or excess voltage required to keep a MOSFET device in the saturation region of operation, compared to the arrangement of Figure 4(a).
  • Figure 1 shows an example of a DAC comprising a plurality of segments.
  • the DAC is a digitally switched DAC with a charge coupled level shifter.
  • This architecture has unary (i.e. base-1 ) segmentation with output transfer function gain adjustment, which enables reconfigurable DAC resolution with ganging via digital control. Such unary segments may operate together to form a multi-bit DAC.
  • the DAC may be implemented in a data processing circuit comprising a digital signal processor configured to form a digital signal as the input to the digital to analogue converter.
  • the digital to analogue converter and the digital signal processor can be configured to operate in the same voltage domain.
  • Each unary segment comprises a first output stage and a second output stage, shown generally at 101 and 102 respectively in Figure 1 .
  • Each output stage is configured to receive a digital input signal.
  • the output stages of the circuit receive the input signals SEL and SELB.
  • the first and second output stages 101 and 102 cooperatively form a differential output (VOUTP/VOUTN) in dependence on the input signal.
  • Each output stage of a segment comprises the following components. The components are shown and described here with respect to the output stage shown generally at 101 in Figure 1 .
  • Each output stage comprises a first transistor 103 which operates as a regulated current source for driving a part of the differential output.
  • the first transistor 103 is switched in a source degenerate manner in dependence on the state of a second transistor 104 of the respective output stage 101.
  • the second transistor 104 is configured so that its state is dependent on a state of the input signal.
  • the transistors 103 and 104 are MOSFET switches, which have gate oxide (GO) layers.
  • the gate oxide layer of the first transistor 103 is thicker than the gate oxide layer of the second transistor 104.
  • the second transistor 304 may comprise a G01 (gate oxide layer 1) switch, which is a thin oxide MOSFET device
  • the first transistor 103 may comprise a G02 (gate oxide layer 2) switch, which is a thick oxide MOSFET device, which has a higher electric overstress voltage tolerance than a G01 switch.
  • the DAC has a capacitor Cs configured for charge pumping the gate capacitance of the second transistor 104.
  • the capacitor may be reset under the control of a switching arrangement cross-coupled between the output stages of a segment operating in the opposite phase.
  • the DAC is implemented in an integrated circuit.
  • the capacitor may at least partially overlie one or both of the transistors in each output segment.
  • the source and drain of the second transistor 104 are coupled between a first voltage reference VDD (the supply voltage) and a first node 105.
  • the source and drain of a third transistor 106 are coupled between the first node 105 and a second node 107.
  • the source and drain of the first transistor 103 are coupled between the second node 107 and a third node 108.
  • the source and drain of a fourth transistor 109 are coupled between the third node 108 and a second voltage reference GND (ground).
  • a part of the differential output (VOUTP) is coupled to the second node 107.
  • One of the second and fourth transistors is a P-type transistor and the other of the second and fourth transistors is an N-type transistor.
  • the transistors are configured to be switched in complementary fashion in dependence on the input.
  • the first transistor 103 and the third transistor 106 are configured to receive complementary bias voltages, VBIASN and VBIASP respectively, at their gates.
  • this equivalent source degenerate comprises a G01 switch.
  • the high side and low side equivalent degenerates switch in compliment: that is, G01 104 turns OFF whilst G01 109 turns ON, and vice versa.
  • the DAC topology is a current steering DAC with differential output, utilizing a push-pull architecture with regulated switched current source.
  • the DAC comprises a complimentary pair of output stages which make up a differential output.
  • each driving output stage comprises an arrangement in a manner typical to a logic inverter with push-pull output drive.
  • both high side and low side G02 I/O devices (103 and 106) are in essence source degenerated.
  • the switching of an equivalent degenerate (impedance) with two threshold of operation i.e. a state of high impedance (OFF) and low impedance (ON)) controls the activation of the current source.
  • This manner of operation facilitates the exclusion of level shifting to a different voltage domain in manner typical of a CML DAC architecture.
  • the N G01 switches can be directly driven by standard cell (SC) logic from the digital voltage domain.
  • the G01 switches 104 and 109 operate in phase.
  • the N G01 switches ON with an applied gate voltage from GND (Logic O’) to DVDD (Logic ), and the P G01 switches OFF from VDD-DVDD (Logic ) to VDD (Logic O’), with the N G01 source tied to GND, and the P G01 tied to VDD.
  • a single digital bit line drives each unary segment of the DAC. This also simplifies the synchronized clocking of data (i.e. the latching of data), moving to the digital back end. This may limit DAC cell related timing delay errors (i.e. dynamic errors attributable to driving AFE output stages), in effect relying more on the high speed offered by the core logic G01 domain with its routing efficiency.
  • the other dynamic temporal error is code-dependent error, that is a stepping of DAC output voltage in relation to code transition. This aspect is addressed by design with the said push-pull output stage. This can improve both the positive and negative slope of output transition, which can provide an improvement over CML DAC designs.
  • the in-phase switching facilitates the use of charge coupling capacitors (Cs) to charge pump the gate capacitance (Cg) of the P G01 device.
  • the coupling capacitor preferably has a capacitance an order of magnitude greater than the gate capacitance of the P G01 device for the generation of a logic level. For example, GND (Logic O’) to DVDD (Logic ‘T), charge coupled to, VDD-DVDD * Cs/(Cg+Cs) (Logic ‘T) to VDD (Logic O’).
  • the ratio of Cs/(Cg+Cs) may be corrected by a closed loop voltage biasing generator for the P G02 device.
  • capacitors and the sizing area penalty that might typically result is mitigated by the low gate capacitance Cg of G01 devices (its width (W) and length (L) are set with consideration to the value W/L, which sets the device Rds, and with respect to Lmin and to W * L, which determines its gate capacitance).
  • the capacitors may be Metal-On-Metal capacitors (CMOM) or Metal-lnsulator-Metal capacitors (CMIM), both of which may be placed on top of active devices (N/P G01 or G02), minimizing layout impact.
  • the use of capacitors requires the resetting of its voltage value. In an ideal mode of operation, the voltage across the coupling capacitor should be kept nominally at VDD-DVDD. With the complimentary pair of output stages, a pair of cross-coupled reset switches driven by opposite phase are implemented. This ensures the discharged Cs is replenished via charge division with Cg.
  • the I/O devices (such as 103 in output stage 101 ) comprise G02 devices. In this implementation, the switching of state is performed via the G01 device and the gate voltage of the G02 device is held static as the voltage biasing sets the magnitude of the switched current. In contrast to previous CML DACs (without cascoding devices), where the gate drain capacitance sees a larger delta voltage change (i.e. V gate decreases while V drain increases), in this implementation, V gate is unchanged (i.e. the biasing voltage is static) while Vdrain increases.
  • the lower voltage delta means that a device of lower voltage tolerance can be used to realize the output stage (i.e. the gate drain voltage (Vg S ) difference is lower).
  • Vg S gate drain voltage
  • this also reduces the capacitance seen on the differential output with the reduction of its gate length, for example, an under driven or UD I/O device (G02 can be used). This can enable a higher switching speed, lowering loading capacitance.
  • the push-pull output also enables a similar slew-rate on the positive and negative slopes to be obtained.
  • the generation of a voltage bias applied to the G02 devices fulfils two functional purposes. Firstly, it is used to set the output gain of the DAC transfer function, tracking the variation of a static reference current. Secondly, it allows for compensation of temperature variance when static reference current with zero temperature coefficient is utilized (which may be realized with a band gap reference). An accurate current reference DAC for static operation can be realized without accuracy tradeoff. This current reference DAC can be made to be over-range (i.e. with resolution greater than the required output gain trimming steps) for the purpose of calibrating the output gain linearity (i.e. the swing of the said DAC would nevertheless suffer from distortion, with finite output impedance in a physical implementation).
  • a golden unary segment identical to the output unary segment may be utilized to generate the static voltage biasing which sets the output switched current (i.e. of unary weight). This is shown in Figure 2.
  • the N devices typically exhibit higher charge carrier mobility, they have a higher transconductance (gm) than the P devices.
  • the N voltage bias (VBIASN, node 201 ) may be first determined as a design parameter. For better matching, a device sizing to a high over- drive voltage (V gs - V th ) may be chosen. This may be beneficial for reducing output load capacitance (i.e. for high speed operation).
  • VBIASN and VBIASP static voltage biasing
  • the loop regulation would bias VBIASP (V gs of P device) greater than that of VBIASN.
  • VBIASN may also be set suitably to avoid exceeding this condition.
  • the closed loop regulation bandwidth sets the update rate of the gain adjustment.
  • the static voltage biasing will see complimentary switching of the gate capacitive load (i.e. C gs of G01 switching from ⁇ ’ to T has a compliment, switching from to O’) and thus in operation the need for decoupling (i.e. the output capacitive load of the op amp) is not significant. This may be advantageous for achieving high loop bandwidth (i.e. a high update rate of gain adjustment).
  • VBIASP is generated in a suitable manner.
  • the implementation of charge coupled level shifting is a dynamic phenomenon.
  • a current trim scheme is applied for the adjustment of the P G01 switch (205 in Figure 2) gate voltage bias.
  • the feedback for correction is to observe the current drawn from the common mode voltage source (VCM) in dynamic DAC operation.
  • the trim set point is to reduce the dynamic current (by VCM source) to a minimum, where VCM is deemed a low impedance AC GND.
  • the closed loop feedback is taken from the output of the golden unary segment.
  • the GUS output stage has its operating condition matched to the full-scale voltage swing of intended operation together with output load, with respect to a common mode voltage (VCM).
  • the output load may, for example, be a matched termination load of a transmission line.
  • the VCM is set at VDD/2. However, if the conditions discussed herein are suitably satisfied, the VCM may be lower so as to keep operational devices in saturation. Generally, the modulus of VBIASP may be arranged to be greater than VBIASN.
  • the DAC allows the DAC to be implemented in applications such as a data communication analogue front end (AFE), where typically the transmitter AFE operates at an upscaling of the clocking frequency (i.e. the corresponding receiver may operate in the opposite way).
  • AFE data communication analogue front end
  • the filtering of switching transients through the DVDD voltage domain regulator can aid the reduction of any EMI contribution, for example, cross-talk between the transmitter and receiver through supply noise or any emitted EM via conduction of supply current loop at circuit board level.
  • Patel, Luke Duncan, Brian Toix and Waleed Khalil is a digital signal processing method to minimize DAC cell mismatch. It can in effect translate mismatched induced distortion to white noise.
  • This temporal approach i.e. the pseudo random interchanging switching taps of unary segmented DAC weights
  • can effectively average the output mismatch errors including timing errors, attributable to layout spatial effect, thus improving DAC integral non-linearity (INL).
  • the DAC architecture described herein requires no level shifting of the data path to the DAC current steering element (output stage).
  • the signalling is in the same voltage domain as the DSP, digital filter or data serializer.
  • the current steering element may be an analog front end (AFE) or PHY, which drives the output load (the transmission line with matching termination load).
  • the architecture relieves voltage tolerance of the output stage I/O devices, reducing the capacitive loading on its output.
  • the push-pull output stage improves output slew rate and also reduces the headroom limitation by removing the need for a tail current source (common to a CML DAC) to keep operation in saturation, enabling a wide output signal swing. Closed loop regulation of the gain adjustment may also compensate for temperature variance.
  • the architecture described herein may also allow for easier digital interfacing when considering integration with designs comprising high performance digital cores for signal processing (which are required for high data throughput), together with the design tradeoff for bandwidth and mitigation of mismatch.
  • Linearity of the DAC is offloaded to the digital core, where techniques of dynamic element matching may be applied.
  • 5 bit segmentation entails 31 segments, for 2Bit ⁇ 16+4, 8+2 ⁇ , 3Bit ⁇ 16, 8, 4 ⁇ , 4Bit (16, 8, 4, 2) and 5Bit ⁇ 16, 8, 4, 2, 1 ⁇ . Because not all of the unary segments are utilized in some uses: e.g.
  • Embodiments of the DAC described herein may have an intrinsically faster switching speed (signaling with logic devices implemented on the process smallest feature length (Lmin)), eliminating any level shifting bottleneck.
  • the present architecture has an improved output signal swing limitation in comparison to traditional DAC resolution weighted (for example, for binary or unary weighting) current mode logic (CML) implementations, which impose headroom limitations to maintain devices in saturation (i.e. for both the differential pair and a shared tail current source).
  • CML current mode logic
  • the common mode voltage ideally can be at half of the supply rail voltage.
  • EOS limitation of input/output devices is better tolerated (for example, for P/N channel devices, each sees half of the output voltage swing).
  • a lower EOS voltage limit accommodates for devices of smaller minimum length.
  • a MOSFET device reliably qualified for operating at 1 8V may have its minimum gate length further reduced (for example, from 150nm to 90nm) to reliably qualify for a de-rated operation up to only 1.2 V. This effectively reduces capacitive load by the same ratio (as calculated per unit area, W * L, around a 40% reduction). This can be expected to provide an improvement in bandwidth.
  • Mismatch between segments may also be mitigated with spatial interleaving, using layout common centroid techniques, whether in 1 -dimension or in a folded layout, in both X and Y.
  • the design may also maintain or enhance signal integrity, thereupon improving figure of merits relating to signal linearity or distortion and increasing DAC resolution (i.e. facilitating increasing data throughput).
  • the improvement may be dependent on the implemented modulation scheme (for example PAM-4, PAM-16, DMT, OFDM), as well as electrical noise and fabrication process manufacturing variation (i.e. intrinsic manufacturing mismatches or stochastic variation).
  • BER bit error rate
  • there may be correction of variability attributable to the modulator’s operating temperature variation for example, laser diode output optical power or Mach-Zehnder phase modulation transfer function. Tracking gain adjustment to the transfer function (i.e. the maximum output signal swing) can be applied, and therefore a correction can be applied to compensate.
  • the DAC topology may use G01 devices as switches.
  • the switching noise from the SC pre-drivers directly drives the output stage without the need for level- shifting, and are further low pass filtered through the G01 power domain voltage regulator (for example, through the regulators output decoupling capacitor). This may be beneficial to reduce the EMI signature.
  • Closed loop regulation of the gain adjustment may also compensate for temperature variance.
  • the ease of digital interface is key when considering integration with designs comprsing high performance digital cores for signal processing (as per the need with increasing data throughput), together with the design tradeoff for bandwidth and mitigation of mismatch.
  • Linearity of the DAC is offloaded to the digital core, where techniques of dynamic element matching may be applied.
  • Figure 3(a) illustrates a simplified schematic view of the half circuit of a prior art current mode DAC output, where an ON’ state switch is represented as a resistor, Rds. This demonstrates that, in dynamic operation, the charging and discharging of gate capacitance (Cg) is limited by a biasing current (which is equivalent to the switched current).
  • Figure 3(b) illustrates, in a similar state of operation to the DAC shown in Figure 3(a), the DAC described herein, where charging and discharging of the gate capacitance operates in the same way as a first order resistor-capacitor (RC) network.
  • RC resistor-capacitor
  • Figures 4(a) and 4(b) illustrate the headroom limitation of a prior art design compared to the DAC described herein, respectively.
  • Figure 4(b) highlights the reduced operating headroom, as indicated by the required overdrive or excess voltage required to keep a MOSFET device in the saturation region of operation, compared to the arrangement of Figure 4(a).

Abstract

La présente invention concerne un convertisseur numérique-analogique (CNA) comprenant : une pluralité de segments comprenant chacun un premier étage de sortie et un second étage de sortie, chaque étage de sortie d'un segment étant configuré pour recevoir un signal d'entrée numérique et les étages de sortie étant configurés pour former de manière coopérative une sortie différentielle en fonction du signal d'entrée ; où : chaque étage de sortie d'un segment comprend un premier dispositif de transistor configuré pour fonctionner en tant que source de courant régulée pour attaquer une partie de la sortie différentielle et pour être commuté d'une manière dégénérée de source en fonction de l'état d'un second transistor de l'étage de sortie respectif ; et chaque segment est configuré pour former un segment unaire et la pluralité de segments mettent en œuvre de manière coopérative le CNA. Les avantages comprennent une bande passante élevée, une bonne résolution et une bonne linéarité et une commande de courant complémentaire.
EP19794475.4A 2019-10-22 2019-10-22 Convertisseur numérique-analogique à grande vitesse Pending EP4046278A1 (fr)

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Publication number Priority date Publication date Assignee Title
US5600321A (en) * 1995-06-07 1997-02-04 Advanced Micro Devices Inc. High speed, low power CMOS D/A converter for wave synthesis in network
JP2016063535A (ja) * 2014-09-19 2016-04-25 アイメック・ヴェーゼットウェーＩｍｅｃ Ｖｚｗ ダイレクトデジタル無線周波数変調器
DE112016007195T5 (de) * 2016-09-02 2019-05-29 Intel IP Corporation Ein Digital-zu-Analog-Wandler-Schaltung, ein Verfahren zum Betrieb derselben, eine Vorrichtung und ein Verfahren zum Steuern einer Digital-zu-Analog-Wandler-Zelle

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