EP4010808A4 - Processeurs à base de mémoire - Google Patents

Processeurs à base de mémoire Download PDF

Info

Publication number
EP4010808A4
EP4010808A4 EP20852497.5A EP20852497A EP4010808A4 EP 4010808 A4 EP4010808 A4 EP 4010808A4 EP 20852497 A EP20852497 A EP 20852497A EP 4010808 A4 EP4010808 A4 EP 4010808A4
Authority
EP
European Patent Office
Prior art keywords
memory
based processors
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20852497.5A
Other languages
German (de)
English (en)
Other versions
EP4010808A2 (fr
Inventor
Elad SITY
Eliad HILLEL
Shany BRAUDO
David Shamir
Gal DAYAN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Neuroblade Ltd
Original Assignee
Neuroblade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Neuroblade Ltd filed Critical Neuroblade Ltd
Publication of EP4010808A2 publication Critical patent/EP4010808A2/fr
Publication of EP4010808A4 publication Critical patent/EP4010808A4/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/454—Vector or matrix data
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
EP20852497.5A 2019-08-13 2020-08-13 Processeurs à base de mémoire Pending EP4010808A4 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201962886328P 2019-08-13 2019-08-13
US201962907659P 2019-09-29 2019-09-29
US201962930593P 2019-11-05 2019-11-05
US202062971912P 2020-02-07 2020-02-07
US202062983174P 2020-02-28 2020-02-28
PCT/IB2020/000665 WO2021028723A2 (fr) 2019-08-13 2020-08-13 Processeurs à base de mémoire

Publications (2)

Publication Number Publication Date
EP4010808A2 EP4010808A2 (fr) 2022-06-15
EP4010808A4 true EP4010808A4 (fr) 2023-11-15

Family

ID=74570549

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20852497.5A Pending EP4010808A4 (fr) 2019-08-13 2020-08-13 Processeurs à base de mémoire

Country Status (5)

Country Link
EP (1) EP4010808A4 (fr)
KR (1) KR20220078566A (fr)
CN (1) CN114586019A (fr)
TW (1) TW202122993A (fr)
WO (1) WO2021028723A2 (fr)

Families Citing this family (15)

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Publication number Priority date Publication date Assignee Title
KR102638791B1 (ko) * 2018-09-03 2024-02-22 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
WO2022245382A1 (fr) * 2021-05-18 2022-11-24 Silicon Storage Technology, Inc. Architecture de matrice divisée pour mémoire neuronale analogique dans un réseau neuronal artificiel à apprentissage profond
US11327771B1 (en) * 2021-07-16 2022-05-10 SambaNova Systems, Inc. Defect repair circuits for a reconfigurable data processor
US20230051863A1 (en) * 2021-08-10 2023-02-16 Micron Technology, Inc. Memory device for wafer-on-wafer formed memory and logic
US11914532B2 (en) 2021-08-31 2024-02-27 Apple Inc. Memory device bandwidth optimization
US11947940B2 (en) 2021-10-11 2024-04-02 International Business Machines Corporation Training data augmentation via program simplification
CN116264085A (zh) * 2021-12-14 2023-06-16 长鑫存储技术有限公司 存储系统以及存储系统的数据写入方法
TWI819480B (zh) * 2022-01-27 2023-10-21 緯創資通股份有限公司 加速系統及其動態配置方法
TWI776785B (zh) * 2022-04-07 2022-09-01 點序科技股份有限公司 裸晶測試系統及其裸晶測試方法
TW202406056A (zh) * 2022-05-25 2024-02-01 以色列商紐羅布萊德有限公司 處理系統及方法
US20230393849A1 (en) * 2022-06-01 2023-12-07 Advanced Micro Devices, Inc. Method and apparatus to expedite system services using processing-in-memory (pim)
WO2024027937A1 (fr) * 2022-08-05 2024-02-08 Synthara Ag Réseau informatique compact à topographie mémoire
CN115237036B (zh) * 2022-09-22 2023-01-10 之江实验室 一种针对晶圆级处理器系统的全数字化管理装置
CN115599025B (zh) * 2022-12-12 2023-03-03 南京芯驰半导体科技有限公司 芯片阵列的资源成组控制系统、方法及存储介质
CN116962176B (zh) * 2023-09-21 2024-01-23 浪潮电子信息产业股份有限公司 一种分布式集群的数据处理方法、装置、系统及存储介质

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120005421A1 (en) * 2000-08-21 2012-01-05 Renesas Electronics Corporation Memory controller and data processing system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9612979B2 (en) * 2010-10-22 2017-04-04 Intel Corporation Scalable memory protection mechanism
US20140040622A1 (en) * 2011-03-21 2014-02-06 Mocana Corporation Secure unlocking and recovery of a locked wrapped app on a mobile device
US9262246B2 (en) * 2011-03-31 2016-02-16 Mcafee, Inc. System and method for securing memory and storage of an electronic device with a below-operating system security agent
US8590050B2 (en) * 2011-05-11 2013-11-19 International Business Machines Corporation Security compliant data storage management
US8996951B2 (en) * 2012-11-15 2015-03-31 Elwha, Llc Error correction with non-volatile memory on an integrated circuit
JP6122135B2 (ja) * 2012-11-21 2017-04-26 コーヒレント・ロジックス・インコーポレーテッド 分散型プロセッサを有する処理システム
WO2019025864A2 (fr) * 2017-07-30 2019-02-07 Sity Elad Architecture de processeurs distribués sur la base de mémoires
US10810141B2 (en) * 2017-09-29 2020-10-20 Intel Corporation Memory control management of a processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120005421A1 (en) * 2000-08-21 2012-01-05 Renesas Electronics Corporation Memory controller and data processing system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
STANKOVIC V V ET AL: "DRAM Controller with a Complete Predictor: Preliminary Results", TELECOMMUNICATIONS IN MODERN SATELLITE, CABLE AND BROADCASTING SERVICE S, 2005. 7TH INTERNATIONAL CONFERENCE ON NIS, SERBIA AND MONTENEGRO 28-30 SEPT. 2005, PISCATAWAY, NJ, USA,IEEE, vol. 2, 28 September 2005 (2005-09-28), pages 593 - 596, XP010874696, ISBN: 978-0-7803-9164-2, DOI: 10.1109/TELSKS.2005.1572183 *

Also Published As

Publication number Publication date
TW202122993A (zh) 2021-06-16
CN114586019A (zh) 2022-06-03
WO2021028723A3 (fr) 2021-07-08
KR20220078566A (ko) 2022-06-10
EP4010808A2 (fr) 2022-06-15
WO2021028723A2 (fr) 2021-02-18

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Owner name: NEUROBLADE LTD.

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 15/78 20060101ALI20230706BHEP

Ipc: G06F 12/02 20060101ALI20230706BHEP

Ipc: G11C 7/10 20060101ALI20230706BHEP

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Ipc: G06F 12/14 20060101AFI20231009BHEP