EP3966860A1

EP3966860A1 - Semiconductor power module

Info

Publication number: EP3966860A1
Application number: EP20717861.7A
Authority: EP
Inventors: Christian Marc Lautensack; Alexander Kaiser; Jan Homoth
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2019-05-10
Filing date: 2020-04-08
Publication date: 2022-03-16
Also published as: CN113795917A; US11973064B2; DE102019206820A1; WO2020229063A1; US20220077119A1

Abstract

The invention relates to a semiconductor power module (1) comprising a first power transistor (5LA) and a second power transistor (5LB), which are arranged in parallel between a first collector conductor track (11L) and a first emitter conductor track (9L), wherein a first connection surface of each of the power transistors (5LA, 5LB) is electrically conductively connected to the first collector conductor track (11L) and a second connection surface of each of the power transistors (5LA, 5LB) is electrically conductively connected to the first emitter conductor track (9L), such that a current flowing between the first collector conductor track (11L) and the first emitter conductor track (9L) is divided between the two power transistors (5LA, 5LB) when the power transistors (5LA, 5LB) are turned on in each case by means of an applied control voltage, wherein a first external power contact (P) is contacted with the first collector conductor track (11) directly at a first contact region (KB1), wherein a second external power contact (TL) is contacted with the first emitter conductor track (9L) at a second contact region (KB2) via a first connecting element (13), and wherein the second contact region (KB2) is positioned mechanically asymmetrically between the power transistors (5LA, 5LB) connected to the first emitter conductor track (9L) in such a way as to result in an electrical symmetry with identical effective control voltages at the two power transistors (5LA, 5LB).

Description

description

title

Semiconductor power module

The invention relates to a semiconductor power module with a first power transistor and a second power transistor, which are arranged in parallel between a first collector conductor track and a first emitter conductor track. In each case, a first connection surface of the power transistors is connected to the first collector conductor track, and a second connection surface of the power transistors is connected to the first emitter conductor track in an electrically conductive manner, so that a current flowing between the first collector conductor track and the first emitter conductor track is divided between the two power transistors, when the power transistors are each switched lei tend via an applied control voltage.

The power electronics for hybrid electric vehicles or electric vehicles including associated semiconductor power modules are increasingly subject to high space requirements, consequently the semiconductor power modules and electrical leads are designed to be smaller. At the same time, the current density increases due to increased power requirements. However, smaller supply lines and higher currents result in higher electrical losses (both ohmic and frequency-affected). Therefore, space-optimized semiconductor power modules are usually built mechanically in the longitudinal direction, but this means that the electrical properties are highly asymmetrical. Therefore, when power transistors are connected in parallel, a first power transistor can take over the switch-on process and a second power transistor takes over the switch-off process. Particularly when a short circuit is switched off, this can lead to the short circuit capability being severely restricted. Fig. 2 shows an example of a so-called B2 bridge 1A 'designed from the state of the art semiconductor power module, which has four IGBT (IGBT: Insulated Gate Bipolar Transistor) designed power transistors 5LA, 5LB, 5HA, 5HB and two Free wheeling diodes 3L, 3H includes. As can also be seen from Fig. 2, a first power transistor 5LA, a second power transistor 5LB and a first freewheeling diode 3L are arranged between a first collector conductor track 11L and a first emitter conductor track 9L and form a low-side of the semiconductor power module. In addition, a third power transistor 5HA, a fourth power transistor 5HB and a second freewheeling diode 3H are arranged between a second collector conductor track 11H and a second emitter conductor track 9H and form a high side of the semiconductor power module. The two collector conductor tracks 11L, 11H are arranged at a distance from one another in the same plane and are coupled to a cooling device (not shown). Therefore, the two collector conductor tracks 11L, 11H each act as a heat sink for cooling the semiconductor power module 1. The four power transistors 5LA, 5LB, 5HA, 5HB and the two free-wheeling diodes 3L, 3H are each arranged on the two collector conductor tracks 11L, 11H, with one each The first connection surface of the power transistors 5LA, 5LB, 5HA, 5HB and the freewheeling diodes 3L, 3H is electrically conductively connected to a corresponding collector conductor track 11L, 11B. A second connection surface of the power transistors 5LA, 5LB, 5HA, 5HB and the freewheeling diodes 3L, 3H is in each case connected in an electrically conductive manner to a corresponding emitter conductor track 9L, 9H. In addition, the power transistors 5LA, 5LB, 5HA, 5HB and the freewheeling diodes 3L, 3H are cooled via the respective collector tracks 11L, 11H.

As can also be seen from FIG. 2, a first external power contact P, to which an alternating voltage potential is applied, is connected to the surface of the first collector conductor track 11L at a first contact area KB1 and is cooled by this. A second external power contact TL, to which a first direct voltage potential is applied, is connected to a second contact area KB2 with the first emitter conductor line 9L and is connected via the first emitter conductor line, through the power transistors 5LA, 5LB and the free-running diodes 3L and via the first collector conductor line 11L cooled. A third external power contact TH, at which a second DC voltage potential is applied, is connected at a third contact area KB3 to the surface of the second collector conductor track 11H and is cooled by this. The second emitter conductor track 9H is electrically connected to the first collector conductor track 11L via a connecting element at a fourth contact area KB4. In addition, the semiconductor power module 1 shown has further external contacts KH, EH, G1H, G2H, KL, EL, G1L, G2L. In this case, the external contact KL is connected to the first collector conductor track 11L or the collector connections of the power transistors 5LA, 5LB of the low side of the semiconductor power module via a bonding wire. The external contact EL is connected to the first emitter conductor track 9L or emitter connections of the power transistors 5LA, 5LB of the low side of the semiconductor power module via a bond wire. The external contact G1L is connected to a gate connection of the first power transistor 5LA of the low side of the semiconductor power module via a bonding wire. The external contact G2L is connected to a gate connection of the second power transistor 5LB of the low side of the semiconductor power module via a bonding wire. Analogously, the external contact KH is connected to the second collector conductor track 11H or collector connections of the power transistors 5HA, 5HB of the high side of the semiconductor power module via a bond wire. The external contact EH is connected via a bonding wire to the second Emitterlei terbahn 9H or emitter connections of the power transistors 5HA, 5HB of the high side of the semiconductor power module. The external contact G1H is connected to a gate connection of the third power transistor 5HA of the high side of the semiconductor power module via a bonding wire. The external contact G2H is connected to a gate terminal of the fourth power transistor 5HB of the high side of the semiconductor power module 1 via a bonding wire.

Disclosure of the invention

The semiconductor power module with the features of independent claim 1 has the advantage that the effectively effective inductances and ohmic resistances of the two power transistors arranged in parallel between a first collector conductor track and a first emitter conductor track are matched to one another via a special wiring system. This leads to symmetrical control voltages at the two parallel power transistors and to even switching on and off, so that during the During normal operation and in the event of a short circuit, the energy input is evenly distributed over the two parallel power transistors. In this way, an ideal chip area can be determined for both power transistors during normal operation. In the event of a short circuit, the equal distribution of the currents results in the maximum exhaustion of the thermal destruction limit of the two power transistors. In addition, due to the electrical symmetry with the same effective control voltages on the two power transistors, the distance between the two parallel power transistors can be increased, which enables a better cooling connection.

Embodiments of the present invention provide a semiconductor power module with a first power transistor and a second power transistor, which are arranged in parallel between a first collector conductor track and a first emitter conductor track, a first connection surface of the power transistors to the first collector conductor track, and a second each Connection surface of the power transistors is electrically conductively connected to the first emitter conductor, so that a current flowing between the first collector conductor and the first emitter conductor is divided between the two power transistors when the power transistors are each switched on via an applied control voltage. In this case, a first external power contact is in direct contact with the first collector conductor path at a first contact area. A second external power contact is in contact with the first emitter conductor track via a first connecting element at a second contact area, the second contact area being positioned mechanically asymmetrically between the power transistors connected to the first emitter conductor track in such a way that electrical symmetry with the same effective control voltages is established between the two Power transistors results.

The measures and developments listed in the dependent claims, advantageous improvements of the semiconductor power module specified in the independent patent claim 1 are possible.

It is particularly advantageous that a third power transistor and a fourth power transistor in parallel between a second collector conductor track and a second emitter conductor track can be arranged, wherein in each case a first connection surface of the power transistors can be electrically conductively connected to the second collector conductor track, and in each case a second connection surface of the power transistors can be electrically conductively connected to the second emitter conductor track, so that a between the second collector conductor track and the second emitter conductor track can divide current flowing to the two power transistors when the power transistors are each switched on via an applied control voltage. Here, a third external power contact can be contacted directly at a third contact area with the second collector conductor, and the second emitter conductor can be contacted with the first collector conductor via a second connection element at a fourth contact area. In addition, the first power transistor and the second power transistor connected in parallel can form a low-side path between the second external power contact and the first external power contact, and the third power transistor and the fourth power transistor connected in parallel can form a high-side path between the third Form external power contact and the first external power contact. Furthermore, a first freewheeling diode can be arranged parallel to the first power transistor and to the second power transistor between the first collector conductor track and the first emitter conductor track. A second freewheeling diode can be arranged parallel to the third power transistor and the fourth power transistor between the second collector conductor track and the second emitter conductor track. As a result, the semiconductor power module can be used as a B2 bridge, with an AC voltage potential then applied to the first external power contact, a first DC voltage potential applied to the second external power contact, and a second DC voltage potential applied to the third external power contact. The power transistors can be implemented as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors, metal-oxide-semiconductor field-effect transistors), etc.

In a further advantageous embodiment of the semiconductor power module, the fourth contact area can be mechanical based on the distance between the third power transistor and the fourth power transistor connected in parallel and be positioned electrically symmetrically between the two power transistors. This leads to symmetrical control voltages at the two parallel power transistors and to even switching on and off, so that the energy input is evenly distributed over the two parallel power transistors during normal operation and in the event of a short circuit.

In a further advantageous embodiment of the semiconductor power module, the second contact area can be moved mechanically in the direction of the second power transistor based on the distance between the first power transistor and the second power transistor, which is spatially further away from the second power contact than the first power transistor. This increases the effective inductance and effective ohmic resistance of the first power transistor and reduces the effective inductance and effective ohmic resistance of the second power transistor, whereby the effective inductances and ohmic resistances of the two power transistors are matched to one another.

In a further advantageous embodiment of the semiconductor power module, a first control voltage can be applied between an external emitter contact and a first external gate contact connected to a control terminal of the first power transistor. Furthermore, a second control voltage can be applied between the external emitter contact and a second external gate contact connected to a control connection of the second power transistor. In addition, the external emitter contact can be connected to the first emitter conductor path at an emitter contact point. Here, the emitter contact point with the first emitter conductor track can be mechanically shifted in the direction of the first power transistor based on the distance between the first power transistor and the second power transistor.

In a further advantageous embodiment of the semiconductor power module, the first connection element can be U-shaped, so that, apart from the second contact area, an air gap is formed between the second connection element and the second emitter conductor track. This enables a special simple and inexpensive implementation of the positioning of the second contact area. In addition, the U-shaped design of the first connecting element allows a simple implementation of a heat dissipation path for cooling the second external power contact.

In a further advantageous embodiment of the semiconductor power module, a cooling arrangement with an electrically insulating intermediate layer can be arranged in the area of the second external power contact, which is connected with the first connection element by a first solder layer and with the first collector conductor by a second solder layer, with the electrically insulating intermediate layer can form an electrically insulated heat dissipation path between the first connecting element and the first collector conductor track, which cools the second external power contact. The electrically isolated heat dissipation path makes it possible to thermally couple the second external power contact of the semiconductor module, which is not directly connected to the surface of a collector conductor track acting as a heat sink, with the first collector conductor track acting as a heat sink and to cool it. As a result, such external power contacts of the semiconductor power module can also be cooled and the power loss can be dissipated via the cooling path of the semiconductor power module. Through the cooling arrangement, the second external power contact is thermally coupled to the cooling system of the semiconductor power module, so that a defined cooling of the external power contact is possible. In addition, the thermal performance of the semiconductor power module is advantageously decoupled from external power loss. In addition, the power transistors do not experience any additional heat input due to the connection to external busbars and can therefore be used more optimally.

An embodiment of the invention is shown in the drawing and is explained in more detail in the following description. In addition, a semiconductor power module known from the prior art and described in the introduction to the description is shown in the drawing. In the drawing, the same reference symbols designate components or elements that perform the same or analogous functions. Brief description of the drawings

Fig. 1 shows a schematic representation of an embodiment of a semiconductor power module according to the invention.

Fig. 2 shows a schematic representation of a semiconductor power module known from the prior art.

FIG. 3 shows a schematic electrical circuit diagram of the semiconductor power module according to the invention from FIG. 1.

FIG. 4 shows a characteristic diagram of the switching behavior of the known semiconductor power module from FIG. 2.

FIG. 5 shows a characteristic diagram of the switching behavior of the semiconductor power module according to the invention from FIGS. 1 and 3.

Embodiments of the invention

As can be seen from FIGS. 1 and 3, the illustrated embodiment of a semiconductor power module 1 according to the invention comprises a first power transistor 5LA and a second power transistor 5LB, which are arranged in parallel between a first collector conductor track 11L and a first emitter conductor track 9L, each with a first connection surface of the power transistors 5LA, 5LB is electrically conductively connected to the first collector conductor track 11L and a second connection surface of the power transistors 5LA, 5LB is connected to the first emitter conductor track 9L, so that a current flowing between the first collector conductor track 11L and the first emitter conductor track 9L is applied to the two Divided power transistors 5LA, 5LB when the power transistors 5LA, 5LB are each switched on via an applied control voltage. A first external power contact P is in direct contact with the first collector conductor 11 at a first contact area KB1. A second external power contact TL is in contact with the first emitter conductor track 9L via a first connecting element 13 on a second contact area KB2. the second contact area KB2 being mechanically asymmetrically positioned between the power transistors 5LA, 5LB connected to the first emitter conductor line 9L so that electrical symmetry results with the same effective control voltages at the two power transistors 5LA, 5LB.

As can also be seen from FIGS. 1 and 3, the illustrated semiconductor power module 1 comprises a third power transistor 5HA and a fourth power transistor 5HB, which are arranged in parallel between a second collector conductor track 11H and a second emitter conductor track 9H, each having a first connection surface of the power transistors 5HA, 5HB is connected to the second collector conductor track 11 H, and in each case a second connection surface of the power transistors 5HA, 5HB is electrically conductively connected to the second emitter conductor track 9H, so that a conductor track 11 H and the second emitter conductor track 9H flows between the second collector conductor track 11H The current is divided between the two power transistors 5HA, 5HB when the power transistors 5HA, 5HB are each switched on via an applied control voltage. In addition, a third external power contact TH is contacted directly at a third contact area KB3 with the second collector conductor track 11H. The second emitter conductor line 9H is in contact with the first collector conductor line 11L via a second connecting element 12 at a fourth contact area KB4. As can also be seen from Fig. 1, the fourth contact area KB4 is positioned mechanically and electrically symmetrically between the two power transistors 5HA, 5HB based on the distance between the third power transistor 5HA and the parallel connected fourth power transistor 5HB.

As can also be seen from FIGS. 1 and 3, the semiconductor power module 1 in the illustrated embodiment is designed as a B2 bridge 1A. Therefore, an alternating voltage potential is applied to the first external power contact P. A first DC voltage potential is applied to the second external power contact TL, and a second DC voltage potential is applied to the third external power contact TH. Analogous to the semiconductor power module known from the prior art shown in FIG. 2, the power transistors 5LA, 5LB, 5HA, 5HB are each designed as IGBT (IGBT: Insulated Gate Bipolar Transistor - bipolar transistors with insulated gate). In the illustrated embodiment As an example of the semiconductor power module 1, the first power transistor 5LA and the second power transistor 5LB connected in parallel form a low-side path between the second external power contact TL and the first external power contact P. The third power transistor 5HA and the fourth power transistor 5HB connected in parallel form a high-side path between the third external power contact TH and the first external power contact P. In addition, a first freewheeling diode 3L is arranged in the low-side path parallel to the first power transistor 5LA and to the second power transistor 5LB between the first collector conductor track 11L and the first emitter conductor track 9L. A second freewheeling diode 3H is arranged in the high-side path parallel to the third power transistor 5HA and the fourth power transistor 5HB between the second collector conductor track 11H and the second emitter conductor track 9H. The two collector conductor tracks 11L, 11H are spaced from each other in the same plane and are coupled to a cooling device, not shown. Therefore, the two collector conductor tracks 11L, 11H each act as a heat sink for cooling the semiconductor power module 1. In addition, the power transistors 5LA, 5LB, 5HA, 5HB and the free-wheeling diodes 3L, 3H are cooled via the respective collector conductor track 11L, 11H.

The first external power contact P is connected directly to the surface of the first collector conductor track 11L at the first contact area KB1 and is cooled by this. In the exemplary embodiment shown, the second external power contact TL is connected to the first emitter conductor line 9L via the first connecting element 14 at a second contact area KB2. The first connec tion element 13 is U-shaped in the illustrated embodiment, so that apart from the second contact area KB2, an air gap 15 is formed between the second connection element 13 and the second emitter conductor 9B. Furthermore, in the exemplary embodiment shown, a cooling arrangement 20 with an electrically insulating intermediate layer (not shown) is arranged in the area of the second external power contact TL, which is materially connected to the first connection element 13 by a first solder layer and to the first collector conductor track 11L by a second solder layer. The electrically insulating intermediate layer forms an electrically insulated heat dissipation path between the first connecting element 13 and the first collector conductor track 11L, which is the second external Power contact TL cooled. The electrically insulating interlayer, not shown, is designed, for example, as an AM B ceramic substrate and has good to very good thermal conductivity in the range from 20 to 200 W / mK. The AMB ceramic substrate has a copper structure as a solderable surface on both surfaces so that the corresponding cohesive solder layers for heat dissipation between the first connecting element 13 and the electrically insulating intermediate layer and between the electrically insulating intermediate layer and the first collector conductor track 11L can be produced. Of course, the electrically insulating intermediate layer can alternatively be designed as a DBC substrate or as an IMS substrate or as a piece of pure silicon. The third external power contact TH is connected directly to the surface of the second collector conductor track 11H at the third contact area KB3 and is cooled by this. In addition, the illustrated semiconductor power module 1 has further external contacts KH, EH, G1H, G2H, KL, EL, G1L, G2L. Here, the external contact KL is connected to the first collector track 11L or the collector connections of the power transistors 5LA via a bonding wire,

5LB connected to the low side of the semiconductor power module 1. The external contact EL is connected to the first emitter conductor track 9L or emitter connections of the power transistors 5LA, 5LB of the low-side of the semiconductor power module 1 via a bonding wire. The external contact G1L is connected to a gate connection of the first power transistor 5LA of the low side of the semiconductor power module 1 via a bonding wire. The external contact G2L is connected to a gate connection of the second power transistor 5LB of the low side of the semiconductor power module 1 via a bonding wire. Analogously, the external contact KH is connected to the second collector conductor track 11 H or collector connections of the power transistors 5HA, 5HB of the high side of the semiconductor power module 1 via a bonding wire. The external contact EH is connected to the second emitter conductor track 9H or emitter connections of the power transistors 5HA, 5HB of the high side of the semiconductor power module 1 via a bonding wire. The external contact G1H is connected to a gate connection of the third power transistor 5HA of the high side of the semiconductor power module 1 via a bonding wire. The external contact G2H is connected to a gate connection of the fourth power transistor 5HB of the high side of the semiconductor power module 1 via a bonding wire. As can also be seen from Fig. 1, the second contact area KB2 is based on the distance between the first power transistor 5LA and the second power transistor 5LB mechanically shifted in the direction of the second power transistor 5LB, which is spatially further away from the second power contact TL than the first Power transistor 5LA. In addition, a first control voltage is applied between the external emitter contact EL and the first external gate contact G1L connected to the control terminal of the first power transistor 5LA. A second control voltage is applied between the external emitter contact EL and the second external gate contact G2L connected to the control terminal of the second power transistor 5LB. The external emitter contact EL is connected to the first emitter conductor track 9LB at an emitter contact point EK. Here, the emitter contact point EK with the first emitter conductor track 9LB is mechanically displaced in the direction of the first power transistor 5LA in relation to the distance between the first power transistor 5LA and the second power transistor 5LB.

In FIG. 3, R each denotes a corresponding line resistance and L denotes a corresponding line inductance. The factors marked x can be set by positioning the second contact area KB2 and / or the emitter contact point EK in order to adapt the ohmic line resistances and line inductances at the emitter of the power transistors 5LA, 5LB or at the anode of the freewheeling diode 3L.

As he can see by comparing the two characteristic diagrams in Fig. 4 and 5, the current distribution to the two power transistors 5LA, 5LB can be set by embodiments of the semiconductor power module 1 according to the invention so that a current difference Dl shown in FIG Current flow I-5LA through the first power transistor 5LA and a current flow I-5LB through the second power transistor 5LB is significantly lower in comparison to the current difference Dl 'shown in FIG. 4 for the same voltage profile UCE-5L.

Claims

Expectations

1. Semiconductor power module (1) with a first power transistor (5LA) and a second power transistor (5LB), which are arranged in parallel between a first collector conductor track (11L) and a first emitter conductor track (9L), a first connection surface of the power transistors (5LA, 5LB) is electrically conductively connected to the first collector conductor track (11L) and a second connection surface of each of the power transistors (5LA, 5LB) is connected to the first emitter conductor track (9L), so that there is a connection between the first collector conductor track (11L) and the first emitter conductor track ( 9L) divides the current flowing to the power transistors (5LA, 5LB) when the power transistors (5LA, 5LB) are each switched on via an applied control voltage, with a first external power contact (P) directly on a first contact area (KB1) is contacted with the first collector conductor track (11), a second external power contact (T L) is contacted via a first connecting element (13) at a second Kontaktbe rich (KB2) with the first emitter conductor track (9L), and where the second contact area (KB2) is mechanically asymmetrical between the power connected to the first emitter conductor track (9L) transistors (5LA, 5LB) is positioned so that there is electrical symmetry with the same effective control voltages on the two power transistors (5LA, 5LB).

2. Semiconductor power module (1) according to claim 1, characterized in that a third power transistor (5HA) and a fourth power transistor (5HB) are arranged in parallel between a second collector conductor (11H) and a second emitter conductor (9H), a first in each case Connection surface of the power transistors (5HA, 5HB) with the second collector conductor track (11H) and a second connection surface of each of the power transistors (5 HA, 5 HB) is electrically connected to the second emitter conductor track (9H), so that there is a connection between the second collector conductor track (11H) and the second emitter trace (9H) divides the current flowing to the two power transistors (5HA, 5HB) when the power transistors (5HA, 5HB) each are switched conductive via an applied control voltage, a third external power contact (TH) being contacted directly at a third contact area (KB3) with the second collector conductor track (11H), and the second emitter conductor track (9H) via a second connection element (12 ) is contacted at a fourth contact area (KB4) with the first collector conductor (11L).

3. Semiconductor power module (1) according to claim 2, characterized in that the first power transistor (5LA) and the parallel-connected second power transistor (5LB) form a low-side path between the second external power contact (TL) and the first external power contact (P ) form, and the third power transistor (5HA) and the parallel-connected fourth power transistor (5HB) form a high-side path between the third external power contact (TH) and the first external power contact (P).

4. Semiconductor power module (1) according to claim 2 or 3, characterized in that a first freewheeling diode (3L) parallel to the first power transistor (5LA) and the second power transistor (5LB) between tween the first collector conductor (11L) and the first emitter conductor track (9L) is arranged, and a second free-wheeling diode (3H) is arranged parallel to the third power transistor (5HA) and the fourth power transistor (5HB) between the second collector conductor (11H) and the second emitter conductor (9H),

5. Semiconductor power module (1) according to one of claims 2 to 4, characterized in that the fourth contact area (KB4) based on the distance between the third power transistor (5HA) and the fourth power transistor (5HB) connected in parallel is mechanically and electrically symmetrical between the two power transistors (5HA, 5HB) is positioned.

6. semiconductor power module (1) according to any one of claims 1 to 5, characterized in that the second contact area (KB2) based on the Distance between the first power transistor (5LA) and the second power transistor (5LB) is mechanically shifted in the direction of the second power transistor (5LB), which is spatially further away from the second power contact (TL) than the first power transistor (5 LA).

7. semiconductor power module (1) according to claim 6, characterized in that a first control voltage between an external Emitterkon clock (EL) and a control terminal of the first power transistor (5LA) connected to the first external gate contact (G1L) is applied.

8. Semiconductor power module (1) according to claim 6 or 7, characterized in that a second control voltage is applied between the external emitter contact (EL) and a second external gate contact (G2L) connected to a control terminal of the second power transistor (5LB).

9. Semiconductor power module (1) according to claim 7 or 8, characterized in that the external emitter contact (EL) is connected to the first emitter conductor (9LB) at an emitter contact (EK).

10. Semiconductor power module (1) according to claim 9, characterized in that the emitter contact point (EK) with the first emitter conductor track (9LB) based on the distance between the first power transistor (5LA) and the second power transistor (5LB) mechanically in the direction of the first Power transistor (5LA) is shifted.

11. Semiconductor power module (1) according to one of claims 1 to 10,

characterized in that the first connecting element (13) is U-shaped so that, apart from the second contact area (KB2), an air gap (15) is formed between the second connecting element (13) and the second emitter conductor track (9B).

12. Semiconductor power module (1) according to one of claims 1 to 11, characterized in that a cooling arrangement (20) with an electrically insulating intermediate layer is arranged in the area of the second external power contact (TL), which is firmly bonded to the first by a first solder layer Connection element (13) and is firmly connected to the first collector conductor track (11L) by a second solder layer, the electrically insulating intermediate layer forming an electrically insulated heat dissipation path between the first connection element (13) and the first collector conductor track (11L), which the second external power contact (TL) is cooled.