EP3891792A4 - Kapazitive kopplung in einer direkt gebondeten schnittstelle für mikroelektronische vorrichtungen - Google Patents

Kapazitive kopplung in einer direkt gebondeten schnittstelle für mikroelektronische vorrichtungen Download PDF

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Publication number
EP3891792A4
EP3891792A4 EP19892672.7A EP19892672A EP3891792A4 EP 3891792 A4 EP3891792 A4 EP 3891792A4 EP 19892672 A EP19892672 A EP 19892672A EP 3891792 A4 EP3891792 A4 EP 3891792A4
Authority
EP
European Patent Office
Prior art keywords
direct
capacitive coupling
microelectronic devices
bonded interface
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19892672.7A
Other languages
English (en)
French (fr)
Other versions
EP3891792A1 (de
Inventor
Belgacem Haba
Arkalgud R. Sitaram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Technologies LLC
Original Assignee
Invensas LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/212,248 external-priority patent/US10811388B2/en
Application filed by Invensas LLC filed Critical Invensas LLC
Publication of EP3891792A1 publication Critical patent/EP3891792A1/de
Publication of EP3891792A4 publication Critical patent/EP3891792A4/de
Pending legal-status Critical Current

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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP19892672.7A 2018-12-06 2019-08-28 Kapazitive kopplung in einer direkt gebondeten schnittstelle für mikroelektronische vorrichtungen Pending EP3891792A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/212,248 US10811388B2 (en) 2015-09-28 2018-12-06 Capacitive coupling in a direct-bonded interface for microelectronic devices
PCT/US2019/048530 WO2020117336A1 (en) 2018-12-06 2019-08-28 Capacitive coupling in a direct-bonded interface for microelectronic devices

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EP3891792A4 true EP3891792A4 (de) 2022-12-28

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WO (1) WO2020117336A1 (de)

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CN117293092A (zh) * 2021-09-06 2023-12-26 长江存储科技有限责任公司 半导体结构
CN117425329A (zh) * 2022-07-07 2024-01-19 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

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US20160020235A1 (en) * 2014-07-16 2016-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitance device in a stacked scheme and methods of forming the same
US20160043060A1 (en) * 2013-05-16 2016-02-11 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method for fabricating the same
US20170092620A1 (en) * 2015-09-28 2017-03-30 Invensas Corporation Capacitive Coupling of Integrated Circuit Die Components
US20180240860A1 (en) * 2017-02-23 2018-08-23 International Business Machines Corporation Microstructure modulation for 3d bonded semiconductor structure with an embedded capacitor

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KR100881182B1 (ko) * 2006-11-21 2009-02-05 삼성전자주식회사 웨이퍼 사이에 형성된 디커플링 커패시터, 그 디커플링커패시터를 포함하는 웨이퍼 스택 패키지, 및 그 패키지제조 방법
KR101046394B1 (ko) * 2010-02-03 2011-07-05 주식회사 하이닉스반도체 스택 패키지
US9953941B2 (en) * 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding

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US20160043060A1 (en) * 2013-05-16 2016-02-11 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method for fabricating the same
US20160020235A1 (en) * 2014-07-16 2016-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitance device in a stacked scheme and methods of forming the same
US20170092620A1 (en) * 2015-09-28 2017-03-30 Invensas Corporation Capacitive Coupling of Integrated Circuit Die Components
US20180240860A1 (en) * 2017-02-23 2018-08-23 International Business Machines Corporation Microstructure modulation for 3d bonded semiconductor structure with an embedded capacitor

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WO2020117336A1 (en) 2020-06-11
CN113169159A (zh) 2021-07-23

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