EP3888212A1

EP3888212A1 - Analogue voltage programming

Info

Publication number: EP3888212A1
Application number: EP20726088.6A
Authority: EP
Inventors: Martin BÜRKERT; Thomas Kilian; Sebastian Schroth; Fabian SCHNEIDER; Georg Wiedmann
Original assignee: Ebm Papst Mulfingen GmbH and Co KG
Current assignee: Ebm Papst Mulfingen GmbH and Co KG
Priority date: 2019-05-28
Filing date: 2020-05-14
Publication date: 2021-10-06
Also published as: DE102019114228A1; US11977400B2; US20220187860A1; KR102672303B1; WO2020239454A1; CN211506890U; KR20220011610A

Abstract

The invention relates to an analogue circuit arrangement (1) for variably setting a voltage U_out within defined voltage limits, comprising a non-inverting adder (10) having a positive input (11), wherein a voltage divider (20) comprising at least a first stage (21) and a second stage (22) is connected to the positive input (11) of the adder (10), wherein at least one stage comprises a parallel circuit of n resistors (R1, R2,..., Rn) which are each connected in series in a conduction path (L1, L2,..., Ln) to an overcurrent protection device (F1, F2,.., Fn), and at least one device (30) for actively changing one or more of the overcurrent protection devices (F1, F2,.., Fn) into a state which interrupts the respective affected conduction path (L1, L2,..., Ln).

Description

Analog voltage programming

Description:

The invention relates to an analog circuit that makes it possible to adjust a voltage variably within defined limits.

Electronic circuits almost always require a reference voltage that is constant, ie both independent of the input voltage and stable, ie independent of the current consumption and sufficiently accurate ie remains in the desired tolerance range. However, it is also desirable that such a voltage can be variably set to a certain value depending on the application.

For this purpose, digital circuit solutions are known in the prior art, which, however, are problematic with regard to safety-relevant components and thus VDE and UL approval procedures. In the case of product approvals, the relevant product standards must be complied with, which results in requirements for the selection of approved products. At UL, so-called “recognized components” are typically required in order to obtain approval in a device. There are also analog IC components that can be programmed digitally (e.g. via SPI). In practice, these also have the problem that difficulties can arise with the approval procedures at VDE and UL.

A required reference voltage can also be implemented using a simple voltage divider by equipping the printed circuit board, with the reference voltage then no longer being variably adjustable. In the prior art, programmable digital potentiometers are also known. With these, a resistor network can be digitally programmed to the desired value via a controller. The disadvantage here is that, in the case of an assembly option, the reference voltage is already set in the production process. However, it is desirable to determine the definition later in the customer application. The user should be able to freely choose the required reference voltage for his application within certain voltage limits in order to e.g. B. to be able to connect a motor of your choice to the respective electronics.

The voltage must also be generated analog. If it is required for safety-relevant circuits, it must not be programmed / changed using software. can be changed.

The invention is therefore based on the object of overcoming the aforementioned disadvantages and of providing a circuit arrangement which is safe to use and with which the possibility is made available of setting the voltage within certain voltage limits and preferably ensuring that the once the set voltage cannot be changed as intended.

This object is achieved by the combination of features according to patent claim 1. According to the invention, an analog circuit arrangement is provided for this purpose for the variable setting of a voltage U _out within defined voltage limits, comprising a non-inverting adder with a positive input, a voltage divider comprising at least a first stage and a second stage being connected to the positive input of the adder, At least one stage consists of a parallel connection of n resistors, which are each connected in series in a line path of the voltage divider to an overcurrent protection device, as well as at least one device to activate one or more of the overcurrent protection devices (e.g. by a specifically initiated overcurrent) to bring the respective affected line path interrupting state. In a particularly advantageous embodiment, it is provided that the overcurrent protection devices are designed as fuses that are specifically burned out for deactivation.

Another advantageous embodiment of the invention provides that the first stage of the preferably two-stage voltage divider is formed from a fixed resistor.

By blowing the fuses in a controlled manner, the Change the total resistance of the parallel connection and thus the total voltage at the intermediate tap of the voltage divider, which is connected to the input of the adder. As a result, the voltage U _out at the output of the non-inverting adder can thus be changed or set. Depending on which or how many of the fuses are blown, a different output voltage can be "programmed" analogously, ie permanently set.

After completion of the measures to burn out or energize the overcurrent protection devices, the remaining, not blown fuses are locked against a burning process. This means that once the voltage has been set, it can no longer be changed as intended after locking.

To ensure and check the function of the circuit, the reference voltage is read back via the ADC of a controller after the burn process is complete. This will detect irregularities or unsuccessfully completed burn-through processes.

In a preferred embodiment of the invention it is therefore provided that said device for "deactivating the conduction paths in the parallel connection of the voltage divider" as an emitter circuit with current negative feedback by means of an NPN transistor and a PNP

Transistor is realized whose base is connected to the collector of the NPN transistor via an intermediate tap of a wide Ren voltage divider.

It is also advantageously provided that the base of the NPN transistor is controlled by a microcontroller (pC), preferably via a series resistor. The control signal for burning a respective fuse tion or overcurrent protection device can, for. B. from a classic I / O output of a microcontroller (pC) or from a needle bed adapter be mounted.

The current flow into the base of the NPN transistor can be adjusted as required via a series resistor. A pull-down resistor between base and emitter prevents uncontrolled switching on of the NPN transistor. The base can also be connected to a further signal (LOCK), which ensures that the control signals can be "faded out" or "deactivated" if required.

According to the invention, it is provided for this purpose that the base, which is connected to the signal connection (LOCK), is connected to the emitter of the NPN transistor via the said pull-down resistor.

Also advantageous is an embodiment in which the collector of the PNP transistor of the (respective) device for triggering the overcurrent protection devices can be or are connected to each of these in order to selectively bring the respectively connected overcurrent protection device into a state that interrupts the relevant line path .

In a likewise preferred embodiment of the invention it is provided that a circuit for deactivating or locking the device is also provided, which means that the device is designed to keep that state stable in a conduction path and to prevent this from being changed subsequently, by z. B. another tripping process of a not yet tripped overcurrent protection device is prevented.

Another aspect of the present invention relates to a method for variably setting a voltage U _out within defined voltage limits using a circuit arrangement as described above with the following step or steps:

Selective energization of one or more of the overcurrent protection devices with an overcurrent generated with the device in order to to bring the transmission path into the electrically separated state and to change it as intended by the voltage of the voltage divider at the input and consequently at the output of the adder.

It is further preferred to design the method in such a way that after the selective triggering or energization of one or more of the overcurrent protection devices with an overcurrent, the respective device connected to an overcurrent protection device or a blown fuse that has not yet been triggered is deactivated by means of the interlocking circuit .

Other advantageous developments of the invention are characterized in the dependent claims or are shown in more detail below together with the description of the preferred embodiment of the invention with reference to the figures. Show it:

Fig. 1 shows a circuit arrangement according to the invention for adjustable

Voltage generation;

2 shows a circuit arrangement according to the invention for triggering an overcurrent protection device or fuse,

3 shows a representation of the time sequence of a triggering process of a fuse, FIG. 4 shows a circuit arrangement according to the invention for locking the circuit arrangement for triggering an overcurrent protection device according to FIG. 2 and

Fig. 5 shows an exemplary representation of the timing for a steep a desired voltage.

In the following, the invention is explained in more detail using an exemplary embodiment with reference to FIGS. 1 to 5. An analog circuit arrangement 1 according to the invention is shown in FIG. The analog circuit arrangement 1 is designed for the variable setting of a voltage U _out within defined voltage limits at the non-inverting adder 10 shown. The adder 10 has a positive input 11 and a negative input 12. The analog ground reference potential is denoted by AGND. At the positive input 11 of the adder 10, a two-stage voltage divider 20 is connected. The voltage divider 20 consists of a first stage 21 with a fixed resistor R _f and a second stage 22. The second stage 22 consists of a parallel connection of 4 resistors R1, R2, R3 and R4, each in a parallel line path L1, L2, L3 and L4 between the ground reference potential and the center tap 23 on the voltage divider 20 are arranged.

Each resistor R1, R2, R3 and R4 is connected in series with an overcurrent protection device F1, F2, F3, F4 in the respective line path L1, L2, L3 and L4. A resistor R _{x is provided} in the conduction path that runs from the analog ground reference potential to the negative input 12 of the adder 10 and a further resistor R _{y is} provided in the connection to the output at the adder 10. At the output of the adder 10, depending on which of the overcurrent protection devices F1, F2, F3, F4 have been triggered as intended, the voltage U _ou t to be set is present.

FIG. 2 shows a device 30 according to the invention for triggering an overcurrent protection device F1, F2, F3, F4. The device 30 is designed as an emitter circuit with negative current feedback, namely by means of an NPN transistor and a PNP transistor, the base being denoted by B, the emitter by E and the collector by C in each case.

The base Bi of the PNP transistor is connected to the intermediate tap 31 of the voltage divider 33, formed from the two resistors R20, R30 Collector C _{2 of} the NPN transistor connected.

The base B _{2 of} the NPN transistor is connected to a microcontroller mq via the series resistor R _B , so that the base can be controlled by the microcontroller mq. The current flow into the base of the NPN transistor can be adjusted as desired via the series resistor R _B.

The base B2 is also connected to a signal connection (LOCK) which is connected to the locking circuit according to FIG. The purpose of this is to “hide” or “deactivate” the control signals as desired, so that the overcurrent protection devices F1, F2, F3, F4 that have not yet been triggered as intended are locked against improper triggering. The pull-down resistor R _Dp prevents uncontrolled switching on of the NPN transistor. A resistor R _{B is also} provided in front of the PNP transistor. This serves to limit the current flow through the PNP transistor and the voltage drop across the PNP transistor.

The flow of current into the NPN transistor causes it to become conductive, as a result of which a current flows through the two resistors R ₂₀ and R ₃₀ . With the appropriate dimensioning of these two resistors R ₂₀ and R30, the required current flow into the base Bi of the PNP transistor can be set accordingly. This now results in the current flow through fuse F 1, which must be dimensioned so that the fuse blows in the desired time. FIG. 3 shows an illustration of the time sequence of a triggering process of a fuse.

For this purpose, the voltage that drops across the fuse was recorded by measurement. The current flow generated by the transistor first causes an increase in potential at the fuse. The destruction process is in progress. After about 11 ms the fuse is completely destroyed and the entire applied voltage minus the saturation Voltage of the PNP transistor across the fuse.

FIG. 4 shows a circuit arrangement according to the invention for locking the circuit arrangement for triggering an overcurrent protection device according to FIG. 2. The circuit 40 is also an emitter circuit with current negative feedback. In this embodiment, the fuse F1 is used to keep the further NPN transistor in the blocked state. As soon as the fuse F1 has been triggered as intended or has blown, the base of the NPN transistor is pulled to a higher potential and this becomes conductive.

All control signals of the device 30 for triggering the fuses, except for the signal for locking, are conducted via the illustrated diodes D to the collector of this NPN transistor. This has the result that the respective affected devices 30 can no longer be activated. The "setting process" of the reference voltage is irrevocably ended after the locking fuse has blown.

FIG. 5 shows an exemplary representation of the time sequence for setting a desired voltage U _out

The reference voltage to be set (U _out = upper curve) is at a potential of approx. 1,100 mV before a fuse F1 is triggered. Now the first fuse F1 is blown first. After the first fuse F1 has been triggered, the reference voltage is at the voltage level of approx. 1300 mV. The second fuse F2 is then blown. The reference voltage U _out has now reached the desired voltage level of around 1600 mV. The lock is then activated to fix the status obtained.

The invention is not limited in its implementation to the above specified preferred embodiments. Rather, a number of variants are conceivable which make use of the solution shown even in the case of fundamentally different designs.

Claims

1. Analog circuit arrangement (1) for the variable setting of a voltage U _ou t within defined voltage limits, comprising a non-inverting adder (10) with a positive input

(11), with a voltage divider (20) of at least a first stage (21) and a second stage (22) being connected to the positive input (11) of the adder (10), at least one stage of a parallel connection of n resistors (R1, R2, ..., Rn), which are each connected in series in a line path (L1, L2, Ln) to an overcurrent protection device (F1, F2, Fn) and at least one device (30), in order to actively bring one or more of the overcurrent protection devices (F1, F2, Fn) into a state that interrupts the respective line path concerned (L1, L2, Ln).

2. Analog circuit arrangement (1) according to claim 1, characterized in that the overcurrent protection devices (F1, F2, Fn) are designed as fuses.

3. Analog circuit arrangement (1) according to claim 1 or 2, characterized in that the first stage of the voltage divider consists of a

Fixed resistance (R _f ) exists.

4. Analog circuit arrangement (1) according to one of the preceding claims, characterized in that the device (30) is implemented as an emitter circuit with current negative feedback by means of an NPN transistor (NPN) and a PNP transistor (PNP), its base (B1) via an intermediate tap (31) of a voltage divider (40) consisting of at least two resistors (R ₂ o, R30) with the collector gate (C2) of the NPN transistor is connected.

5. Analog circuit arrangement (1) according to claim 4, characterized in that the base (B2) of the NPN transistor (NPN) is controlled by a microcontroller (mq), preferably via a series resistor (R _B ).

6. Analog circuit arrangement according to one of the preceding claims 4 or 5, characterized in that the base (B2) on the one hand via a pull-down resistor RD _P to the emitter (E2) of the NPN transistor, which is an uncontrolled transistor To prevent the transistor from being switched on and the base (B2) is connected to a signal connection (LOCK), which in turn is connected to the locking circuit (40), which locks the state of one or more not yet disconnected installed overcurrent protective device (s) (F1, F2, ..., Fn).

7. Analog circuit arrangement (1) according to one of the preceding claims 4 or 6, characterized in that the collector (C1) of the PNP transistor of the device (30) with the respective overcurrent protective devices (F1, F2, .., Fn) connectable or connected in order to selectively bring the respectively connected overcurrent protection device (F1, F2, .., Fn) into a state which interrupts the relevant line path (L1, L2, ..., Ln).

8. Analog circuit arrangement according to one of the preceding claims, characterized in that a circuit (40) for deactivating the device (30) for locking that state of one or more not yet in the disconnecting state installed overcurrent protective device (s) (F1, F2, ..., Fn) is provided.

9. A method for the variable setting of a voltage U _out within de defined voltage limits with a circuit arrangement (1) according to one of claims 1 to 8, with the one or the following steps:

Selective energization of one or more of the overcurrent protection device (F1, F2, Fn) with an overcurrent generated with the device (30) in order to bring the respective line path (L1, L2, Ln) into the electrically separated state and thereby the span voltage of the voltage component at the input of the adder (10) as intended.

10. The method according to claim 8 and 9, characterized in that after the selective energization of one or more of the overcurrent protection devices (F1, F2, .., Fn) with an overcurrent, the respective

Device (30) is deactivated by means of the circuit (40).