EP3884522A1 - Multi-junction pico-avalanche detector - Google Patents

Multi-junction pico-avalanche detector

Info

Publication number
EP3884522A1
EP3884522A1 EP19802143.8A EP19802143A EP3884522A1 EP 3884522 A1 EP3884522 A1 EP 3884522A1 EP 19802143 A EP19802143 A EP 19802143A EP 3884522 A1 EP3884522 A1 EP 3884522A1
Authority
EP
European Patent Office
Prior art keywords
junction
layer
gain
photon detector
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19802143.8A
Other languages
German (de)
French (fr)
Other versions
EP3884522B1 (en
EP3884522C0 (en
Inventor
Giuseppe Iacobucci
Pierpaolo Valerio
Lorenzo Paolozzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universite de Geneve
Original Assignee
Universite de Geneve
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universite de Geneve filed Critical Universite de Geneve
Publication of EP3884522A1 publication Critical patent/EP3884522A1/en
Application granted granted Critical
Publication of EP3884522B1 publication Critical patent/EP3884522B1/en
Publication of EP3884522C0 publication Critical patent/EP3884522C0/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
    • H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02016—Circuit arrangements of general character for the devices
    • H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02027—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier for devices working in avalanche mode

Definitions

  • the present invention relates to photon detector and more particularly to a high sensitivity single photon detector.
  • Existing semiconductors sensors comprise silicon p-substrate devices, which are the most common ones and which are possible to integrate with conventional microelectronic processes.
  • the simplest silicon detectors comprise PIN diodes and are called pixel sensors.
  • This type of sensor is represented in figures 1A-1C. It comprises a P region 1 (bulk), P+ regions 2 and N+ regions 3 acting as pixels. As shown in Figure 1A, it is composed by an N-on-P diode matrix, but P-on-N or alternative solutions are also possible.
  • Figure 1 B shows that upon operation, the primary electrons e ⁇ produced in the depletion region (bulk) drift to the anode, whereas the holes h + drift to the cathode, thereby inducing a signal.
  • Figure 1 C shows a plot showing that the electric field is kept low while there is no multiplication mechanism in place in these sensors.
  • FIG. 2A to 2C describe conventional Avalanche Diode sensors comprising avalanche photo diodes (APD) 2, 3 instead of PIN diodes as above.
  • the APD is a diode with a higher doping at the junction interface (PIPN), in order to increase the electric field locally and generate impact ionization.
  • PIPN junction interface
  • FIG. 2B is represented an avalanche diode sensor upon operation (detection), in which thanks to the electron multiplying device which consists in the P+ region disposed on the N+ region, the electrons injected in the multiplication region start an avalanche, producing new electron/hole couples.
  • the main contribution to the charge signal is induced by the secondary holes, represented by the bold arrow h + .
  • FIGS 3A to 3C show another type of existing sensors for single photon detection comprising arrays of Single Photons Avalanche Diodes (SPADs), also called Silicon Photo Multipliers (SiPM).
  • SPADs Single Photons Avalanche Diodes
  • SiPM Silicon Photo Multipliers
  • FIG 3B shows the operating of a SPAD sensor. More particularly, in a SPAD, the detection of a single primary charge carrier happens via Geiger discharge (above breakdown voltage). The breakdown is interrupted by the voltage drop on a bias element, called quenching resistor. After a short dead-time the SPAD is operative again
  • DNCR Dark Noise Counting Rate
  • photons can be generated from the electron-hole recombination. These photons are responsible for the optical cross-talk of the SiPM.
  • the depletion region of a SPAD is very shallow. This means that, despite a very small pixel size, its capacitance is very high due to the small thickness of the gain layer.
  • the SPADs cannot integrate very low-noise electronics, which means that they are not able to discriminate the signal of a single photon if they are operated in proportional regime (gain ⁇ 1000).
  • the traditional approach is then to produce arrays of small pixels operated in Geiger regime (gain 10 6 -10 7 ), in which each pixel cannot distinguish the number of synchronous, primary incident photons.
  • the gain regions In Geiger regime, the gain regions must be independent for each pixel, in order to prevent the full sensor discharge. The separate gain regions generate critical field regions at the pixel borders, which may cause crosstalk, inefficiencies, loss of time resolution and early discharge.
  • the Geiger regime does not allow the operation of the sensor in presence of strong light sources, as natural light illumination, due to the dead time associated to the pixel discharge.
  • Figure 3C shows that the electric field in a SPAD is very high and limited to the junction region such that the gain of a SPAD is of the order of 10 6 .
  • LGAD Low-Gain Avalanche Diodes
  • APDs Avalanche Photo Diodes
  • These devices can operate with front-side illumination or back-side illumination.
  • the photoelectrons do not exploit the full gain layer, being injected from the side where the electron path is smaller.
  • the photoelectron drift in the substrate introduces time-jitter in the sensor response; the substrate thickness must therefore be minimized.
  • a primary object of the invention is to solve the above-mentioned problems and more particularly to provide a single photon detector having an improved detection signal amplification with very low noise.
  • Another object of the invention it to provide a single photon detector with no pixel dead time
  • a further object of the invention it to provide a single photon detector with uniform timing response with proper pixel design Summary of the invention
  • a first aspect of the invention is a multi-junction photon detector comprising a lightly p-doped or intrinsic silicon substrate presenting a drift region in the bulk, a plurality of N pixels on the top surface of the substrate, a P uniform doping implant on the backside of the substrate and at least one deep N implant layer on the backside, deeper in the substrate bulk than the P uniform doping implant, such that the detector presents a first PN junction in inverse polarization, corresponding to the interface between the N pixels and the drift region in the substrate, a second junction in direct polarization between the drift region and the deep N implant on the back side and a third PN junction in inverse polarization between the deep N implant and the substrate forming a gain region.
  • both the drift region and the deep N-gain implant are fully depleted, so that no current is injected through the corresponding forward-biased junction.
  • the third PN junction corresponds to a gain layer that covers uniformly the backside of the sensor active area.
  • the third PN junction is operated at a field high enough to generate impact ionization from the charge carriers.
  • a region between the backside contact of the sensor and the gain layer is an absorption layer which can be modulated in thickness.
  • the gain region comprises multiple fully depleted PN-junctions.
  • the senor is integrated with the electronics in a CMOS or a BiCMOS process.
  • the gain region is structured in impact layers and thermalisation layers thus increasing or decreasing the ratio between the electron and the hole multiplication gain in the multiplication region
  • the present invention further comprises electronegative elements favoring the capture or recombination of one type of carrier, i.e. the electrons or the holes, thus increasing or decreasing the ratio between the electron and the hole multiplication gain in the multiplication region.
  • the pixel matrix area is surrounded by a guard ring structure. In this manner, one gradually increases the top-surface potential from the low voltage inside the guard ring to the same negative high voltage applied to the backside of the chip.
  • a second aspect of the invention is a multi-junction photon detector manufacturing method comprising a first step comprising a growth of a P-doped epi layer on a very low resistivity P+ silicon wafer, a second step of growing Gain N-layer on the P-doped epi layer, or alternatively the N-layer growth is replaced by ion implantation, and the whole is annealed, a third step consists in growing a P-doped epi-layer on top of the previous one, acting as substrate for the subsequent CMOS processing, a fourth step consisting in carrying out a CMOS processing, and a fifth step comprising thinning the total object by removing a major part of the wafer such that the total PicoAD thickness is approx. 40 m ⁇ .
  • the present invention shows several advantages over the prior art sensors, among which:
  • the proposed sensor having the gain layer on the backside, immediately multiplies the photo-electron in the case of backside illumination, without producing time jitter.
  • the photoelectron in contrast with front side illuminated APD, traverses the full gain-layer.
  • the electrons produced by thermal agitation in the thick drift region do not drift through the gain layer, so the extra noise factor is very low compared with the LGAD structure.
  • the new proposed structure of the sensor of the present invention shows the following advantages. Thanks to the proportional operation of the pixel, the sensor provides an analogue in-pixel photon counting, a zero dark-noise counting rate, a stable working point with respect to temperature and voltage variations, no pixel dead time, a sensor operation with natural light illumination and no optical cross talk. Furthermore, thanks to the uniform gain layer, the sensor can provide close to 100% fill- factor while integrating the electronics in the sensor ASIC, no critical inter-pixel regions and a uniform timing response with proper pixel design.
  • the senor provides a low pixel capacitance (low electronics noise), a dominating electron gain and drift (faster response) and only the few primary charges produced by thermal agitation in the very thin gain layer are multiplied (low excess noise factor).
  • the principle of introducing separate junctions inside the substrate can be extended to a larger number of junctions: a multi-stage gain is possible with a NPNPNP... structure.
  • the advantage in this case could be a reduced non-uniformity of the gain due to process mismatch.
  • CMOS process can be extended to n- substrate process or to other semi-conductor technologies (such as GaAs, InGaAs, Diamond, etc.).
  • Lower bandgap technologies could allow operating at a lower voltage and with larger photo-detection efficiencies in the IR band compared to silicon technology.
  • the device originally designed for light, could be used with ionizing particles, granting exceptional time resolution compared with any existing pixel detector technology, thanks to the very small active area for the signal gain.
  • Figures 2A to 2C represent a conventional APD sensor, its functioning upon detection and an electrical field vs depth plot;
  • Figures 3A to 3C represent a conventional SPAD sensor, its functioning upon detection and an electrical field vs depth plot;
  • the figure 4A to 4C show a first aspect of the invention which is a section of a sensor according to the present invention, showing at the top N+ pixels interleaved by P-stops which are preferred but non fundamental, and a deep N-well that will host the electronics.
  • the PN gain junction is placed in the opposite side of the P-drift region with respect to the pixels.
  • the figure 4D shows the Electric field in the gain (left) and in the drift (right) regions.
  • the example is given in the case of two PN-gain junctions and one PN-drift junction.
  • the gain in the multi-junction pico-avalanche detector is in the range 10-1000 and the sensor is operated in linear avalanche region.
  • the figure 5 shows the manufacturing process of the sensor of the present invention.
  • the sensor of the present invention is illustrated in figures 4A and 4B.
  • the sensor structure which is not a diode, is composed by a lightly p-doped silicon substrate 1 , n+ pixels 2 on the top surface and p+ uniform 3 doping on the backside.
  • An additional n-doped, uniform layer 4 is present on the backside, deeper in the bulk than the p+ implant 3, in order to generate a gain region. Therefore, the doping structure of the sensor, from top to bottom, is NPNP. Between the pixel and the gain layer is provided a drift region 6.
  • the inter-pixel p+ implant 7 is optional.
  • the detector presents the n+ pixels 2 and p+ uniform doped region 3 as end terminals of the current such that upon detection the current signal generated goes through the drift region 1 and the additional n-doped, uniform layer 4.
  • the top surface can be fully processed with a microelectronic process such as bias components and electronic devices.
  • the bottom surface presents only uniform implantation or growth and metal depositions.
  • the pixels on the top surface, i.e. the n+ zones, are operated at low, positive voltage, while the backside p+ implant is referred to negative high-voltage.
  • the senor is meant to operate after fully depleting both the n+/p junctions between the pixels and the substrate and the n/p+ junction on the backside.
  • the space charge density of the n-doped region in the n/p+ junction is higher compared to the p-substrate, thus creating a very high electric field region on the backside (gain region) and a low-field region in the substrate (drift region).
  • the high field region, or gain region has sufficiently high electric field to generate electron avalanche-multiplication.
  • the full depletion of the p substrate grants the pixel- to-pixel insulation.
  • the sensor is illuminated from the backside, so that the conversion of primary photons injects electrons in the gain region.
  • the secondary electrons incur in avalanche multiplication, generating the secondary electron/hole pairs.
  • the secondary electrons drift for several microns in the drift region, generating the signal on the corresponding pixel by capacitive coupling, while the secondary holes drift back for few hundreds of nanometers, their path being so short that almost no signal is induced.
  • a thicker absorption region can be placed between the gain region and the backside p+ contact, just by increasing the thickness of the p-doped layer forming the gain junction
  • the signal induced on the pixels is amplified and processed by means of the electronics, which can be integrated in the top surface of the sensor.
  • the gain junction is meant to operate in proportional regime, in contrast with the conventional single-photon avalanche diodes which require to operate in Geiger regime in order to discriminate the single photon signal.
  • the senor is integrated with the electronics in a CMOS or a BiCMOS process and optimized for single photons detection
  • the PNPN (or in general multi-junction) structure grants the sensor with stable operation as the diode, but in addition allows engineering the gain and drift regions.
  • the Multi-Junction Pico-Avalanche Detector (MJAD or PicoAD) of the present invention is a silicon sensor with a pixelated, fully depleted
  • the first inversely polarized PN junction constitutes the drift and signal induction region, with the N-pixels on a P-substrate (in alternative: P-pixels on N-substrate, P- pixels on P substrate, N-pixels on N substrate) operated at a field of approximately 2 V/pm to saturate the electron drift velocity and minimize the amplified signal rise time, thus minimizing the electronics contribution to time resolution (in general, the electric field in the drift region is low enough in order to avoid the generation of an avalanche effect).
  • the other inversely polarized PN junction corresponds to the gain layer that covers uniformly (or with reasonable variations in order to generate uniform gain in the layer itself) the backside of the sensor active area inside a guard ring and is operated at a field high enough to generate impact ionization from the charge carriers.
  • the region between the backside contact of the sensor and the gain layer is the absorption layer and it can be modulated in thickness.
  • the gain layer is operated below the breakdown voltage and the sensor is not meant to be used in Geiger regime. Profiting of the low-noise of the electronics offered by the low-capacitance design, the sensor can have sufficient sensitivity to detect single photons while operating in proportional regime.
  • the depletion of the gain layer goes downwards from the N-gain to the bottom P+ contact.
  • the direct junction between the N-gain and the P-drift substrate transfers the high voltage to the substrate itself, starting the normal depletion of the sensor, which goes downwards from the pixels (the depletion can start from the top junction and then move to the bottom one, but the final result is the same).
  • This second depletion ensures the proper insulation of the pixels, as for a traditional N-on-P detector.
  • the full depletion is achieved when the two depletion layers are in contact.
  • the top and the bottom reverse-biased junctions will prevent the current injection from the terminals in the device.
  • Further increase of the high voltage allows setting of the gain of the multiplication region.
  • the electric field is as uniform as possible for a given depth of the sensor active area. In order to improve the uniformity, the pixels are wider than the sensor thickness and the inter-pixel spacing is minimized.
  • the drift region is also deep in comparison to the inter-pixel spacing to minimize the local variations of the electric field.
  • the gain implantations which are typically uniform under the pixel area, can be adjusted in the inter-pixel region to increase the uniformity of the gain region.
  • the active area i.e. the area where the pixel matrix is located
  • the active area is surrounded by a guard ring structure, which gradually increases the top-surface potential from the low voltage inside the guard ring to the same negative high voltage applied to the backside of the chip.
  • a positive high voltage can be applied to the pixel.
  • the N implantations of the gain layer do not extend far outside the area underneath the guard ring, in order to avoid charge injection from the chip edge.
  • the senor is integrated in a CMOS process as shown in figure 5.
  • the sensor is integrated in a SiGe BiCMOS process and the signal amplification is made by using SiGe HBT transistors.
  • the electronics is placed inside deep N- wells (These N-wells can be independent or they can be the same implants used for the pixel formation) in order to insulate it form the high-voltage.
  • Each pixel has its own amplifier and, in the preferred configuration, the coincidence between different pixels is done at digital level by counting the number of pixels firing at the same time. This approach allows to maintain a small capacitance at the input of the amplifier, thus extending the sensitivity to smaller input signals.
  • the integration with a CMOS processing would also allow a real-time control of the potential on the single pixels in order to compensate gain variations along the detector surface. This, together with the uniform electric field configuration, would allow for a higher average gain achievable in the sensor.
  • the gain region is made of several PN junctions in series in a multi-step configuration. This allows to control the electric field more precisely (figure 2, an example with two PN junctions in the gain region).
  • the gain junctions can be structured in a way that the electric field is very intense in very thin layers (impact layers), with regions with a lower field in between (thermalisation layers). This will allow to exploit the non-local impact gain multiplication mechanisms, which could be used to increase the maximum internal gain while keeping a low the excess noise of the sensor.
  • hetero-structures in the multi-step gain region allows further increase of the maximum achievable gain at low noise.
  • the main candidate materials are Silicon-Germanium for the impact layers and Silicon-Carbide for the thermalisation layers.
  • the PicoAD can be implemented in different semiconductor materials, as GaAs, InP, Ge, and the like
  • the present invention also refers to a sensor fabrication method which is shown in Figure 6 which shows the five steps of the procedure to manufacture the PicoAD.
  • a first step comprises a growth of approx. 1 pm of a P -doped epi layer on a very low resistivity wafer.
  • a second step one implant a Gain N-layer and the whole is annealed.
  • the third step consists in growing a wider P-doped epi-layer (for example 19 miti).
  • step 4 a CMOS processing is carried out (approx. 18 miti).
  • step 5 comprises thinning the total object by excising the major part of the wafer such that the total PicoAD is approx. 40 mhi.
  • the PicoAD can be used for detection of ionizing radiation, X-Rays, p-Rays and light in the spectrum ranging from the Infra-Red to the Ultra-Violet.
  • the PicoAD structure is preferably optimized for timing measurement with photons, for high-sensitivity and possibility of high gain.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The present relates to a multi-junction photon detector comprising a semiconductor substrate, a plurality of n+ pixels on the top surface and a p+ uniform doping implant on the backside and at least one n-doped layer on the backside, deeper in the substrate bulk than the p+ implant, such that the detector presents a first PN junction corresponding to a drift and signal induction region and comprising the pixels on the substrate, and a second PN junction corresponding to a gain region and comprising the n-doped layer disposed on the backside of the detector active area deeper in the substrate bulk. These two junctions are operated in inverse polarization. The area between them contains a PN junction in direct polarization and it is fully depleted from the free charges.

Description

MULTI-JUNCTION PICO-AVALANCHE DETECTOR
Technical Field
The present invention relates to photon detector and more particularly to a high sensitivity single photon detector.
Background of the art
Existing semiconductors sensors comprise silicon p-substrate devices, which are the most common ones and which are possible to integrate with conventional microelectronic processes. The simplest silicon detectors comprise PIN diodes and are called pixel sensors.
This type of sensor is represented in figures 1A-1C. It comprises a P region 1 (bulk), P+ regions 2 and N+ regions 3 acting as pixels. As shown in Figure 1A, it is composed by an N-on-P diode matrix, but P-on-N or alternative solutions are also possible.
With this type of sensors, the bulk 1 of the sensor is depleted upon operation (detection). Figure 1 B shows that upon operation, the primary electrons e~ produced in the depletion region (bulk) drift to the anode, whereas the holes h+ drift to the cathode, thereby inducing a signal.
In these sensors, the pixel size is small and the depletion layer is wide, thus reducing the pixel capacitance and the electronic noise. Figure 1 C shows a plot showing that the electric field is kept low while there is no multiplication mechanism in place in these sensors.
Figure 2A to 2C describe conventional Avalanche Diode sensors comprising avalanche photo diodes (APD) 2, 3 instead of PIN diodes as above. The APD is a diode with a higher doping at the junction interface (PIPN), in order to increase the electric field locally and generate impact ionization.
The area between two pixels has no gain and is therefore considered inefficient. For this reason in an APD matrix the pixel size is typically large, limiting the space resolution and the performance of the front-end electronics, or the fill-factor is low, limiting the efficiency. In Figure 2B is represented an avalanche diode sensor upon operation (detection), in which thanks to the electron multiplying device which consists in the P+ region disposed on the N+ region, the electrons injected in the multiplication region start an avalanche, producing new electron/hole couples. The main contribution to the charge signal is induced by the secondary holes, represented by the bold arrow h+.
These secondary electrons are collected by the anode while the secondary holes drift back to the cathode. With this kind of sensor, the illumination can be from the top or from the Bottom. However, in the latter case the time resolution is worse. Also, all the electrons produced in the bulk generate avalanche multiplication, which leads to an excess noise of the device, limiting the performance of the Front-End electronics. Finally, as shown in figure 2C, with this sensor, in order to maintain a low sensor gain, the electric field must not exceed the breakdown voltage. The typical gain of an APD is in the range 10 to 1000.
Figures 3A to 3C show another type of existing sensors for single photon detection comprising arrays of Single Photons Avalanche Diodes (SPADs), also called Silicon Photo Multipliers (SiPM).
The SPAD is structurally similar to an APD where the depletion region is very thin, in order to minimize the probability of injection of a carrier produced by thermal generation. For this reason the SPAD is most sensitive to non-penetrating radiation Figure 3B shows the operating of a SPAD sensor. More particularly, in a SPAD, the detection of a single primary charge carrier happens via Geiger discharge (above breakdown voltage). The breakdown is interrupted by the voltage drop on a bias element, called quenching resistor. After a short dead-time the SPAD is operative again
The insulation between two SPADs is fundamental to minimize cross-talk and the risk of excess spurious counts
All the electron/hole couples generated in the depletion region by thermal generation start a spurious count. The frequency of these counts is called Dark Noise Counting Rate (DNCR).
During the breakdown, photons can be generated from the electron-hole recombination. These photons are responsible for the optical cross-talk of the SiPM.
In order to minimize the DNCR, the depletion region of a SPAD is very shallow. This means that, despite a very small pixel size, its capacitance is very high due to the small thickness of the gain layer. Operating on large capacitance, the SPADs cannot integrate very low-noise electronics, which means that they are not able to discriminate the signal of a single photon if they are operated in proportional regime (gain <1000). The traditional approach is then to produce arrays of small pixels operated in Geiger regime (gain 106-107), in which each pixel cannot distinguish the number of synchronous, primary incident photons. In Geiger regime, the gain regions must be independent for each pixel, in order to prevent the full sensor discharge. The separate gain regions generate critical field regions at the pixel borders, which may cause crosstalk, inefficiencies, loss of time resolution and early discharge.
Moreover, when integrating the electronics in the sensor surface, it will reduce the active gain area, thus reducing the active area (fill-factor) of the sensor. Finally, the Geiger regime does not allow the operation of the sensor in presence of strong light sources, as natural light illumination, due to the dead time associated to the pixel discharge.
An example of a conventional detector working in Geiger regime is made in US 9728667 which shows a detector using a Geiger photodiode and a single P-N junction and presenting the drawbacks recited above.
Figure 3C shows that the electric field in a SPAD is very high and limited to the junction region such that the gain of a SPAD is of the order of 106.
Devices which operate in proportional regime and have a drift region, such as the Low-Gain Avalanche Diodes (LGAD) or some Avalanche Photo Diodes (APDs), integrate a gain Implant under the pixel, in the top surface of the device (similarly to what is done for the SPAD). These devices can operate with front-side illumination or back-side illumination. In the first case, the photoelectrons do not exploit the full gain layer, being injected from the side where the electron path is smaller. In the second case, the photoelectron drift in the substrate introduces time-jitter in the sensor response; the substrate thickness must therefore be minimized.
In this regard, a primary object of the invention is to solve the above-mentioned problems and more particularly to provide a single photon detector having an improved detection signal amplification with very low noise.
Another object of the invention it to provide a single photon detector with no pixel dead time
A further object of the invention it to provide a single photon detector with uniform timing response with proper pixel design Summary of the invention
The above problems are solved by the present invention which will be called PicoAD.
A first aspect of the invention is a multi-junction photon detector comprising a lightly p-doped or intrinsic silicon substrate presenting a drift region in the bulk, a plurality of N pixels on the top surface of the substrate, a P uniform doping implant on the backside of the substrate and at least one deep N implant layer on the backside, deeper in the substrate bulk than the P uniform doping implant, such that the detector presents a first PN junction in inverse polarization, corresponding to the interface between the N pixels and the drift region in the substrate, a second junction in direct polarization between the drift region and the deep N implant on the back side and a third PN junction in inverse polarization between the deep N implant and the substrate forming a gain region.
Preferably both the drift region and the deep N-gain implant are fully depleted, so that no current is injected through the corresponding forward-biased junction.
Advantageously, the third PN junction corresponds to a gain layer that covers uniformly the backside of the sensor active area.
Preferably, the third PN junction is operated at a field high enough to generate impact ionization from the charge carriers. Advantageously, a region between the backside contact of the sensor and the gain layer is an absorption layer which can be modulated in thickness.
Preferably, the gain region comprises multiple fully depleted PN-junctions.
Preferably, the sensor is integrated with the electronics in a CMOS or a BiCMOS process. Advantageously, the gain region is structured in impact layers and thermalisation layers thus increasing or decreasing the ratio between the electron and the hole multiplication gain in the multiplication region
According to a preferred embodiment of the present invention, it further comprises electronegative elements favoring the capture or recombination of one type of carrier, i.e. the electrons or the holes, thus increasing or decreasing the ratio between the electron and the hole multiplication gain in the multiplication region. Preferably, the pixel matrix area is surrounded by a guard ring structure. In this manner, one gradually increases the top-surface potential from the low voltage inside the guard ring to the same negative high voltage applied to the backside of the chip.
A second aspect of the invention is a multi-junction photon detector manufacturing method comprising a first step comprising a growth of a P-doped epi layer on a very low resistivity P+ silicon wafer, a second step of growing Gain N-layer on the P-doped epi layer, or alternatively the N-layer growth is replaced by ion implantation, and the whole is annealed, a third step consists in growing a P-doped epi-layer on top of the previous one, acting as substrate for the subsequent CMOS processing, a fourth step consisting in carrying out a CMOS processing, and a fifth step comprising thinning the total object by removing a major part of the wafer such that the total PicoAD thickness is approx. 40 mΐΎΐ.
Thanks to the above features, the present invention shows several advantages over the prior art sensors, among which:
1 ) It allows for the construction of small pixels with small capacitance, which result in small Equivalent Noise Charge and low values of the threshold on the integrated charge.
2) It provides a sensor with uniformity of response and very large efficiency also in the inter-pixel regions.
3) Only the electrons generated in the absorption layer on the backside of the sensor are multiplied. On the contrary, only the holes from electron-hole pairs produced in the drift region of the sensor are injected into the gain region. Since the gain for these carriers is low, a large enhancement of the prompt electron-component of the signal is produced and therefore providing an excellent timing performance.
4) It produces signal waveforms with onset in the region where the weighting field, which determines the signal induction on the pixels, is most uniform.
5) It is compatible with CMOS structures, thus allowing for a monolithic implementation.
All the limitations of the SiPM are removed in the sensor of the present invention since the proportional gain layer on the backside can be uniform and common for the whole sensor region, while the top surface can be fully processed without any loss of sensor fill factor.
The proposed sensor, having the gain layer on the backside, immediately multiplies the photo-electron in the case of backside illumination, without producing time jitter. The photoelectron, in contrast with front side illuminated APD, traverses the full gain-layer. Finally, the electrons produced by thermal agitation in the thick drift region do not drift through the gain layer, so the extra noise factor is very low compared with the LGAD structure.
To summarize, the new proposed structure of the sensor of the present invention shows the following advantages. Thanks to the proportional operation of the pixel, the sensor provides an analogue in-pixel photon counting, a zero dark-noise counting rate, a stable working point with respect to temperature and voltage variations, no pixel dead time, a sensor operation with natural light illumination and no optical cross talk. Furthermore, thanks to the uniform gain layer, the sensor can provide close to 100% fill- factor while integrating the electronics in the sensor ASIC, no critical inter-pixel regions and a uniform timing response with proper pixel design. Finally, thanks to the separate drift region and the PNPN structure, the sensor provides a low pixel capacitance (low electronics noise), a dominating electron gain and drift (faster response) and only the few primary charges produced by thermal agitation in the very thin gain layer are multiplied (low excess noise factor).
Also, the principle of introducing separate junctions inside the substrate can be extended to a larger number of junctions: a multi-stage gain is possible with a NPNPNP... structure. The advantage in this case could be a reduced non-uniformity of the gain due to process mismatch.
The concept, described for p-substrate CMOS process, can be extended to n- substrate process or to other semi-conductor technologies (such as GaAs, InGaAs, Diamond, etc.). Lower bandgap technologies could allow operating at a lower voltage and with larger photo-detection efficiencies in the IR band compared to silicon technology.
Despite the possibility to integrate the electronics is a big advantage of this invention, it is not strictly required and the innovation of the NPNP sensor structure (not diode) would still hold.
The device, originally designed for light, could be used with ionizing particles, granting exceptional time resolution compared with any existing pixel detector technology, thanks to the very small active area for the signal gain.
Brief description of the drawings
Further particular advantages and features of the invention will become more apparent from the following non-limitative description of at least one embodiment of the invention which will refer to the accompanying drawings, wherein Figures 1A to 1 C represent a conventional PIN sensor, its functioning upon detection and an electrical field vs depth plot;
Figures 2A to 2C represent a conventional APD sensor, its functioning upon detection and an electrical field vs depth plot;
Figures 3A to 3C represent a conventional SPAD sensor, its functioning upon detection and an electrical field vs depth plot;
The figure 4A to 4C show a first aspect of the invention which is a section of a sensor according to the present invention, showing at the top N+ pixels interleaved by P-stops which are preferred but non fundamental, and a deep N-well that will host the electronics. The PN gain junction is placed in the opposite side of the P-drift region with respect to the pixels.
The figure 4D shows the Electric field in the gain (left) and in the drift (right) regions. The example is given in the case of two PN-gain junctions and one PN-drift junction. The gain in the multi-junction pico-avalanche detector is in the range 10-1000 and the sensor is operated in linear avalanche region.
The figure 5 shows the manufacturing process of the sensor of the present invention.
Detailed description of the invention
The present detailed description is intended to illustrate the invention in a non- limitative manner since any feature of an embodiment may be combined with any other feature of a different embodiment in an advantageous manner.
The sensor of the present invention is illustrated in figures 4A and 4B.
The sensor structure, which is not a diode, is composed by a lightly p-doped silicon substrate 1 , n+ pixels 2 on the top surface and p+ uniform 3 doping on the backside. An additional n-doped, uniform layer 4 is present on the backside, deeper in the bulk than the p+ implant 3, in order to generate a gain region. Therefore, the doping structure of the sensor, from top to bottom, is NPNP. Between the pixel and the gain layer is provided a drift region 6. The inter-pixel p+ implant 7 is optional.
With this structure, the detector presents the n+ pixels 2 and p+ uniform doped region 3 as end terminals of the current such that upon detection the current signal generated goes through the drift region 1 and the additional n-doped, uniform layer 4. The top surface can be fully processed with a microelectronic process such as bias components and electronic devices. The bottom surface presents only uniform implantation or growth and metal depositions. The pixels on the top surface, i.e. the n+ zones, are operated at low, positive voltage, while the backside p+ implant is referred to negative high-voltage.
As shown in figure 4C, the sensor is meant to operate after fully depleting both the n+/p junctions between the pixels and the substrate and the n/p+ junction on the backside. Once depleted, the space charge density of the n-doped region in the n/p+ junction is higher compared to the p-substrate, thus creating a very high electric field region on the backside (gain region) and a low-field region in the substrate (drift region). The high field region, or gain region, has sufficiently high electric field to generate electron avalanche-multiplication. The full depletion of the p substrate grants the pixel- to-pixel insulation. The sensor is illuminated from the backside, so that the conversion of primary photons injects electrons in the gain region. These electrons incur in avalanche multiplication, generating the secondary electron/hole pairs. The secondary electrons drift for several microns in the drift region, generating the signal on the corresponding pixel by capacitive coupling, while the secondary holes drift back for few hundreds of nanometers, their path being so short that almost no signal is induced. In the case of illumination with longer wavelength light, a thicker absorption region can be placed between the gain region and the backside p+ contact, just by increasing the thickness of the p-doped layer forming the gain junction The signal induced on the pixels is amplified and processed by means of the electronics, which can be integrated in the top surface of the sensor. The gain junction is meant to operate in proportional regime, in contrast with the conventional single-photon avalanche diodes which require to operate in Geiger regime in order to discriminate the single photon signal.
Preferably, the sensor is integrated with the electronics in a CMOS or a BiCMOS process and optimized for single photons detection
The PNPN (or in general multi-junction) structure grants the sensor with stable operation as the diode, but in addition allows engineering the gain and drift regions.
In other words, the Multi-Junction Pico-Avalanche Detector (MJAD or PicoAD) of the present invention is a silicon sensor with a pixelated, fully depleted
(PN)DRIFT(PN )GAIN structure.
The first inversely polarized PN junction constitutes the drift and signal induction region, with the N-pixels on a P-substrate (in alternative: P-pixels on N-substrate, P- pixels on P substrate, N-pixels on N substrate) operated at a field of approximately 2 V/pm to saturate the electron drift velocity and minimize the amplified signal rise time, thus minimizing the electronics contribution to time resolution (in general, the electric field in the drift region is low enough in order to avoid the generation of an avalanche effect).
The other inversely polarized PN junction corresponds to the gain layer that covers uniformly (or with reasonable variations in order to generate uniform gain in the layer itself) the backside of the sensor active area inside a guard ring and is operated at a field high enough to generate impact ionization from the charge carriers. The region between the backside contact of the sensor and the gain layer is the absorption layer and it can be modulated in thickness.
The gain layer is operated below the breakdown voltage and the sensor is not meant to be used in Geiger regime. Profiting of the low-noise of the electronics offered by the low-capacitance design, the sensor can have sufficient sensitivity to detect single photons while operating in proportional regime.
When a negative high voltage is applied to the backside of the sensor, while keeping the pixels at positive low voltage, the depletion of the gain layer goes downwards from the N-gain to the bottom P+ contact. Once the gain layer is depleted, the direct junction between the N-gain and the P-drift substrate transfers the high voltage to the substrate itself, starting the normal depletion of the sensor, which goes downwards from the pixels (the depletion can start from the top junction and then move to the bottom one, but the final result is the same).
This second depletion ensures the proper insulation of the pixels, as for a traditional N-on-P detector. The full depletion is achieved when the two depletion layers are in contact. At this point, the top and the bottom reverse-biased junctions will prevent the current injection from the terminals in the device. Further increase of the high voltage allows setting of the gain of the multiplication region. The electric field is as uniform as possible for a given depth of the sensor active area. In order to improve the uniformity, the pixels are wider than the sensor thickness and the inter-pixel spacing is minimized. The drift region is also deep in comparison to the inter-pixel spacing to minimize the local variations of the electric field. The gain implantations, which are typically uniform under the pixel area, can be adjusted in the inter-pixel region to increase the uniformity of the gain region.
The active area (i.e. the area where the pixel matrix is located) is surrounded by a guard ring structure, which gradually increases the top-surface potential from the low voltage inside the guard ring to the same negative high voltage applied to the backside of the chip. In alternative, a positive high voltage can be applied to the pixel. The N implantations of the gain layer do not extend far outside the area underneath the guard ring, in order to avoid charge injection from the chip edge.
In its preferable implementation, the sensor is integrated in a CMOS process as shown in figure 5. In a more preferable implementation, the sensor is integrated in a SiGe BiCMOS process and the signal amplification is made by using SiGe HBT transistors. In the N-on-P pixel configuration, the electronics is placed inside deep N- wells (These N-wells can be independent or they can be the same implants used for the pixel formation) in order to insulate it form the high-voltage. Each pixel has its own amplifier and, in the preferred configuration, the coincidence between different pixels is done at digital level by counting the number of pixels firing at the same time. This approach allows to maintain a small capacitance at the input of the amplifier, thus extending the sensitivity to smaller input signals. The integration with a CMOS processing would also allow a real-time control of the potential on the single pixels in order to compensate gain variations along the detector surface. This, together with the uniform electric field configuration, would allow for a higher average gain achievable in the sensor.
In a more general configuration, the gain region is made of several PN junctions in series in a multi-step configuration. This allows to control the electric field more precisely (figure 2, an example with two PN junctions in the gain region). The gain junctions can be structured in a way that the electric field is very intense in very thin layers (impact layers), with regions with a lower field in between (thermalisation layers). This will allow to exploit the non-local impact gain multiplication mechanisms, which could be used to increase the maximum internal gain while keeping a low the excess noise of the sensor.
The possibility to use hetero-structures in the multi-step gain region, either for the impact layers or for the for the themalisation layers, allows further increase of the maximum achievable gain at low noise. In particular, for a silicon substrate the main candidate materials are Silicon-Germanium for the impact layers and Silicon-Carbide for the thermalisation layers.
The PicoAD can be implemented in different semiconductor materials, as GaAs, InP, Ge, and the like
The present invention also refers to a sensor fabrication method which is shown in Figure 6 which shows the five steps of the procedure to manufacture the PicoAD. According to the manufacturing method of the present invention, a first step comprises a growth of approx. 1 pm of a P -doped epi layer on a very low resistivity wafer. Then, in a second step one implant a Gain N-layer and the whole is annealed. The third step consists in growing a wider P-doped epi-layer (for example 19 miti). Then in step 4, a CMOS processing is carried out (approx. 18 miti). Finally, step 5 comprises thinning the total object by excising the major part of the wafer such that the total PicoAD is approx. 40 mhi. Through this fabrication process, one can vary the thickness of the different layers. By varying the thickness of the absorption layer and the material, the PicoAD can be used for detection of ionizing radiation, X-Rays, p-Rays and light in the spectrum ranging from the Infra-Red to the Ultra-Violet. The PicoAD structure is preferably optimized for timing measurement with photons, for high-sensitivity and possibility of high gain.
While the embodiments have been described in conjunction with a number of embodiments, it is evident that many alternatives, modifications and variations would be or are apparent to those of ordinary skill in the applicable arts. Accordingly, this disclosure is intended to embrace all such alternatives, modifications, equivalents and variations that are within the scope of this disclosure. This for example particularly the case regarding the different apparatuses which can be used.

Claims

1. Multi-junction photon detector comprising a silicon substrate presenting a drift region in the bulk (1 ), a plurality of pixels (2) on the top surface of the silicon substrate, a uniform doping implant (3) on the backside surface of the substrate and at least one deep implant layer (4) on the backside, deeper in the substrate bulk than the uniform doping implant, such that the detector presents a first junction in inverse polarization, corresponding to the interface between the pixels (2) and the drift region in the substrate (1 ), and a second PN junction in inverse polarization between the deep implant layer (4) and the uniform doping implant (3) on the backside surface forming a gain region, wherein both the plurality of pixels (2) and the uniform doping implant (3) function as end terminals, with the drift region (1 ) and the deep implant layer (4) interposed in between, so as to be able to direct a current signal between them through the drift region (1 ) and the deep implant layer (4).
2. Multi-junction photon detector according to claim 1 , characterized in that the first junction is a PN junction in inverse polarization where the silicon substrate is a lightly p- doped or intrinsic silicon substrate and the pixels are n-doped.
3. Multi-junction photon detector according to claim 1 or 2, characterized in that the second junction is a PN junction in inverse polarization formed between a deep n-doped layer (4) and a uniform p+ doped region (3) in the backside surface of the substrate.
4. Multi-junction photon detector according to any one of claims 1 to 3, characterized in that it comprises a third junction in direct polarization between the drift region and the deep n-doped implant layer on the back side.
5. Multi-junction photon detector according to any one of claims 1 to 4, characterized in that the second PN junction in inverse polarization corresponds to a gain layer that covers uniformly the backside of the sensor active area.
6. Multi-junction photon detector according to any one of claims 1 to 5, characterized in that the second PN junction in inverse polarization is operated at a field high enough to generate impact ionization from the charge carriers.
7. Multi-junction photon detector according to any one of claims 1 to 6, characterized in that a region between the backside contact of the sensor and the gain layer is a photon absorption layer which can be modulated in thickness.
8. Multi-junction photon detector according to any one of claims 1 to 7, characterized in that it comprises multiple PN-junctions in the gain region.
9. Multi-junction photon detector according to any one of claims 1 to 8, characterized in that the pixel matrix is surrounded by a guard ring structure.
10. Multi-junction photon detector according to any one of claims 1 to 9, characterized in that it is integrated with the electronics in a CMOS or a BiCMOS process.
11 Multi-junction photon detector according to any one of claims 1 to 10, characterized in that it is integrated with the electronics in a SiGe BiCMOS process.
12. Multi-junction photon detector according to any one of claims 1 to 11 , characterized in that the gain region is structured in impact layers and thermalisation layers.
13. Multi-junction photon detector according to any one of claims 1 to 12, characterized in that it further comprises electronegative elements favoring the capture or recombination of the electrons or the holes.
14. Multi-junction photon detector manufacturing method comprising: a first step comprising a growth of a P-doped epi layer on a very low resistivity P+ silicon wafer, a second step of growing or implantation of Gain N-layer on the P-doped epi layer and the whole is annealed, a third step consists in growing a P-doped or intrinsic epi-layer on top of the previous one, a fourth step consisting in carrying out a CMOS or BiCMOS processing, and a fifth step comprising thinning the total object by removing a major part of the wafer.
EP19802143.8A 2018-11-19 2019-11-08 Multi-junction pico-avalanche detector Active EP3884522B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP18207008.6A EP3654376A1 (en) 2018-11-19 2018-11-19 Multi-junction pico-avalanche detector
PCT/EP2019/080735 WO2020104220A1 (en) 2018-11-19 2019-11-08 Multi-junction pico-avalanche detector

Publications (3)

Publication Number Publication Date
EP3884522A1 true EP3884522A1 (en) 2021-09-29
EP3884522B1 EP3884522B1 (en) 2023-07-12
EP3884522C0 EP3884522C0 (en) 2023-07-12

Family

ID=64362419

Family Applications (2)

Application Number Title Priority Date Filing Date
EP18207008.6A Withdrawn EP3654376A1 (en) 2018-11-19 2018-11-19 Multi-junction pico-avalanche detector
EP19802143.8A Active EP3884522B1 (en) 2018-11-19 2019-11-08 Multi-junction pico-avalanche detector

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP18207008.6A Withdrawn EP3654376A1 (en) 2018-11-19 2018-11-19 Multi-junction pico-avalanche detector

Country Status (3)

Country Link
US (1) US11817518B2 (en)
EP (2) EP3654376A1 (en)
WO (1) WO2020104220A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023500636A (en) 2019-10-31 2023-01-10 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア Deep junction low gain electron avalanche detector
CN113921646B (en) * 2021-09-30 2023-03-31 厦门市三安集成电路有限公司 Single-photon detector, manufacturing method thereof and single-photon detector array
JP2024031352A (en) * 2022-08-26 2024-03-07 株式会社東芝 Photodetectors, photodetection systems, lidar devices and moving objects

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009103048A1 (en) * 2008-02-14 2009-08-20 Quantum Semiconductor Llc Dual photo-diode cmos pixels
IT1393781B1 (en) * 2009-04-23 2012-05-08 St Microelectronics Rousset OPERATING PHOTODIODO IN GEIGER MODE WITH INTEGRATED AND CONTROLLABLE JFET EFFECT SUPPRESSION RESISTOR, PHOTODIUM RING AND ITS PROCESS OF PROCESSING
US9728667B1 (en) * 2011-10-21 2017-08-08 Radiation Monitoring Devices, Inc. Solid state photomultiplier using buried P-N junction
IT201800007231A1 (en) * 2018-07-16 2020-01-16 AVALANCHE PHOTODIODE OPERATING IN GEIGER MODE WITH LOW NOISE AND RELATED MANUFACTURING PROCESS

Also Published As

Publication number Publication date
WO2020104220A1 (en) 2020-05-28
EP3654376A1 (en) 2020-05-20
EP3884522B1 (en) 2023-07-12
US11817518B2 (en) 2023-11-14
US20210280734A1 (en) 2021-09-09
EP3884522C0 (en) 2023-07-12

Similar Documents

Publication Publication Date Title
US10217889B2 (en) Clamped avalanche photodiode
US9257589B2 (en) Single photon avalanche diode with second semiconductor layer burried in epitaxial layer
US10283664B2 (en) Avalanche diode including vertical PN junction
US8441032B2 (en) Low-level signal detection by semiconductor avalanche amplification
US8258594B2 (en) Avalanche photodiode
US8766164B2 (en) Geiger-mode photodiode with integrated and adjustable quenching resistor and surrounding biasing conductor
US8093624B1 (en) High fill-factor avalanche photodiode
US11888003B2 (en) Photodetector
US11817518B2 (en) Multi-junction pico-avalanche detector
JP2017005276A (en) Single-photon avalanche diode
CN111684610B (en) Single photon avalanche diode and method for operating a single photon avalanche diode
CN107895743B (en) Apparatus and method for single photon avalanche photodiode detector
US20180158849A1 (en) Photodiode device and method of manufacture
US11335823B2 (en) Silicon carbide ultraviolet light photodetector
US10748951B2 (en) Near ultraviolet photocell
CN117239000A (en) Avalanche photodiode, manufacturing method thereof and single photon detector
US10290760B2 (en) Process of manufacturing an avalanche diode
US5583352A (en) Low-noise, reach-through, avalanche photodiodes
JPH09148618A (en) Silicon avalanche photodiode
US20200328314A1 (en) Photodiode with sensitivity control using a further depletion region
WO2010080048A1 (en) Semiconductor geiger mode microcell photodiode (variants)
RU83361U1 (en) SEMICONDUCTOR MICRO-CELLED GEIGERIAN PHOTODIOD (OPTIONS)

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20210608

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20230323

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602019032704

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

U01 Request for unitary effect filed

Effective date: 20230811

U07 Unitary effect registered

Designated state(s): AT BE BG DE DK EE FI FR IT LT LU LV MT NL PT SE SI

Effective date: 20230818

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

U20 Renewal fee paid [unitary effect]

Year of fee payment: 5

Effective date: 20231123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231013

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20231123

Year of fee payment: 5

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231112

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231012

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231112

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231013

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 20231201

Year of fee payment: 5

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712