EP3884490A1 - Method and device for operating a memory assembly - Google Patents
Method and device for operating a memory assemblyInfo
- Publication number
- EP3884490A1 EP3884490A1 EP19782986.4A EP19782986A EP3884490A1 EP 3884490 A1 EP3884490 A1 EP 3884490A1 EP 19782986 A EP19782986 A EP 19782986A EP 3884490 A1 EP3884490 A1 EP 3884490A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- physical address
- memory
- modified
- address
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7204—Capacity control, e.g. partitioning, end-of-life degradation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
Definitions
- the present disclosure relates to a method and an apparatus for operating a memory device.
- Some computing systems include a memory arrangement for storing and providing data for executing a program in real time.
- the storage arrangement can comprise an arrangement of storage segments, each of which can store and provide an information unit.
- a respective physical address can be assigned to each of the memory segments in order to enable a unique assignment.
- the life of a memory array may be affected by a total number of write and read operations performed.
- the lifespan of a memory arrangement can be shortened due to aging effects.
- the memory segments of a memory arrangement can often not be repaired or exchanged in isolation, so that the occurrence of a defect in one of the memory segments can already lead to the failure of the entire memory arrangement.
- An uneven load on certain memory segments for example, as a result of above-average repeated writing and reading, can therefore lead to a reduction in the life of a memory arrangement.
- a physical address is received.
- the physical address is assigned to a first memory segment of a memory arrangement.
- the physical address is modified to a modified physical address.
- the modified physical address is assigned to a second memory segment of the memory arrangement. Then that memory segment can be selected that corresponds to the modified physical address.
- the second memory segment can thus be selected, for example in order to store a memory value or to call up a memory value stored there.
- the storage arrangement can be set up to store data and to provide stored data for reading.
- the memory arrangement can be set up to store and provide data for executing a program in real time.
- the memory arrangement can (temporarily) store memory values that are generated, called up and / or processed when a program is executed.
- the memory arrangement can comprise memory cells of a volatile memory.
- the memory arrangement is set up to maintain stored information or stored values as long as it is in operation and / or is supplied with an operating current. In the event of an interruption in the power supply, the volatile memory can, for example, maintain the stored information for a fraction of a second, or for an even longer period.
- the memory array includes cells of an SRAM and / or cells of a DRAM.
- the memory arrangement is part of a processor register and / or is coupled to machine code operands of a processor.
- the memory arrangement is coupled to a processor unit as data memory and / or program memory.
- the memory arrangement may comprise memory cells of a non-volatile memory.
- the non-volatile memory can include, for example, a ROM, PROM, EPROM, EEPROM, Flash EEPROM, FRAM, MRAM or phase change RAM.
- the memory arrangement can comprise an arrangement of memory segments.
- a memory segment can comprise a memory cell that comprises a circuit of active and passive semiconductor components.
- Each memory cell can be set up to store an information unit, for example a binary value, briefly a bit, and to make it available for reading.
- a memory cell comprises an SRAM cell with four, six, eight or more transistors.
- a memory cell comprises a DRAM cell with two transistors.
- the transistors can include field effect transistors, FET.
- a memory segment can comprise several memory cells.
- An amount of data, or a memory value, that can be stored in a plurality of memory cells of a memory segment can be referred to as a word.
- the number of memory cells in a memory segment can correspond to a (maximum) word length.
- the number of memory cells in a memory segment is 2, 4, 8, 16, 32, 64 or 2 to the extent n, where n is greater than 6.
- the number of memory cells in a memory segment can correspond to half a length of a word (halfword).
- the memory arrangement can have a word length of eight bits and the memory segments can each be four bits long.
- a respective physical address can be assigned to each memory segment in order to enable a unique assignment and thus a unique selection of the respective memory segment for a read or write operation.
- the memory segments of the memory arrangement can be organized in rows and columns.
- the storage arrangement can be subdivided into banks, each bank being able to comprise a predetermined number of rows and / or a predetermined number of columns.
- a particular memory segment can be uniquely selected using a combination of the associated row, the associated column and, if present, the associated bank.
- the physical address can include details of the row, the column and, if any, the bank.
- the memory arrangement can be provided as a separate, independent unit and / or integrated in an overall system.
- the storage arrangement can be configured as part of a main storage, a secondary storage and / or another storage of a computer system.
- the computer system can be a universally usable computer system, which can comprise, for example, a general-purpose computer, a PC, a mobile computing device or a workstation.
- the memory arrangement can be part of an embedded system which is set up and adapted to perform certain operations.
- the embedded system includes a computing system.
- the embedded system can, for example, be set up to carry out a monitoring function, a control function, and / or a regulation function.
- the embedded system can be directed to process data or signals, for example in order to encrypt, decrypt, encode, decode or filter them.
- the embedded system can be implemented in application-specific hardware, for example in a motor vehicle, an aircraft, a medical device, a household appliance, a consumer electronics device or in a mobile device.
- the embedded system can communicate with other embedded systems and / or can form a larger overall system with them, for example for controlling parts of a motor vehicle or an aircraft.
- Several embedded systems can be coupled via a bus, for example.
- the memory array is configured to communicate with a microprocessor.
- the memory segments of the memory device can be suitable for storing a memory value in each case and for making a stored memory value available for retrieval.
- the term storage value can refer to the content of the information to be stored.
- the stored value can in particular comprise information that is (temporarily) stored for further processing.
- the storage value comprises an input value for an operation.
- the input value may have been entered by a user or generated by a program.
- the storage value can include an output value that is to be output as a result of an operation.
- the storage value comprises an intermediate result of a processor, a simple or complex operation of a switching mechanism, an arithmetic logic unit and / or an arithmetic-logic unit.
- the stored value may include an input value, an intermediate result and / or a result of an operation of the arithmetic and / or the logic.
- the storage value can have a length of one bit or more bits.
- the length of the memory value is 2, 4, 8, 16, 32 or 64 bits.
- the length of the memory value can be the length of a word of the memory arrangement.
- the physical address can uniquely identify an associated memory segment of the memory arrangement.
- the physical address can be a binary number, ie a sequence of several bits.
- the physical address can be in a language that can be interpreted by machines.
- the physical address can be present as a hexadecimal number, which can be converted into a corresponding binary number.
- the physical address can be assigned by a processor unit to a respective storage value which is to be stored in the storage arrangement.
- the processor unit can use the physical address to assign one in the respective retrieve stored memory segment of the memory array stored value.
- a memory management unit MMU
- the physical address can be supplied together with the storage value in a data packet. For example, it can be specified which (bit) positions of the data packet designate the physical address and which others designate the storage value. Alternatively or additionally, the physical address and the memory packet can be received via separate paths. For example, the memory value is transmitted via a data bus, while the physical address is transmitted via an address bus.
- the physical address is modified to a modified physical address.
- the modified physical address can be from the same address space as the physical address before the modification.
- the modified physical address is assigned to a different memory segment of the memory arrangement than the physical address before the modification. Accordingly, the physical address can be assigned to a first memory segment of the memory arrangement, and the modified physical address can be assigned to a second memory segment of the memory arrangement.
- the modified physical address can be set into corresponding control signals to select the corresponding memory segment.
- This process can also be called decoding.
- a control unit can be provided which is set up to receive the modified physical address and to generate corresponding control signals in order to select the memory segment to which the modified physical address is assigned.
- the control unit can comprise one or more of the decoding units. If, as mentioned above, the memory segments of the memory arrangement are organized in rows and columns, a certain memory segment can be selected by activating the associated row and the associated column with a respective control signal. In examples in which the memory arrangement is organized in banks, the associated bank can also be controlled in order to select the corresponding memory segment.
- the individual memory segments of the memory arrangement are connected to a respective word line and to a respective bit line.
- the memory segments can each be connected to more than one word line and / or to more than one bit line.
- a single memory segment can be selected by applying respective predefined voltages to the word lines and the bit lines.
- the method described herein causes that the second memory segment can be selected instead of the first memory segment by modifying the physical address to the modified physical address.
- the modified physical address can be from the same address space as the physical address. This can facilitate the translation of the physical address into the modified physical address.
- the physical address can be modified to the modified physical address using a suitable circuit. Consequently, the modification of the physical address to the modified physical address can be done purely on a hardware basis. As a result, a processing time for the modification of the physical address to the modified physical address can be reduced, for example compared to a software-based solution.
- the hardware-based modification of the physical address to the modified physical address can take place within a fraction of a clock cycle, while a comparable modification on the software basis can require several clock cycles.
- the time in clock cycles can relate to the clock cycle of a processor unit and / or a data transmission unit. In this way, a possibility can be created to enable a balanced use of the storage arrangement by regularly changing the storage targets for the data to be stored. As a result, the utilization of the memory segments can be better distributed. In this way, the life of the storage arrangement can be positively influenced.
- an apparatus which comprises a memory arrangement with a plurality of memory segments and a modification unit.
- the modification unit is set up to receive a physical address and to modify the physical address to a modified physical address.
- the physical address is assigned to a first memory segment of the memory arrangement.
- the modified physical address is assigned to a second memory segment of the memory arrangement.
- the device can be set up to carry out the method described above.
- the device described herein may also be part of an embedded system. Additionally or alternatively, the device can be part of a universally usable computer system. The device, the embedded system or the computer system, the described herein may be able to perform the method described herein.
- the memory arrangement of the device described herein can correspond to the memory arrangement described above with reference to the method. Accordingly, the memory segments can each be set up for storing and providing a stored value. As described above, a respective physical address can be assigned to each memory segment.
- the physical address can be modified to the modified physical address before the corresponding memory segments are selected.
- the process of actuating the corresponding memory segments can be omitted.
- the modification of the physical address to the modified physical address can be carried out independently of a memory management unit, if present.
- the physical address comprises a group of address segments, of which a subset of the address segments can be modified to obtain the modified physical address.
- the physical address can be divided into the address segments.
- the address segments can include a row, a column and, if present, a bank that can determine a single memory segment.
- the group of address segments includes a first address segment that identifies the row of the memory segment, a second address segment that identifies the column of the memory segment, and a third segment that identifies the bank of the memory segment.
- the physical address can also include one or more further address segments. The order of the address segments within the physical address can depend on a particular embodiment. When modifying the physical address, one or more address segments from the group of address segments can be modified.
- the subgroup of address segments can denote the address segments modified here.
- One or more address segments of the physical address can be taken from the physical address and processed separately. This process can be called segmenting or parsing.
- the physical address can be segmented into three address segments each for the row, column and bank of the associated memory segment.
- the address segments can be be supplied to each decoder in order to drive the associated memory segment.
- the physical address can only be segmented into several address segments, and one or more of the address segments can then be individually modified. For example, the physical address is segmented into three address segments for the row, column and bank of the associated memory segment, and then one, two or all of these three address segments are modified.
- the physical address can only be modified to the modified physical address and then segmented into the individual address segments.
- the physical address includes three address segments for the row, column and bank of the associated memory segment, and the physical address can be modified by modifying one, two or all of the three address segments before segmenting them into the individual address segments.
- a modification value can be provided.
- the physical address and the modification value can each be a binary number with N digits, where N is a positive integer.
- the modified physical address is obtained from an exclusive-OR combination of the physical address and the modification value.
- the exclusive-OR operation which can also be called XOR operation for short, receives two binary values or two logical values as input values.
- the exclusive-or link can be set up to output a zero or a logical false if the input values are equivalent.
- the exclusive or combination can be set up to output a one or a logical true if the input values are different.
- the device described herein may include an XOR gate configured to receive the physical address and the modification value and to output the modified physical address as a result of XORing the physical address and the modification value.
- an XOR gate can be provided for individual bits that are to be modified.
- the device may include multiple XOR gates configured to modify the physical address bits.
- the modified physical address can be obtained from an XNOR combination of the physical address and the modification value will.
- one or more of the N digits of the physical address and the modification value can be linked according to an XOR link, while the remaining of the N digits can be linked according to an XNOR link.
- one or more of the N digits of the physical address and the modification value can be linked to an inverter.
- an XNOR gate can be provided for individual bits that are to be modified.
- the device may include multiple XNOR gates configured to modify the physical address bits.
- the device can comprise one or more XOR gates in combination with one or more XNOR gates.
- the modification value is generated by means of a random number generator.
- the random number generator can be set up to generate a random number or a sequence of random numbers.
- the random number generator may include a deterministic mechanism, a non-deterministic mechanism, or a combination thereof.
- a random number or a sequence of random numbers can be generated on the basis of software according to a deterministic mechanism.
- a random number or a sequence of random numbers can be generated according to a non-deterministic mechanism based on a physical process.
- the random generator can help ensure that the modification value generated runs through all permutations for an N-digit binary number as evenly as possible.
- the modification value is determined using an integer counter.
- the integer counter increments or decrements at predefined operating points, for example during a re-sorting, a start or a restart of the memory arrangement or the memory segments.
- the integer counter can store and provide a value of the count, ie a counter reading.
- the integer counter can be incremented or decremented by one or more when the memory array is reordered, started or restarted.
- the count of the integer counter is an N-digit binary number, which is increased or decreased by a value, for example one, in the event of an event which triggers a re-sorting, a start or a restart.
- the integer counter can be reset to a minimum value after a maximum value has been reached.
- the minimum value can be o.
- the maximum value of the counter reading can be, for example, the number of possible physical addresses or the number of bit positions in the physical address. In further examples, the maximum value of the counter reading can be less than the number of possible physical addresses or be less than the number of bit positions of the physical address.
- the integer counter can be converted to a maximum value after a minimum value has been reached.
- the terms integer counters and counters are used interchangeably here, unless a difference is explicitly indicated.
- the modification value can be identical to the meter reading of the meter.
- the counter reading of the counter can be modified according to the design of the method or the device in order to obtain the modification value.
- the maximum value for the counter reading may exceed both the number of possible physical addresses and the number of bit positions in the physical address.
- a circuit can be provided which converts the counter reading into a value which is compatible with the addresses from the address space of the physical address. This converted value can correspond to the modification value.
- the maximum value of the counter reading can be less than the number of possible physical addresses or less than the number of bit positions of the physical address.
- stored data can be moved to other storage locations.
- the storage arrangement can be re-sorted if the storage arrangement has been inactive for longer than a defined duration, for example 10 minutes, 30 minutes, one hour or several hours.
- the reordering of the memory arrangement can be carried out by hardware and / or by software for direct memory access (Direct Memory Access, DMA).
- DMA Direct Memory Access
- the stored data can be deleted or erasable.
- the modification value can be changed in addition to the counter reading. Consequently, the manner in which the physical address is modified to the modified physical address can be changed when the memory arrangement or the memory segments are rearranged or started or restarted.
- a balanced utilization of the memory arrangement and the memory segments can thereby be achieved over an extended period of time.
- the device described herein may include a counter for providing the modification value.
- a counter for providing the modification value.
- Such a counter can be set up to increment or decrement the modification value when the memory segments are re-sorted, started or restarted.
- the counter can be an event that triggers a re-sorting, a start or a restart of the memory segments, detect them and, in response, change the modification value.
- the counter may include volatile or non-volatile memory to store the count.
- the counter can also include its own power supply or be connected to it in order to maintain the counter reading even after the storage arrangement has been switched off.
- the value of the integer counter is identical to the modification value.
- the modification value can be uniquely determined from the count of the integer counter, for example by superimposing it with another value.
- the modification value can be obtained from a bit-wise inversion at one, some or all of the N positions of the counter reading of the integer counter. The use of an integer counter can help the modification value to run through all permutations for an N-digit binary number as evenly as possible.
- the modified physical address is made up of a shift and rotation of bit values of the N-digit physical address by K digits in the direction of a first or a last digit, i.e. an Nth digit, the physical address.
- the number K can be greater than zero and not equal to N.
- the modified physical address can thus correspond to a periodic and bitwise shift of the physical address.
- the modified physical address can run through all possible permutations for the N-digit binary number in the address space of the physical address.
- the addresses in the address space of the physical address can thus be used as evenly as possible.
- Such a shift of the bit values of the physical address can take place, for example, using a barrel shifter.
- the device described herein may include a barrel shifter.
- the barrel shifter can be configured to output the modified physical address from a shift and rotation of bit values of the physical address by K digits in the direction of a first or an Nth digit of the physical address.
- a barrel shifter can comprise a circuit which is set up to receive a bit sequence, ie a sequence of several bit values, at its input and to shift and possibly rotate it by a definable number of bit positions.
- the shift distance ie the number of bit positions by which the bit sequence is to be shifted, can vary from be given to a control circuit.
- the control circuit can in particular comprise a counter.
- the circuit of the barrel shifter can in particular be designed in such a way that the bit positions are cyclically connected to one another, so that, depending on the direction of displacement, the least significant bit position changes to the most significant bit position or vice versa.
- the barrel shifter can thus be set up to output a bit sequence shifted by one or more bit positions from the input bit sequence.
- the barrel shifter may comprise a circuit with several multiplexers.
- the barrel shifter may include N to i multiplexers.
- the barrel shifter can be broken down into several steps.
- the barrel shifter may include N-2 VN-to-i multiplexers, where N is a square number.
- the barrel shifter can comprise a decoder, which converts the displacement distance into a corresponding electrical signal.
- the barrel shifter comprises an I-out-of-N decoder, which comprises N outputs and activates one of these outputs according to the shift distance.
- the barrel shifter can comprise several decoders, which are cascaded.
- the number K is determined by means of an integer counter, which increments or decrements when the memory arrangement is re-sorted.
- the integer counter can be configured as described above.
- the device described herein may include a corresponding counter, for example as described above.
- the binary number of the physical address contains N zeros or N ones. If it is determined that the binary number of the physical address contains N zeros or N ones, it is determined whether the number N is even or odd. If N is an even number, the binary number of the physical address is inverted at N / 2 digits. If N is an odd number, the binary number of the physical address is inverted at (N-I) / 2 digits. Modification instructions can thus be provided for situations in which a shift of the incoming physical address would be unsuccessful because it consists of only zeros or only ones. This can prevent a possible reduction in the effectiveness of the method or the device described herein.
- the count of the integer counter is even or odd. If it is determined that the binary number of the physical address contains N zero or N one and that the count of the integer counter is odd, the binary number of the physical address is inverted. Alternatively, the binary number of the physical address can be inverted if the count of the integer counter is even. Exceptions can thus be provided for situations in which a shift in the physical address would be unsuccessful. This can prevent a possible reduction in the effectiveness of the method or the device described herein.
- the second memory segment is selected by decoding the modified physical address.
- a memory value can furthermore be stored in the selected memory segment.
- a stored memory value can be read analogously to the description above. Accordingly, an operation for reading the stored value can be linked to the physical address, which is converted into the modified physical address before reading, so that access to the stored value is accomplished.
- the device described herein further comprises a processor unit and a data transmission unit.
- the processor unit can be set up to transmit a stored value to the memory device or to retrieve a stored memory value from the memory device.
- the physical address can be assigned to the stored value.
- the data transmission unit can connect the processor unit to the memory device and can be set up to transmit the physical address between the processor unit and the memory device.
- the data transmission unit can comprise a bus.
- the bus can comprise a data bus for the transfer of a memory value and an address bus for the transfer of the physical address.
- the data bus and the address bus can be provided as separate buses.
- FIG. 1 is a schematic flow diagram of a method according to an example.
- FIG. 2A to 2C are schematic diagrams of a device according to an example.
- FIG. 3 is a schematic diagram of a modification unit according to one
- FIG. 4 is a schematic diagram of a device according to an example.
- FIG. 5 is a schematic diagram of a device according to an example.
- FIG. 6A and 6B are schematic diagrams of a modification unit and a table with physical addresses and the associated modified physical addresses according to an example.
- FIG. 7A and 7B are schematic diagrams of a modification unit and a shift and rotation of a physical address to modified physical addresses according to an example.
- FIG. 8 is a schematic diagram of an apparatus according to an example.
- FIG. 1 shows a schematic flowchart of a method 100 for operating a memory arrangement.
- the method 100 may be applicable to one of the examples of a memory arrangement described herein.
- the method 100 can be applicable to the device 200 described below.
- a physical address is received that is associated with a first memory segment of a memory array.
- the physical address is modified to a modified physical address that is associated with a second memory segment of the memory array.
- the second memory segment can be selected at 106.
- FIG. 2A to 2C show a device 200 for operating a memory arrangement 210.
- the device 200 can be part of a universally usable computer system, part of an embedded system or a combination thereof.
- the device 200 can be set up to obtain a storage value for storage or for temporary storage in the storage arrangement 210.
- the memory arrangement 210 can be configured as described above.
- memory array 210 may include an array of multiple SRAMs, DRAMs, or other RAMs or flash memories.
- the memory arrangement 210 comprises a plurality of memory segments including the first memory segment Si and the second memory segment S2.
- the memory segments Si and S2 are provided with reference characters. Other memory segments have no reference numerals in order to increase the clarity.
- the memory segments Si, S2 can have a uniform storage capacity, for example 8 bits, 16 bits, 32 bits, 64 bits or 2 n bits, where n is a natural number larger than 6.
- the memory segments of the memory arrangement can be organized in rows and columns as well as in banks.
- FIG. 2A shows a schematic partial view of the device 200 and illustrates the assignment of a first physical address Ai and a second physical address A2 to a first memory segment Si and to a second memory segment S2 of the memory arrangement 210. Accordingly, the first physical address Ai identifies the associated one first memory segment Si clearly. Likewise, the second physical address A2 uniquely identifies the associated second memory segment S2.
- the memory arrangement 210 comprises a modification unit 220, which is configured to receive the first physical address Ai and to modify it to the second physical address A2.
- the second physical address A2 corresponds to the modified physical address as described above.
- a control unit 230 is shown, which is set up to receive the modified physical address A2 and to generate control signals corresponding to the modified physical address A2 in order to select the associated second memory segment S2.
- the control unit 230 may include one or more of the decoding units (not explicitly shown in FIGS. 2A to 2C).
- a memory segment is selected that differs from the memory segment designated at the beginning.
- a rule according to which the received physical address Ai is modified can change over time.
- the local utilization of the memory segments of the memory arrangement 210 can be distributed as evenly as possible over the entire memory arrangement 210.
- the service life of the memory arrangement 210 can thus be positively influenced.
- FIG. 3 schematically shows the physical address Ai which is modified by the modification unit 220 to the modified physical address A2.
- the physical address Ai comprises four address segments All to A14.
- the address segments An to A13 each designate a line, a column and a bank of the first memory segment Si.
- the address segment A14 can be empty, contain further information for determining the associated memory segment and / or contain other information.
- Each of the address segments An to A14 can be one bit or several bits long.
- the address segments All to A14 can have different lengths.
- the modification unit 220 can modify one, part or all four of the four address segments All to A14 to a respective address segment A21 to A24.
- the address segments A21 to A24 of the modified physical address A2 each have the same length as the address segments An to A14 of the incoming physical address Ai.
- the physical address Ai is segmented into the address segments All to A14, which are individually modified by the modification unit 220.
- the modification unit 220 can comprise a plurality of modification units for a respective address segment.
- the modification unit 220 receives the physical address Ai contiguously and modifies it.
- the modification unit 220 can selectively modify the address segments An to A14 from the connected physical address Ai without segmenting them.
- FIG. 4 schematically shows examples of the memory arrangement 210, the modification unit 220 and the control unit 230.
- the memory arrangement 210 comprises a plurality of memory segments 214, which comprises the first memory segment Si and the second memory segment S2, which are shown in FIG. 4 are not explicitly shown.
- the memory segments 214 are organized into banks 212, rows and columns.
- Memory segments 214 each include one or more SRAM cells.
- Memory segments 214 are associated with a respective physical address. In FIG. 4, not all memory segments are provided with a corresponding reference symbol 214 in order to increase the clarity.
- the control unit 230 comprises a row decoder 232, a column decoder 234, a bank decoder 236.
- the decoding unit 230 may comprise a plurality of column decoders 234 and a plurality of read / write circuits 238, the number of which corresponds to the number of the memory banks 212.
- the control unit 230 can comprise a read / write circuit 238 for reading or writing a memory value.
- the decoders 232 to 236 are set up to select a single memory segment 214.
- row decoder 232 can drive a single row by applying a predetermined voltage to that row.
- the column decoder 234 and the bank decoder 236 can drive a single column and a single bank by changing a voltage applied there.
- read / write circuit 238 can be operated to write a memory value to the selected memory segment or to read from the selected memory segment.
- the physical address Ai comprises address segments All to A13, which determine the row, column and bank of the first memory segment Si. In the example of FIG.
- the modification unit 220 can be set up to receive the physical address Ai contiguously, ie without the physical address Ai being segmented into the address segments An to A13.
- the modified physical address A2 is segmented into its address segments A21 to A23 and fed to the respective decoder 232 to 236.
- the address segments A21 to A23 of the modified physical address determine the row, column and bank of the associated memory segment S2 in the memory arrangement 210.
- the decoders 232 to 236 receive the respective address segment A21 to A23 and select the associated second memory segment S2.
- FIG. 5 schematically shows another example of the modification unit 220.
- the modification unit 220 comprises a row modification unit 222, a column modification unit 224 and a bank modification unit 226.
- the row modification unit 222 is set up to receive the first address segment At the physical address Ai and to modify it to a modified first address segment A21.
- the column modification unit 224 and the bank modification unit 226 are set up to receive the respective address segments A12 and A13 and to modify them to a respective modified address segment A22 and A23.
- the modification unit 220 comprises three modification units 222-226 for the row, column and bank.
- the modification unit 220 may include only one or two of the modification units 222-226 to selectively modify the row, column and / or bank of the physical address Ai.
- FIG. 6A and 6B schematically show an example of a modification unit 220.
- the modification unit according to the example of FIG. 6A and 6B comprise a counter 240 and a plurality of XOR gates 242.
- the number of XOR gates 242 can correspond to the number of bit positions to be modified in the incoming physical address Ai. Alternatively or additionally, the number of XOR gates 242 can correspond to the number of bit positions of an address sensor segment of the incoming physical address Ai, which is to be modified.
- the incoming physical address Ai is exemplified as a four-digit binary number
- the modification unit 220 includes four XOR gates 242.
- the counter 240 comprises a circuit for storing and incrementing a counter reading as an N-digit binary number.
- counter 240 may include circuitry for storing and decrementing a counter reading as an N-digit binary number.
- the length N of the binary number of the counter reading corresponds to the number of bit positions of the incoming physical address Ai.
- the counter reading of the counter 240 increments or decrements when the storage arrangement 210 is re-sorted, started or restarted.
- the counter 240 can be designed as described above.
- Each XOR gate 242 is configured to modify a respective bit of the physical address Ai.
- the XOR gates 242 receive at their input a respective bit of the physical address Ai, as illustrated by lines 228, and a respective bit of the counter reading of the counter 240.
- the counter reading of counter 232 corresponds to a modification value M, see FIG. 6B.
- the counter reading can be modified to a modification value M and supplied to the XOR gates 242.
- one or more of the XOR gates 242 can each be replaced by an XNOR gate.
- FIG. 6B shows a tabular representation of modified physical addresses A2 which result from an exclusive-OR combination of a four-digit binary physical address Ai with a four-digit binary counter reading as a modification value M.
- the physical address Ai from a linear address space in which a total of sixteen addresses from 0 to 15 are numbered linearly, which are represented as four-digit binary numbers (0000 to 1111) in the first column of the table.
- the modification value M can assume a value between 0 and 15, which is represented by four-digit binary numbers (0000 to 1111) in the top line of the table in FIG. 6B.
- the values from the second line and from the second column of the table represent the modified physical address A2 as the results of an exclusive-OR combination of the incoming physical address Ai with the respective modification value M.
- the values from an exclusive or combination of the physical address Ai with a modification value M of (0000) are shown.
- the modified physical address A2 is identical to the incoming physical address Ai in this case.
- the values are the values from an exclusive-OR combination of the physical address Ai represented with a modification value M of (im), which corresponds to an inversion of the physical address Ai.
- the modification value M can be changed during a re-sorting, a start or a restart of the memory arrangement 210 or the device 200.
- the maximum value for the counter status of the counter 240 can correspond to the number of possible physical addresses.
- the modification value M is increased by one starting from 0000 when the storage arrangement 210 is re-sorted, started or restarted. If the modification value M has the maximum value 1111 (or 15 in the decimal representation), the modification value M can be reset to 0000 (or o in the decimal representation) when the storage arrangement 210 is re-sorted, started or restarted.
- the modification value M can be increased by more than one.
- the shift in the value of the modification value M can be varied over time or as desired.
- the modification value M can be reduced by one or more when the storage arrangement 210 is re-sorted, started or restarted and reset to 1111 if the modification value M is 0000 and is to be further reduced.
- a random number generator can be provided, which is set up to generate a four-digit random binary number. Accordingly, the modification value M can correspond to the four-digit random binary number from the random number generator. In further examples, the modification value M can be obtained from a combination of the counter reading of the counter 240 with the four-digit random binary number from the random number generator.
- FIG. 7A shows a further example of a modification unit 220.
- the modification unit 220 comprises a counter 240 and a barrel shifter 244.
- the counter 240 and / or the barrel shifter 244 can be configured as described above.
- Barrel shifter 244 may receive the physical address Ai bit by bit, as illustrated by lines 228.
- FIG. 7A and 7B are the physical address Ai and the modified physical address A2, each exemplified as four-digit binary numbers.
- the barrel shifter 244 may modify a portion or an address segment of the incoming physical address Ai.
- the barrel shifter 236 can also receive the counter reading of the counter 240.
- the barrel shifter 244 can determine from the counter reading of the counter 240 a number of bit positions by which the bits of the physical address Ai are to be shifted. The result of the shift can correspond to the modified physical address A2.
- a random number generator can be provided which generates a four-digit random binary number. Accordingly, the counter reading can be replaced by or overlaid with the four-digit random binary number of the random number generator.
- the random number generator can be configured as described above.
- the modification unit 220 may further include a multiplexer 246 and a detection circuit 248.
- the detection circuit 248 can be configured to detect whether the binary number of the physical address Ai consists of only ones or only zeros.
- the detection circuit 248 includes an AND gate and a NOR gate each receiving the bits of the physical address A, an OR gate that combines the output values of these gates, and another AND gate that the output value of the OR -Gatters linked to the counter reading of the counter 240 and an output value in the multiplexer 246. Accordingly, the multiplexer 246 inverts the bits of the physical address Ai if all bits of the physical address are zeros or ones and if the count of the counter 240 is an odd number. In further examples, the binary number of the physical address Ai can be inverted at two of the four bit positions.
- FIG. 7B shows the incoming physical address Ai and two examples of modified addresses A2 and A2 *, which are generated using the modification unit 220 of FIG. 7A can be preserved.
- the modified addresses A2 and A2 * are obtained from a shift of the four-digit binary number of the physical address Ai in a respective direction Mi, M2.
- the binary number of the physical address Ai comprises four bit positions with the bit values ai to a4, where ai is the least significant bit and a4 is the most significant bit of the physical address Ai.
- the incoming physical address Ai is a four-digit binary number 1000, which corresponds to a value of 8 in the decimal representation.
- the binary number of the physical address Ai is shifted to the right by one bit position, as illustrated by arrow Mi.
- Bit ai is rotated from the least significant bit position of the physical address Ai to the left and placed at the most significant bit position.
- the remaining bit values a2 to a4 are shifted one bit to the right, which results in a value of oioo (4 in the decimal representation).
- the binary number of the physical address Ai is shifted to the left by one bit position, as illustrated by arrow M2.
- This can correspond to a shift of the bit values ai to a4 of the physical address Ai by one bit position to the highest bit position, as represented by the corresponding modified physical address A2 *.
- Bit a4 is rotated to the right from the most significant bit position of the physical address Ai and placed at the least significant bit position.
- the remaining bit values ai to a3 are shifted one bit to the left, which results in a value of 0001 (1 in the decimal representation).
- FIG. 7B show a shift and rotation of the bit values of the physical address Ai by one bit position each.
- the modification unit 220 can be configured to shift the bit values of the physical address to the left or to the right by more than one bit position.
- FIG. 8 shows a device 200 according to a further example.
- the device 200 can include a processor unit 250 and a data transmission unit 252.
- the processor unit 250 can in particular be set up to transmit a storage value to the storage device 210 or to retrieve a storage value from the storage device 210.
- the data transmission unit 252 can connect the processor unit 210 to the memory device 210 and can be configured to transmit the physical address Ai between the processor unit 250 and the memory device 210.
- the data transfer unit 252 can comprise a data bus for transferring the memory value and an address bus for transferring the physical address between the processor 250 and the memory arrangement 210.
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Abstract
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DE102018128980.4A DE102018128980A1 (en) | 2018-11-19 | 2018-11-19 | METHOD AND DEVICE FOR OPERATING A STORAGE ARRANGEMENT |
PCT/EP2019/076585 WO2020104091A1 (en) | 2018-11-19 | 2019-10-01 | Method and device for operating a memory assembly |
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US (1) | US11557327B2 (en) |
EP (1) | EP3884490A1 (en) |
CN (1) | CN112912957A (en) |
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DE3572553D1 (en) * | 1984-09-28 | 1989-09-28 | Siemens Ag | Data-processing systems with virtual storage addressing for a plurality of users |
DE19922155A1 (en) | 1999-05-12 | 2000-11-23 | Giesecke & Devrient Gmbh | Memory arrangement and memory access procedure for microcomputers has an additional scrambling step to increase data security, for use in financial applications etc. |
DE10322541A1 (en) | 2003-05-19 | 2004-12-16 | Infineon Technologies Ag | Memory chip with integral address scrambling unit whereby the address can be scrambled in different ways according to the address control bits |
KR20110101012A (en) | 2010-03-05 | 2011-09-15 | 삼성전자주식회사 | Method and computer readable recording media, and apparatus for parallel data interfacing using combined coding |
WO2009140981A1 (en) * | 2008-05-21 | 2009-11-26 | Verigy (Singapore) Pte. Ltd. | Method and apparatus for the determination of a repetitive bit value pattern |
KR20130039505A (en) | 2011-10-12 | 2013-04-22 | 삼성전자주식회사 | Address transforming circuit having random code generator and semiconductor memory device including the same |
US9146688B2 (en) * | 2012-12-05 | 2015-09-29 | SanDisk Technologies, Inc. | Advanced groomer for storage array |
KR102133573B1 (en) | 2013-02-26 | 2020-07-21 | 삼성전자주식회사 | Semiconductor memory and memory system including semiconductor memory |
US10956318B2 (en) * | 2018-06-19 | 2021-03-23 | Macronix International Co., Ltd. | Overlapping ranges of pages in memory systems |
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CN112912957A (en) | 2021-06-04 |
US20210398571A1 (en) | 2021-12-23 |
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