DE112017000855B4 - Energy-efficient temporally multiplexed neurosynaptic core for implementing neural networks - Google Patents

Abstract

A multiplexed core neural circuit comprising:T sets of electronic neurons, where T is an integer multiplexing factor and is equal to four;T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons; anda synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each of the T sets of electronic axons to its corresponding set of electronic neurons; anda set of axon buffers each divided into T partitions, each of the T partitions associated with one of T sub-time steps of a time step, and each of the T sub-time steps having:a common set of neuron parameters, the neuron parameters comprising a spike threshold, a leak rate, and axon type weights;a common set of neuron target locations indicative of a target axon for each of the electronic neurons, anda different set of neuron membrane potentials than the other sub-time steps, each set of neuron membrane potentials having a membrane potential V that increases when receiving inputs from source excitatory neurons and that decreases when receiving inputs from source inhibitory neurons,wherein the multiplexed core neural circuit is time-multiplexed for the T sub-time steps of the time step, with synaptic weights and the neuron parameters being shared across the T sub-time steps, andwherein each of the T Sub-time steps are assigned to a different set of neuron target locations and a different set of neuron membrane potentials than the other sub-time steps, so that the multiplexed neural core circuit operates as four cores during a time step, with each of the four cores having its own unique neuron target locations and neuron membrane potentials.

Description

BACKGROUND

The present invention relates to neurosynaptic networks, and more particularly, this invention relates to time-division multiplexed neurosynaptic cores.

Core-based neurosynaptic systems consist of multiple neurosynaptic cores, where the neurosynaptic cores are configured and connected to form a neurosynaptic network. A single neurosynaptic chip contains a fixed number of neurosynaptic cores. For example, a single neurosynaptic chip may contain hundreds or thousands of cores. Chips of different sizes, i.e., number of cores, can be manufactured. One or more chips are required to implement a neurosynaptic system. Since manufacturing neurosynaptic chips is expensive, it is desirable to minimize the number of chips used by a given system.

In some environments, a large number of neurosynaptic cores can be programmed to perform the same function. Moreover, a given configuration of neurosynaptic cores can be tiled multiple times on a chip. In other words, an arrangement or interconnection between cores can be repeated multiple times on one or more chips, so that a first group of cores performs the same task(s) as a second group of cores.

In this context, several documents have already been published: The document US 2014 / 0 180 987 A1 describes time-based multiplexed neurosynaptic modules with implicit memory addressing for a neural network implementation. The document CN1 05 095 967 A describes a neuromorphic network core for simulating the data processing of a biological synapse-neuron-brain structure. It uses multiple layers of computing cores and inter-level connections. The document US 2014 /0 222 740 A1 describes a consolidation of several neurosynaptic nuclei into one memory. The document also describes US 2015 / 0 324 684 A1 neuromorphic hardware for neural and non-neural computations. A delay circuit is also used to generate neural output values. The document also describes US 8 977 578 B1 a time-based multiplexed neuromorphic network that uses a subset of connections at different time intervals. In addition, the paper by MINKOVICH, Kirill [et al.]: “Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler” (published in IEEE transactions on neural networks and learning systems, 2012, Vol. 23, No. 6, pp. 889-901 ) how hardware can be configured for neuromorphic computing to better simulate biological neural networks. The paper also describes CRUZ-ALBRECHT, Jose M.; DEROSIER, Timothy; SRINIVASA, Narayan: “A scalable neural chip with synaptic electronics using CMOS integrated memristors (published in Nanotechnology, 2013, Vol. 24, No. 38 ) a scalable neurochip with synaptic electronics and the use of integrated CMOS memristors. And finally, the document by MEROLLA, Paul A. [et al.]: “A million spiking-neuron integrated circuit with a scalable communication network and interface - Supplementary Materials” (published in Science, 2014, Vol. 345, No. 6197 ) a neuromorphic core, which consists of a plurality of core units of the TrueNorth architecture, each with 256 neurons for calculations and 256 axons for communication and 256 * 256 synapses for memory.

Nevertheless, there is still potential for further optimization in the relatively young technical field of neuromorphic computing to improve the performance of such circuits.

BRIEF DESCRIPTION

This problem is solved by the subject matter of the independent claims. Further embodiments arise from the respective dependent claims.

A multiplexed neural core circuit according to an embodiment comprises, at an integer multiplexing factor T greater than zero, T sets of electronic neurons, T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons, and a synaptic interconnection network having a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons.

According to another embodiment, a computer-implemented method for multiplexing a core neural circuit at an integer multiplexing factor T greater than zero comprises configuring T sets of electronic neurons, configuring T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons, and configuring a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons.

According to yet another embodiment, a neurosynaptic system comprises a neurosynaptic chip, a single-core neurosynaptic module as a component on a chip, or a multi-core neurosynaptic module as a component on a chip including a plurality of multiplexed neural core circuits interconnected via an on-chip network, each of the plurality of multiplexed neural core circuits comprising, at an integer multiplexing factor T greater than zero, T sets of electronic neurons, T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons.

Other aspects and embodiments of the present invention will become apparent from the following detailed description, which, taken in conjunction with the drawings, illustrates by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

• 1 ein Modul mit einem neurosynaptischen Kern gemäß einer Ausführungsform der Erfindung veranschaulicht.
• 2 ein neurosynaptisches Netzwerk gemäß einer Ausführungsform der Erfindung veranschaulicht.
• 3 einen gemultiplexten neuronalen Kernschaltkreis gemäß einer Ausführungsform der Erfindung veranschaulicht.
• 4 eine Mehrzahl von möglichen Speicherkonfigurationen eines gemultiplexten neuronalen Kernschaltkreises gemäß einer Ausführungsform der Erfindung veranschaulicht.
• Die 5A bis 5C die Effizienz eines gemultiplexten neurosynaptischen Kerns gemäß einer Ausführungsform der Erfindung veranschaulichen.
• Die 6A bis 6B die Weiterleitung von Spike-Ereignissen zwischen gemultiplexten neurosynaptischen Kernen gemäß einer Ausführungsform der Erfindung veranschaulichen.
• Die 7A bis 7B veranschaulichen die Weiterleitung von Spike-Ereignissen zwischen gemultiplexten neurosynaptischen Kernen gemäß einer Ausführungsform.
• 8 veranschaulicht eine typische Hardware-Umgebung zum Konfigurieren eines gemultiplexten neurosynaptischen Kerns gemäß einer Ausführungsform.

Embodiments of the invention are described below by way of example with reference to the accompanying drawings, in which:

• 1 illustrates a module with a neurosynaptic core according to an embodiment of the invention.
• 2 illustrates a neurosynaptic network according to an embodiment of the invention.
• 3 illustrates a multiplexed neural core circuit according to an embodiment of the invention.
• 4 illustrates a plurality of possible memory configurations of a multiplexed neural core circuit according to an embodiment of the invention.
• The 5A to 5C illustrate the efficiency of a multiplexed neurosynaptic core according to an embodiment of the invention.
• The 6A to 6B illustrate the propagation of spike events between multiplexed neurosynaptic nuclei according to an embodiment of the invention.
• The 7A to 7B illustrate the propagation of spike events between multiplexed neurosynaptic nuclei according to one embodiment.
• 8th illustrates a typical hardware environment for configuring a multiplexed neurosynaptic core according to one embodiment.

DETAILED DESCRIPTION

The following description is intended to illustrate the general principles of the present invention and is not intended to limit the inventive concepts claimed herein. Moreover, certain features described herein may be used in combination with other described features in any of various possible combinations and implementations.

Unless expressly stated otherwise, all terms should be given the broadest possible interpretation, including meanings that arise from the description, meanings understood by those skilled in the art, and/or as defined in dictionaries, treatises, etc.

It should also be noted that the singular forms "a" and "the" when used in the specification and the appended claims include the plural forms as well, unless otherwise indicated. It is also to be understood that the terms "comprises" and/or "comprising" when used in this specification indicate the presence of stated features, integers, steps, operations, elements and/or components. but does not exclude the presence or addition of one or more other characteristics, integers, steps, operations, elements, components and/or groups thereof.

The following description discloses several preferred embodiments of systems, methods, and computer program products for multiplexing neurosynaptic nuclei.

In a general embodiment, a multiplexed core neural circuit, at an integer multiplexing factor T greater than zero, comprises: T sets of electronic neurons, T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons.

In another general embodiment, a computer-implemented method for multiplexing a core neural circuit at an integer multiplexing factor T greater than zero comprises: configuring T sets of electronic neurons, configuring T sets of electronic axons, wherein each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and configuring a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, wherein the interconnection network connects each set of the T sets of electronic axons to its corresponding set of electronic neurons.

In another general embodiment, a neurosynaptic system comprises a neurosynaptic chip, a single-core neurosynaptic component-on-chip module, or a multi-core neurosynaptic component-on-chip module including a plurality of multiplexed core neural circuits interconnected via an on-chip network, each of the plurality of multiplexed core neural circuits comprising, at an integer multiplexing factor T greater than zero, T sets of electronic neurons, T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons.

1 1 illustrates a neurosynaptic core module ("neurosynaptic core" or "core") 10 according to an embodiment of the invention. The core 10 is a core neural circuit/neurosynaptic circuit. The core 10 includes a plurality of incoming axons 15 and a plurality of neurons 11. Each neuron 11 and axon 15 has configurable operating parameters. The core 10 also includes a synaptic crossbar 12 having a plurality of synapses 31, a plurality of rows/axon pathways 26, and a plurality of columns/dendritic pathways 34.

Each synapse 31 transmits firing events (e.g., spike events) between an axon 15 and a neuron 11. In particular, each synapse 31 is located at the intersection point between an axon pathway 26 and a dendritic pathway 34 such that a connection between the axon pathway 26 and the dendritic pathway 34 is made through the synapse 31. Each axon 15 is connected to an axon pathway 26 such that the axon 15 sends spikes to the connected axon pathway 26. Each neuron 11 is connected to a dendritic pathway 34 such that the neuron 11 receives spikes from the connected dendritic pathway 34.

Each synapse 31 has a synaptic weight. The synaptic weights of the synapses 31 of the core 10 may be represented by a weight matrix W, where an element W _ij of the matrix W represents a synaptic weight of a synapse 31 located in a row/axon path i and a column/dendrite path j of the crossbar 12. In one embodiment, the synapses 31 are binary memory units. For example, each synapse 31 may have a weight of “0”, indicating that the synapse 31 is non-conductive, or a weight of “1”, indicating that the synapse 31 is conductive. A learning rule such as spike-timing dependent plasticity (STDP) may be applied to update the synapse weights of the synapses 31.

2 illustrates an exemplary neural network 50 according to an embodiment of the invention. The neural network 50 is is a scalable neuromorphic and synaptronic architecture. The neural network 50 includes a plurality of chip structures 70. Each chip structure 70 includes a plurality of cores 10. An event routing system 75 of the neural network 50 routes firing events between cores 10 of the chip structures 70. A core 10 of the neural network 50 can forward firing events to and receive firing events from another core 10 of the same chip structure 70 or of a different chip structure 70.

3 illustrates a multiplexed neural core circuit 100 according to an embodiment of the invention. The core circuit 100 is a multiplexed neurosynaptic core circuit because it includes one or more memories that store neural attributes for multiple neurons 11. The core circuit 100 also multiplexes one or more computation and control logic circuits for multiple neurons 11. The core circuit 100 includes a memory 110 that stores data for the neural core circuit, a control unit (i.e., processing and computation logic circuit) 120 for the memory unit 110, and a memory interface circuit 115. The circuit 115 may be a standard memory interface circuit. As shown, the memory 110 includes a memory 110a, a synaptic crossbar or interconnect network 110b, and a memory 110c.

The synaptic crossbar or interconnection network 110b may contain synaptic interconnection information for multiple neurons 11, having multiple electronic synapses connecting electronic axons of the core neural circuit 100 to the electronic neurons of the core neural circuit 100. Each synapse of the interconnection network 110b connects an electronic axon to an electronic neuron.

Various additional memory subcomponents store data for the core neural circuit 100. In particular, the core circuit 100 includes a memory 110a and a memory 110c, each of which stores data for the core neural circuit. Additionally, the memory 110a may be divided into T partitions. Each of the T partitions may be associated with a corresponding one of T sub-time steps of a time step. The memory 110c stores additional data for the core neural circuit 100. In one embodiment, the additional data includes neural attributes shared across two or more of the T sub-time steps of the time step. For example, the memory 110c may store neuron parameters for the neurons 11, forwarding data for the neurons 11, etc., as discussed in more detail below.

In one embodiment, 110 may contain multiple entries or rows. For example, synaptic crossbar 110b and memory 110c may contain multiple entries, each entry storing neuronal attributes for a neuron 11. In one embodiment, each entry stores the following neuronal attributes for a neuron 11: synaptic connection information (W _ij ), neuron parameters, and routing information. In one embodiment, a first subset of each entry stores synaptic weights of synapses 31 connecting a neuron 11 to axons 15.

In one embodiment, the controller 120 includes an input processing fabric and a computation fabric. The processing fabric is configured to receive and process, for each entry, firing events intended for that entry. For example, each received firing event may target an axon 15 to which a neuron 11 represented by the entry is connected. As indicated above, a first subset of each entry stores synapse weights of synapses 31 connecting a neuron 11 to axons 15. If the synapse 31 connecting the target axon 15 and the neuron 11 represented by the entry is conductive, the firing event may be integrated by the computation fabric. In one embodiment, the processing structure comprises a decoder, a scheduler control unit, a scheduler, an axon type register, a multiplexing control unit, and a dot product module.

In a neural network having multiple core circuits 100, firing events are passed between core circuits 100 of the neural network in the form of spike event packets. Each spike event packet may contain a firing event or spike event encoded as a binary address representing a target axon 15, where the firing event was generated by a neuron 11 in the same core circuit 100 or in a different core circuit 100. Each spike event packet may also contain a time step and a sub-time step indicating when a firing event included in that spike event packet was generated. A decoder of each core circuit 100 may be configured to receive and decode spike event packets.

In one embodiment, the scheduler is configured to manage buffering of axons, and the memory 110a includes an axon buffer associated with the axons 15 of the core circuit 100. In other words, the memory 110a of the core circuit 100 may include a set of A axon buffers, where A is the number of axons of the core circuit 100. For a particular axon 15, the scheduler may buffer received firing events directed to the axon 15 in a buffer associated with the axon 15. Furthermore, if each time step has been divided into T sub-time steps, the buffer associated with the axon may be divided based on T and a depth of the memory 110a, as explained in more detail below.

At the beginning of each sub-time step, the scheduler may move the firing events into the axon buffers. In one embodiment, a vector indicating all active axons 15 in the current sub-time step may be read from the scheduler at the beginning of each sub-time step.

The contents of the memory 110 can be read and written once per sub-time step. In particular, for each sub-time step, entries of the memory 110 are individually read out sequentially using a sequential scanner. For each entry representing a neuron 11, a dot product can be calculated between the vector of active axons 15 in the current sub-time step and the synaptic connection information stored in the entry, ie the synapse weights of all synapses 31 to which the dendritic path 34 of the neuron 11 is connected (W _j ).

For each entry, a multiplexer can use information to select a neuron parameter (i.e., Syn0, Syn1, Syn2, Lk). For example, the leak rate Lk stored in the entry can be selected after all spikes have been integrated. An adder can add the neuron parameter selected by the multiplexer to a membrane potential variable selected by another multiplexer. For each entry, the other multiplexer can select the membrane potential variable V stored in the entry for the first addition. For each entry, the other multiplexer can select a modified membrane potential variable for subsequent additions, where the modified membrane potential variable is a temporary variable.

After all spikes have been integrated and the leak rate has been applied, a comparator can determine for each entry whether the modified membrane potential variable exceeds a threshold parameter Th stored in the entry. If the threshold parameter Th is exceeded, the encoder can generate a spike and encode the generated spike into a spike event packet. The membrane potential variable V can be reset to zero before being written back to the entry.

In some embodiments, illustrated below, the memory 110 may be allocated such that the memory 110 includes a first memory, a second memory, a third memory, etc. For example, the memory 110 may include multiple memory arrays, where a first memory array stores synaptic connection information for multiple neurons 11 (i.e., a synaptic crossbar), a second memory array stores neuron parameters for the neurons 11, a third memory array includes axon buffers, and a fourth memory array stores routing information for the neurons 11.

With reference to 4 For example, several possible memory configurations of a multiplexed neural core circuit are now shown according to various embodiments. One option is that the memory configurations may be implemented in conjunction with features from any other embodiment listed herein, e.g., those described with reference to the other figures. Of course, however, such and other memory configurations set forth herein may be used in various applications and/or implementations that are not necessarily explicitly described in the illustrative embodiments listed herein. Furthermore, the memory configurations set forth herein may be used in any desired environment.

In one embodiment, a memory configuration 500 includes a synaptic crossbar 110b and a memory 110c, where the memory 110c has been mapped to include neuron parameters 512, neuron destination locations 514, and neuron membrane potentials 516. The synaptic crossbar 110b stores the synapse weights of the synapses 31 of the core 10 in a weight matrix W. As indicated above, an element W _ij of the matrix W represents a synapse weight of a synapse 31 located in a row/axon path i and a column/dendrite path j of the crossbar. Optionally, the neuron parameters 512 of the memory configuration 500 may include for each neuron 11 connected to the synaptic crossbar 110b: a spike threshold (Th), a leak rate (Lk) and/or weights of each possible axon type (Syn0, Syn1, Syn2). Additionally, the neuron target locations 514 of the memory configuration 500 for each neuron 11 connected to the synaptic crossbar 110b may include a target axon of the neuron 11. Furthermore, the neuron membrane potentials 516 of the memory configuration 500 for each neuron 11 connected to the synaptic crossbar 110b may still include a membrane potential variable (V), wherein the membrane potential includes a single or multi-bit state that increases when receiving input signals from source excitatory neurons and decreases when receiving input signals from source inhibitory neurons.

As illustrated by configuration 500, core neural circuit 100 may be configured to operate at a time-division multiplexing factor of 1 (T=1) such that each time step contains only a single sub-time step. In other words, neural parameters, neuron target locations, and neuron membrane potentials are not shared between two other sub-time steps.

In various embodiments, a size of the synaptic crossbar 110b and memory 110c may depend on a number of axons and neurons in the neurosynaptic core (A x N), as well as the number of stored neuron parameters, neuron targets, and neuron membrane potentials. For example, in an embodiment where the neurosynaptic core has an array of 256 axons x 256 neurons, the synaptic crossbar 110b may have a memory allocation of 256 bits x 256 bits. In such an embodiment, the memory configuration 500 may also be organized such that the neuron parameters 512 have a 256 bits x 102 bits memory arrangement, the neuron targets 514 have a 256 bits x 32 bits memory arrangement, and the neuron membrane potentials 516 have a 256 bits x 20 bits memory arrangement. Accordingly, the synaptic crossbar 110b and the memory 110c of the memory configuration 500 together comprise a 256-bit x 410-bit memory arrangement.

In another embodiment, a memory configuration 502 includes the synaptic crossbar 110b and the memory 110c, where the memory 110c has been allocated to include neuron parameters 512, neuron target locations 514, and T sets of neuron membrane potentials 516. The T sets of neuron membrane potentials 516 comprise neuron membrane potentials for those of electronic neurons of a core neural circuit 100, such that each of the T partitions stores neuron membrane potentials for the plurality of electronic neurons for one of the T sub-time steps.

As in 4 As shown, T = 4, so that configuration 502 contains four sets of neuron membrane potentials 516 for four sub-time steps of a time step, but it is understood that T may be any number. For example, in other embodiments, T may be equal to 2, 8, 16, 64, etc. In memory configuration 502, the synaptic crossbar 110b synapse weights, neuron parameters 512, and neuron target locations 514 may be shared across the T sub-time steps, with each of the T sub-time steps associated with a different set of neuron membrane potentials 516. Accordingly, the memory configuration 502 enables a single core neural circuit to be time-multiplexed for T sub-time steps of a time step in a manner such that the synapse weights, neuron parameters, and neuron target locations are shared across the sub-time steps, but each sub-time step is associated with a different set of neuron membrane potentials 516. This may allow a single physical core 10 to function as four cores during a time step, with each of the four simulated cores having its own unique neuron membrane potentials.

As mentioned above, in one embodiment, the synaptic crossbar 110b may have a memory allocation of 256 bits x 256 bits. In addition, the memory configuration 502 may be configured such that the neuron parameters have a 256 bits x 102 bits memory allocation, the neuron target locations 514 have a 256 bits x 32 bits memory allocation, and the T sets of neuron membrane potentials 516 have T (256 bits x 20 bits) memory allocations. Accordingly, when T = 4, the synaptic crossbar 110b and memory 110c of the memory configuration 502 together have a 256 bits x (256 + 102 + 32 + T(20)) bits memory allocation, or 256 bits x 470 bits. A core neural circuit 100 configured to include memory configuration 502 can perform the same number of spike calculations in a single time step as four separate core neural circuits 100 with the same synapse weights, neuron parameters, and neuron target locations, but different neuron membrane potentials logged for each sub-time step.

In yet another embodiment, the memory configuration 504 includes the synaptic crossbar 110b and the memory 110c, where the memory 110c is allocated to Neuron parameters 512, T sets of neuron target locations 514, and T sets of neuron membrane potentials 516. The T sets of neuron target locations 514 comprise neuron target locations for the plurality of electronic neurons of a core neural circuit 100 such that each of the T partitions stores neuron target locations for the plurality of electronic neurons for one of the T sub-time steps. In addition, the T sets of neuron membrane potentials 516 comprise neuron membrane potentials for the plurality of electronic neurons of a core neural circuit 100 such that each of the T partitions stores neuron membrane potentials for the plurality of electronic neurons for one of the T sub-time steps.

As in 4 , T = 4, so that configuration 504 includes four sets of neuron target locations 514 and four sets of neuron membrane potentials 516 for four sub-time steps of a time step, but it should be understood that T may be any number. For example, in other embodiments, T may be equal to 2, 8, 16, 64, etc. In memory configuration 504, the synaptic weights of synaptic crossbar 110b and neuron parameters 512 may be shared across the T sub-time steps, with each of the T sub-time steps associated with a different set of neuron target locations 514 and a different set of neuron membrane potentials 516. Accordingly, the memory configuration 504 enables a single core neural circuit to be time-multiplexed for T sub-time steps of a time step in a manner such that the synapse weights and neuron parameters 512 are shared across the sub-time steps, but each sub-time step is associated with a different set of neuron target locations 514 and a different set of neuron membrane potentials 516. This may allow a single physical core 10 to function as four cores during a time step, with each of the four simulated cores having its own unique neuron target locations and neuron membrane potentials.

As mentioned above, in one embodiment, the synaptic crossbar 110b may have a memory allocation of 256 bits x 256 bits. Additionally, the memory configuration 504 may be configured such that the neuron parameters 512 have a 256 bits x 102 bits memory arrangement, the T sets of neuron target locations 514 have T (256 bits x 32 bits) memory arrangements, and the T sets of neuron membrane potentials 516 have T (256 bits x 20 bits) memory arrangements. Accordingly, when T = 4, the synaptic crossbar 110b and memory 110c of the memory configuration 504 together have a 256 bits x (256 + 102 + T(32 + 20)) bits memory arrangement or 256 bits x 566 bits. A core neural circuit 100 configured to include memory configuration 504 can perform the same number of spike calculations in a single time step as four separate core neural circuits 100 with the same synapse weights and neuron parameters, but different neuron target locations and neuron membrane potentials logged for each sub-time step.

In another embodiment, a memory configuration 506 includes the synaptic crossbar 110b and the memory 110c, where the memory 110c has been allocated to include T sets of neuron parameters 512, neuron target locations 514, and T sets of neuron membrane potentials 516. The T sets of neuron parameters 512 comprise neuron parameters for the plurality of electronic neurons of a core neural circuit 100 such that each of the T partitions stores neuron parameters for the plurality of electronic neurons for one of the T sub-time steps. In addition, the T sets of neuron membrane potentials 516 comprise neuron membrane potentials for the plurality of electronic neurons of a core neural circuit 100 such that each of the T partitions stores neuron membrane potentials for the plurality of electronic neurons for one of the T sub-time steps.

As in 4 , T = 4, so that configuration 506 includes four sets of neuron parameters 512 and four sets of neuron membrane potentials 516 for 4 sub-time steps of a time step, but it should be understood that T may be any number. For example, in other embodiments, T may be equal to 2, 8, 16, 64, etc. In memory configuration 506, the synaptic weights of synaptic crossbar 110b and neuron target locations 514 may be shared across the T sub-time steps, with each of the T sub-time steps associated with a different set of neuron parameters 512 and a different set of neuron membrane potentials 516. Accordingly, the memory configuration 506 enables a single core neural circuit to be time-multiplexed for T sub-time steps of a time step in a manner such that the synapse weights and the neuron target locations are shared across the sub-time steps, but each sub-time step is associated with a different set of the neuron parameters 512 and a different set of neuron membrane potentials 516.

As mentioned above, in one embodiment, the synaptic crossbar 110b may have a memory allocation of 256 bits x 256 bits. In addition, the memory configuration 506 may be configured such that the T sets of neuron parameters 512 comprise T (256 bits x 102 bits) memory arrays, the neuron target locations 514 comprise a 256 bits x 32 bits memory array, and the T sets of neuron membrane potentials 516 comprise T (256 bits x 20 bits) memory arrays. Accordingly, when T = 4, the synaptic crossbar 110b and memory 110c of the memory configuration 506 together comprise a 256 bits x (256 + 32 + T(102 + 20)) bits memory array, or 256 bits x 776 bits. A core neural circuit 100 configured to include memory configuration 506 can perform the same number of spike calculations in a single time step as four separate core neural circuits 100 with the same synapse weights and neuron target locations, but different neuron parameters and different neuron membrane potentials logged for each sub-time step.

In yet another embodiment, a memory configuration 508 includes the synaptic crossbar 110b and the memory 110c, where the memory 110c has been allocated to contain T sets of neuron parameters 512, T sets of neuron target locations 514, and T sets of neuron membrane potentials 516.

As in 4 , T = 4, so that configuration 508 includes four sets of neuron parameters 512, four sets of neuron target locations 514, and four sets of neuron membrane potentials 516 for four sub-time steps of a time step, but it should be understood that T may be any number. For example, in other embodiments, T may be equal to 2, 8, 16, 64, etc. In memory configuration 508, the synaptic weights of synaptic crossbar 110b may be shared across the T sub-time steps. However, each of the T sub-time steps is associated with a different set of neuron parameters 512, a different set of neuron target locations 514, and a different set of neuron membrane potentials 516. Accordingly, the memory configuration 508 enables a single core neural circuit to be time-multiplexed for T sub-time steps of a time step in a manner such that the synapse weights are shared across the sub-time steps, but each sub-time step is associated with a different set of neuron parameters 512, a different set of neuron target locations 514, and a different set of neuron membrane potentials 516.

As mentioned above, in one embodiment, the synaptic crossbar 110b may have a 256-bit x 256-bit memory allocation. Additionally, the memory configuration 508 may be configured such that the T sets of neuron parameters 512 comprise T (256-bit x 102-bit) memory arrays, the T sets of neuron target locations 514 comprise T (256-bit x 32-bit) memory arrays, and the T sets of neuron membrane potentials 516 comprise T (256-bit x 20-bit) memory arrays. Accordingly, when T = 4, the synaptic crossbar 110b and memory 110c of the memory configuration 508 together comprise a 256 x (256 + T(102 + 32 + 20)) bit or 256 bit x 872 bit memory array. A core neural circuit 100 configured to include memory configuration 508 can perform the same number of spike calculations in a single time step as four separate core neural circuits 100 with the same synapse weights but different neuron parameters, different neuron target locations, and different neuron membrane potentials logged for each sub-time step.

In yet another embodiment, a memory configuration 510 includes the synaptic crossbar 110b and the memory 110c, where the memory 110c has been allocated to include neuron parameters 512 and neuron target locations 514. In the memory configuration 510, the memory 110 has been configured such that synaptic weights, the neuron parameters 512, and neuron target locations 514 are shared across the sub-time steps of a time step and neuron membrane potentials are not logged. In a core neural circuit 100 implementing the memory configuration 510, neuron membrane potentials are not stored. As a result, neurons of such a core neural circuit 100 may generate a spike each time an input signal is received on a connected axon without a membrane potential being compared to a threshold.

In view of the memory configurations 500 to 510 described herein from 4 It should be understood that a core neural circuit 100 can be configured into any combination of N neuron states or N × T neuron states, N membrane potentials or N × T membrane potentials, N neuron parameters or N × T neuron parameters, and N neuron target locations or N × T neuron target locations, where N is the number of neurons of the core neural circuit 100 and T is a time-multiplexing factor (i.e., the total number of sub-time steps). In addition, the interconnection network or synaptic crossbar 110 b stores in each of the memory configurations 500 to 510 of 4 Synapse weights shared by the electronic neurons 11 of the neural core circuit 100 over the T partial time steps. Furthermore, the neural core circuit 100 can be of memory configurations 500 to 510 from 4 contain a memory for buffering axons, where each axon belongs to a partitioned or T-based organized axon buffer.

The 5A to 5C illustrate the capabilities of a multiplexed neurosynaptic core module 610 according to one embodiment. Optionally, the multiplexed neurosynaptic core module may be implemented in conjunction with features from any other embodiment listed herein, e.g., those described with reference to the other figures. Of course, such multiplexed neurosynaptic core module 610 and others set forth herein may, however, be used in various applications and/or implementations that are not necessarily expressly described in the illustrative embodiments listed herein. Furthermore, the multiplexed neurosynaptic core module 610 set forth herein may be used in any desired environment.

With reference to 5A Four neurosynaptic core modules 10 (10a, 10b, 10c and 10d) are now shown operating independently of each other in a non-multiplexed manner. In one embodiment, the four neurosynaptic core modules 10 may all be on the same chip, such as one associated with 2 described chip structure 70. It is also shown that each of the cores 10 contains a plurality of axons 15. In particular, the core 10a contains the axons 15a, the core 10b contains the axons 15b, the core 10c contains the axons 15c and the core 10d contains the axons 15d. It is also shown that each of the cores 10 contains a plurality of neurons 11. In particular, the core 10a contains the neurons 11a, the core 10b contains the neurons 11b, the core 10c contains the neurons 11c and the core 10d contains the neurons 11d. It is also shown that each axon 15 of 5A is connected to an independent axon buffer 605 (e.g. axon buffers 605a, 605b, 605c,... 605n) such that each core 10 contains the same number of axon buffers 605 as axons 15.

As in 5A , the synaptic crossbars 12a through 12d of the cores 10a through 10d were each configured in the same manner. In other words, the respective synapses of the cores 10a through 10d were configured such that the matrix W and the elements W _ij of the matrix W are the same for each of the cores 10a through 10d. Accordingly, a spike event received for any axon of the core 10a will cause the core 10a to output the spike event that would be output by any of the cores 10b through 10d if one of the corresponding axons of any of the cores 10b through 10d received the spike event.

With reference to 5B , a multiplexed neurosynaptic core module (or "core") 610 is now illustrated in accordance with one embodiment. The multiplexed core 610 includes a plurality of electronic axons 615 connected to a plurality of electronic neurons 611. Each of the axons 615 may be selectively connected to one or more of the neurons 611 via synapses of a synaptic crossbar 612 of the multiplexed core 610. The synaptic crossbar 612 of the multiplexed core 610 is also shown to be configured in the same manner as the synaptic crossbars 12a-12d of the cores 10a-10d of 5A . In other words, the respective synapses of the multiplexed core 610 have been configured such that the matrix W and the elements W _ij of the matrix W are the same for each of the cores 10a to 10d.

As in 5B As shown, a single axon buffer 605 can also store the previously stored four corresponding axon buffers 605 of 5A For example, the axon buffer 605a of the multiplexed core 610 stores the firing events received from the four other axon buffers 605a of the cores 10a to 10d of 5A Similarly, the axon buffer 605b of the multiplexed core 610 stores the firing events that are generated by the four other axon buffers 605b of the cores 10a to 10d of 5A would be stored, etc. With respect to a particular axon 615, the axon buffer 605 may be configured/read in a manner to interleave the firing events of the various sub-time steps of a given time step.

With reference to 5B For example, it has been shown that the firing events cached in axon buffers 605 have been identified as belonging to one of four sub-time steps (i.e., sub-time step 0, sub-time step 1, sub-time step 2, or sub-time step 3) of four different time steps (i.e., each of the buffers 605 is four units wide, one for each time step). During operation of the multiplexed core 610, operations may be performed on a first event in axon buffer 605a associated with sub-time step 0, then operations may be performed on a first event in axon buffer 605a associated with sub-time step 1, then operations may be performed on a first event in axon buffer 605a associated with sub-time step 2, then operations may be performed on a first event in axon buffer 605a associated with sub-time step 3, and then operations may be performed on a first event in the axon buffer 605a, which (after shifting) belongs to the sub-time step 0 of another time step, operations are carried out, etc.

As through 5C , a memory 650 may include the axon buffers 605 associated with each of the axons 615 of the multiplexed core 610. The memory 650 may be substantially identical to the memory 110a previously described in connection with 3 A width of the memory 650 may depend on the size of the core for which the memory 650 stores data. In one embodiment, the memory 650 is 256 bits wide so that 256 axons of the multiplexed core 610 may be buffered. The number of time steps (Δ)/sub-time steps for which the memory 650 stores data may depend on a height of the memory 650. For example, the memory 650 has a height of (T x max(Δ)) bits, where Δ is a number of time steps and T is a time multiplexing factor. As shown, the memory 650 buffers T sub-time steps for each of Δ time steps. Accordingly, each row of the memory 650 is associated with a single sub-time step, and each 1-bit wide column of the memory 650 is associated with a single axon. In this way, the memory 650 may include an axon buffer divided into T x max(Δ) rows, where max(Δ) is a maximum number of time steps.

Thus, for a given size of memory 650, T and max(Δ) are directly related. For example, a memory 650 with a depth or height of 128 rows can be configured such that T = 64 and max(Δ) = 2; T = 32 and max(Δ) = 4; T = 16 and max(Δ) = 8; T = 8 and max(Δ) = 16; T = 4 and max(Δ) = 32; T = 2 and max(Δ) = 64; or T = 1 and max(Δ) = 128.

In one embodiment, the multiplexed neurosynaptic core 610 may function in the following manner. At each of T sub-time steps (from sub-time step 0 to sub-time step T-1), each axon i _t is synchronously checked to determine if the axon has a spike that needs to be transmitted. If the axon has a spike that needs to be transmitted, for each neuron j _{t ,} updating a state of the neuron depending on the synapse weight s _ij . After each axon is checked to determine if the axons have spikes to be transmitted, for each neuron j _{t ,} calculating its new neuron state depending on its previous state, parameters, and input signals; and then checking if the neuron has generated a spike. When a particular neuron has generated a spike, finding the target location of the neuron, generating a spike event packet addressed to the target location, transmitting the spike event packet to the neurosynaptic network, and resetting the state of the neuron j _t . Additionally, the multiplexed neurosynaptic core 610 may operate asynchronously to receive spike event packets from the neurosynaptic network and update axon buffers.

In another embodiment, the multiplexed neurosynaptic core 610 may operate in the following manner. In each of T sub-time steps (from sub-time step 0 to sub-time step T-1), for each neuron j, synchronously read a state of neuron j, neuron parameters of neuron j, and a target location of neuron j. Next, add the parallel sum of synaptic inputs (from axons connected to the neuron) to the previous state to determine a new neuron state. If no is the previous state, n ₁ is the new neuron state, g is the axon type identifier (axon_type_id), A is the axon buffer, k is the number of axon types, and w is the weight associated with axon type k at neuron j, which may be calculated as $${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE112017000855B4\_0009.png,DE112017000855B4\_0010.png"\; state="\{\{state\}\}">n</figure-callout>}}_1={\mathrm{<figure-callout\; id="0"\; label="n"\; filenames="DE112017000855B4\_0007.png,DE112017000855B4\_0009.png"\; state="\{\{state\}\}">n</figure-callout>}}_0+{\displaystyle \sum _k\left(W_{jk}{\displaystyle \sum {}_{i=0}^{size\left(A\right)}{A}_i\times s_{ij}\times \left(G_j==k\right)}\right)}.$$

Next, it is checked whether the new neuron state triggers a spike. If the new neuron state triggers a spike, find the target location of the neuron, generate a spike event packet addressed to the target location, transmit the spike event packet to the neurosynaptic network, and reset the state of neuron j. In such an embodiment, the multiplexed neurosynaptic core 610 may operate asynchronously to receive spike event packets from the neurosynaptic network and update axon buffers.

By sharing one or more neuron attributes or parameters, networks of neurons and axons that are repeatedly found on a neurosynaptic chip can reside on a smaller number of cores on the chip. As a result, a given collection of neurosynaptic computations can require less physical space on a neurosynaptic chip and/or less power than non-multiplexed cores.

To achieve faster operation of neurosynaptic core circuits, updating processes of neurons can be parallelized, for example by special multipliers. The axon buffers can be used due to timestamps and/or time delays.

By multiplexing the neurosynaptic cores of a chip, a chip may be able to walk the line between mobility and scalability, achieving both high area utilization and energy efficiency, and constantly balancing the two. In addition, multiplexed neurosynaptic cores provide the ability to mix and match space-invariant and space-variant cores in a homogeneous architecture, and allow a given chip to be optimized for a given power budget without wasting dynamic power when no work needs to be done. However, if the metric for optimization is speed of operation (throughput, latency, etc.), the chip can be optimized for the necessary speed with minimal resource allocation or energy consumption (assuming the specified metric of speed is available in a given architecture). For a given application, the chip can also be optimized for minimal resource allocation (if multiple applications are running side by side on the same chip). In addition, such optimization operations can be performed during the reconfiguration phase of the chip (static optimization/reconfiguration) or by taking advantage of partial reconfiguration capabilities during the operational phase (dynamic optimization/reconfiguration). These concepts are applicable not only to chip-level optimization operations, but also to system-wide optimization operations.

Accordingly, in some embodiments, a neurosynaptic network may include a plurality of multiplexed cores 610. Additionally, not all of the multiplexed cores 610 may be multiplexed according to the same time-division multiplexing factor. For example, a first multiplexed core 610 may be multiplexed according to a first time-division multiplexing factor (T), wherein neuron parameters, neuron target locations, and/or neuron membrane potentials of the first multiplexed core 610 are shared across T sub-time steps of a time step. Additionally, one or more of the memories storing neuron parameters, neuron target locations, and neuron membrane potentials of the first multiplexed core 610 may be divided into T partitions, wherein each of the T partitions is associated with a corresponding one of T sub-time steps of the time step. Furthermore, a second multiplexed core 610 may be multiplexed according to a second time multiplexing factor (U), wherein neuron parameters, neuron target locations, and/or neuron membrane potentials of the second multiplexed core 610 may be shared across U sub-time steps of the time step. Furthermore, one or more of the memories storing neuron parameters, neuron target locations, and/or neuron membrane potentials of the second multiplexed core 610 may be divided into U partitions, wherein each of the U partitions is associated with a corresponding one of U sub-time steps of the time step. Finally, T may be equal to, greater than, or less than U.

For example, a first multiplexed core 610 may be multiplexed at a time division multiplexing factor of 4 (T=4). Accordingly, synapse weights, neuron parameters, and neuron target locations may be shared across the 4 sub-time steps of each time step, but a memory storing neuron membrane potentials for the first multiplexed core 610 may be divided into 4 partitions, each of the 4 partitions associated with a corresponding one of 4 sub-time steps of each time step. Connected to the first multiplexed core 610 is a second multiplexed core 610 that is multiplexed at a time division multiplexing factor of 8 (U=8). For the second multiplexed core 610, synapse weights, neuron parameters, and neuron target locations may be shared across the 8 sub-time steps of each time step, however, a memory storing neuron membrane potentials for the second multiplexed core 610 may be divided into 8 partitions, with each of the 8 partitions associated with a corresponding one of 8 sub-time steps of each time step. Of course, both the first multiplexed core 610 and the second multiplexed core may be multiplexed at any time multiplexing factor (e.g., 1, 2, 4, 8, 16, 32, 64, etc.).

Firing events or spike events between a first core 610 multiplexed at a first time division multiplexing factor and a second core 610 multiplexed at a second time division multiplexing factor, the second being different from the first time division multiplexing factor, can be bridged by assigning spatially distributed input signals to partial time steps.

In particular, a spike event may be forwarded between multiplexed cores by generating a packet for the spike event in a first multiplexed neural core multiplexed into T sub-time steps of a time step. The packet also contains at least an address field of the neural core, the time step, an axon address and a time scale and/or an offset. The first multiplexed neural core then transmits the spike event packet so that the spike event is received by the second neural core. The second neural core may be at a different time multiplexing factor than the first multiplexed neural core can be multiplexed. For example, the second neural core can be multiplexed by U sub-time steps for each of the time steps, where U is greater or less than T.

In one embodiment, the at least one address field of the neural core packet may comprise a field (dx + dx _t ) and/or a field (dy + dy _t ). For example, the at least one address field of the neural core packet may be formatted to include (dx+dx _t , dy+dy _t ). Optionally, d _xt and d _yt are each ceil(log ₂ N) bits. Additionally, dx _t and dy _t may each be programmed per core per sub-time step. In various embodiments, the address fields dx and dy provide offsets in the X-coordinate and Y-coordinate directions of a neural network, respectively. Optionally, a packet may be forwarded first in the X-dimension and then in the Y-dimension. Additionally, the axon address included in the packet may include an address of the electronic axon in the target neural core to which the spike must be delivered.

In one embodiment, the packet includes the time scale and not the offset. The time scale may be represented by a constant F, where F is the time division multiplexing factor scale of the neural core operating at a lower time division multiplexing factor. The time scale (F) may be used when a spike event is communicated from a neural core operating at a higher time division multiplexing factor (a faster core) to a neural core operating at a lower time division multiplexing factor (a slower core). If the time scale (F) is included in the packet, no offset may be included in the packet. For example, if the spike event packet is communicated from a multiplexed core with T = 8 to a multiplexed core with T = 4, then F = 4 and the offset = 0 or not included.

Additionally, the dx _t and dy _t bits may be used when a spike event is transmitted from a core operating at a higher time division multiplex factor (a faster core) to a core operating at a lower time division multiplex factor (a slower core), and the dx _t and dy _t bits may not be included in a packet transmitted from a slower core to a faster core.

In another embodiment, the packet includes the offset and not the time scale. The offset may be represented by a constant C, where C is an offset that maps spike events to a fractional time step of a faster core. Thus, the offset (C) may be used when a spike event is communicated from a neural core operating at a lower time division multiplex factor (a slower core) to a neural core operating at a higher time division multiplex factor (a faster core). Additionally, when C is included in the packet, the time scale constant (F) may be equal to 0 or not included in the packet. In this way, C and F are constants that can be used to define a fractional time step for communicating a spike event when the spike event is transmitted between cores with different time division multiplex factors.

For example, if a first multiplexed neural core is multiplexed by T sub-time steps for each time step and a second multiplexed neural core is multiplexed by U sub-time steps for each time step and T is less than U, the packet transmitted from the slower core to the faster core will contain the offset (C) to associate transmission of the spike event with an appropriate sub-time step of the faster core.

In a particular embodiment, the spike event packet may be formatted as (dx+dx _t , dy+dy _t , C + (t % F), Δ, axon_address), where % is the modulus operator and Δ is the time step. Accordingly, this packet may be delivered to a neural core (dx+dx _t , dy+dy _t ) after a delay of Δ in the sub-time step C + (t % F) to an axon at axon_address.

The 6A to 6B illustrate the propagation of spike events between neurosynaptic nuclei according to one embodiment. Optionally, the propagation of spike events may be implemented in conjunction with features of any other embodiment listed herein, e.g., those described with reference to the other figures. It should be understood, however, that the systems and methods for propagating spike events may be used in various applications and/or in implementations that are not necessarily expressly described in the illustrative embodiments listed herein. Furthermore, the systems and methods for propagating spike events set forth herein may be used in any desired environment.

According to 6A core neural circuits 702, 704, 706 and 708 are each operated with a time multiplexing factor of 1, so that each of the cores 702, 704, 706 and 708 is operated once for each time step (Δ). The cores 702, 704, 706 and 708 can be conventional, non-multiplexed neurosynaptic cores. An output signal from the neurons from each of the cores 702, 704, 706 and 708 is configured to result in spike events (i.e., firing events) that are transmitted to a multiplexed neural core circuit 710. As in 6A As shown, the multiplexed neural core 710 is operated with a time multiplexing factor of 4, so that it is operated four times in each time step (Δ).

Accordingly, to enable data exchange between cores 702, 704, 706, and 708 and multiplexed core 710, each of cores 702, 704, 706, and 708 has been assigned a different C value. Each C value is a sub-time step offset that maps a received spike event to a sub-time step of a faster core (i.e., core 710). Accordingly, C = 0 for core 702, and spike events received by core 702 are mapped to the first sub-time step of multiplexed core 710; C = 1 for core 704, and spike events received by core 704 are mapped to the second sub-time step of multiplexed core 710; C = 2 for core 706, and spike events received from core 706 are mapped to the third sub-time step of multiplexed core 710; and C = 3 for core 708, and spike events received from core 708 are mapped to the fourth sub-time step of multiplexed core 710. In both 6A and 6B is dx _t = 0 and dy _t = 0. Forwarding of packets can be managed by event routers located between the cores.

According to 6B Now, in another example, multiplexed neural core circuits 752 and 754 are each operated with a time multiplexing factor of 2, such that each of the cores 752 and 754 is operated twice in each time step (Δ). The neurons of the cores 752 and 754 are configured to transmit spike events (ie, firing events) to a multiplexed neural core circuit 760. As in 6B As shown, the multiplexed neural core 760 is operated with a time multiplexing factor of 4, so that it is operated four times in each time step (Δ).

Accordingly, to enable data exchange of the multiplexed cores 752 and 754 with the multiplexed core 760, each of the cores 752 and 754 has been assigned a different C value. Specifically, C = 0 for the core 752, which results in the spike events received by the core 752 being mapped to the first two sub-time steps (t = 0, t = 1) of the multiplexed core 760; and C = 2 for the core 754, which results in the spike events received by the core 754 being mapped to the third and fourth sub-time steps (t = 2, t = 3) of the multiplexed core 760. As a result, although the multiplexed cores 752 and 754 may perform computations during the same period of two sub-time steps of each time step, the spikes transmitted by the cores 752 and 754 are buffered and input to the multiplexed core 760 in an orderly and collision-free manner.

The 7A to 7B illustrate the propagation of spike events between neurosynaptic nuclei according to one embodiment. Optionally, the propagation of spike events may be implemented in conjunction with features of any other embodiment listed herein, e.g., those described with reference to the other figures. Of course, the systems and methods for propagating spike events may be used in various applications and/or in implementations that are not necessarily explicitly described in the illustrative embodiments listed herein. Furthermore, the systems and methods for propagating spike events set forth herein may be used in any desired environment.

According to 7A a multiplexed neural core circuit 810 is operated at a time division multiplexing factor of 4, such that it is operated four times per time step (Δ). As shown, the multiplexed core 810 transmits spike events to each of the neural core circuits 802, 804, 806, and 808, each of which is operated at a time division multiplexing factor of 1. In other words, each of the cores 802, 804, 806, and 808 is operated once in each time step (Δ).

Accordingly, to enable reliable transmission of spike events from the multiplexed core 810 to the cores 802, 804, 806 and 808, the packets from the multiplexed core 810 are configured to contain a C value of 0 and an F value of 1. In other words, the time scale of such packets is 1 (F = 1), which reflects the time multiplexing factor of the slower cores 802 to 808, and C = 0 because the multiplexed core 810 is faster than the slower cores 802 to 808. Moreover, the spike event packets from the multiplexed core 810 to the cores 802 to 808 are shown to contain a field dx _t in the address field of the packets from the neural core. Specifically, dx _t = 0 for the spike event packet from multiplexed core 810 to core 802, indicating that it is mapped to the first sub-time step of each Δ, dx _t = 1 for the spike event packet from multiplexed core 810 to core 804, indicating that it is mapped to the second sub-time step of each Δ, dx _t = 2 for the spike event packet from multiplexed core 810 to core 806, indicating that it is mapped to the third sub-time step of each Δ , and dx _t = 4 on the spike event packet from multiplexed core 810 to core 808, indicating that it is mapped to the fourth sub-time step of each Δ.

Optionally, dy _t can be used instead of or in addition to dx _t to represent a spatial distribution. Each of the receiving cores can be encoded in pairs (dx _t , dy _t ) in each of the sub-time steps. The values of dx _t and dy _t can be set by a programmer, for example. The set {(dx _t , dy _t ), t = 1, 2, ... , T} can be a neighborhood.

According to 7B a multiplexed neural core circuit 860 is now operated at a time multiplexing factor of 4, such that it is operated four times per time step (Δ). As shown, the multiplexed core 860 transmits spike events to each of the neural core circuits 852 and 854, each of which is operated at a time multiplexing factor of 2. In other words, each of the cores 852 and 854 is operated twice in each time step (Δ).

Accordingly, to enable reliable transmission of spike events from the multiplexed core 860 to the cores 852 and 854, the packets from the multiplexed core 860 are configured to contain a C value of 0 (C = 0) and an F value of 2 (F = 2). In other words, the time scale of such packets is 2 (F = 2), which reflects the time multiplexing factor of the slower cores 852 and 854 receiving the packets, and C = 0 because the multiplexed core 860 is faster than the slower cores 852 and 854. Moreover, the spike event packets from the multiplexed core 860 to the multiplexed cores 852 and 854 are shown to contain a dx _t field in the address field of the neural core packets. In particular, dx _t = 0 for the spike event packet from multiplexed core 860 to multiplexed core 852, indicating that it is mapped to the first sub-time step of each Δ, and dx _t = 1 for the spike event packet from multiplexed core 860 to multiplexed core 854, indicating that it is mapped to the second sub-time step of each Δ.

In one embodiment, a multiplexed core neural circuit may comprise, at an integer multiplexing factor T greater than zero, T sets of electronic neurons, T sets of electronic axons, each of the T sets of electronic axons corresponding to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons.

In one embodiment, the synaptic connection network may also be shared across the T sets of electronic neurons. In another embodiment, a plurality of neuron parameters may be shared across the T sets of electronic neurons. In yet another embodiment, a plurality of neuron target locations may be shared across the T sets of electronic neurons. In yet another embodiment, a neuron state may be shared across the T sets of electronic neurons.

Additionally, in one embodiment, operation of the multiplexed core neural circuit may be described in terms of a plurality of discrete time steps, and in a single discrete time step, each set of the T sets of electronic axons may be connected to its corresponding set of electronic neurons via the synaptic interconnection network. In another embodiment, each of the plurality of discrete time steps may be divided into T sub-time steps, wherein each set of the T sets of electronic axons and its corresponding set of electronic neurons may be assigned to one of the T sub-time steps, and each set of the T sets of electronic axons may be connected to its corresponding set of electronic neurons in its assigned one of the T sub-time steps via the synaptic interconnection network.

In one embodiment, the multiplexed core neural circuitry may further include two different memory banks, where the two different memory banks may include a first memory bank comprising the synaptic connection network, a plurality of neuron parameters, a plurality of neuron target locations, and a neuron state for all electronic neurons in the T sets of electronic neurons, and a second memory bank comprising an electronic axon buffer. In another embodiment, the electronic axon buffer may be divided into T rows × max(Δ) columns, where max(Δ) is a number of time delays.

In one embodiment, a neurosynaptic system may further comprise a neurosynaptic chip, a single-core neurosynaptic module as a component on a chip, or a multi-core neurosynaptic module as a component on a chip containing a plurality of multiplexed core neural circuits interconnected via an on-chip network, each of the plurality of multiplexed core neural circuits comprising, at an integer multiplexing factor T greater than zero, T sets of electronic neurons, T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons.

In one embodiment, the neurosynaptic chip, the single-core neurosynaptic module, or the multi-core neurosynaptic module may also be interconnected via an off-chip interconnection network. In another embodiment, the on-chip network may be event-driven. In another embodiment, the off-chip network may be event-driven. In yet another embodiment, one or more of the plurality of multiplexed core neural circuits may have an integer multiplexing factor that is different from the other multiplexed core neural circuits of the plurality of core neural circuits.

Furthermore, in one embodiment, a first set of the plurality of multiplexed neural core circuits may have a first integer multiplexing factor T1, and the first set may be connected to a second set of multiplexed neural core circuits having a second integer multiplexing factor T2 that is different from the first integer multiplexing factor T1. In another embodiment, messages transmitted between the cores may include spike packets that include a relative address of a target core, a time delay of an electronic axon, an address of a set of electronic axons, an axon address, and data encoding a mapping between the integer multiplexing factor Ts of source cores and the integer multiplexing factor Td of target cores.

8th shows a typical hardware environment for configuring neurosynaptic nuclei according to one embodiment. Such a figure illustrates a typical hardware configuration of a workstation having a central processing unit 210, for example a microprocessor, and a number of other units interconnected via a system bus 212.

In the 8th includes a random access memory (RAM) 214, a read only memory (ROM) 216, an I/O adapter 218 for connecting peripheral devices such as disk storage devices 220 to the bus 212, a user interface adapter 222 for connecting a keyboard 224, a mouse 226, a speaker 228, a microphone 232 and/or other user interface devices such as a touch screen and a digital camera (not shown) to the bus 212, a data communication adapter 234 for connecting the workstation to a data communication network 235 (e.g., a data processing network), and a display adapter 236 for connecting the bus 212 to a display device 238.

The workstation may contain an operating system, e.g. a Microsoft Windows® operating system (OS), a MAC operating system, a UNIX operating system, etc. It will be appreciated that a preferred embodiment may be implemented on platforms and operating systems other than those mentioned. A preferred embodiment may be written using the XML language, C and/or C++ or other programming languages, together with an object-oriented programming methodology. Object oriented programming (OOP) may be used, which is increasingly used for developing complex applications.

The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer-readable storage medium(s) having stored thereon computer-readable program instructions for causing a processor to carry out aspects of the present invention.

The computer-readable storage medium may be a physical device that can retain and store instructions for use by an instruction-executing device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. For a non-exhaustive list of more specific examples of the computer-readable storage medium, see Computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch cards or raised structures in a groove on which instructions are stored, and any suitable combination thereof. A computer readable storage medium, as used herein, is not intended to be construed as ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., pulses of light carried through a fiber optic cable), or electrical signals carried through a wire.

Computer readable program instructions described herein may be downloaded from a computer readable storage medium to respective computing/processing units or to an external computer or storage unit over a network such as the Internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routers, firewalls, switching units, gateway computers, and/or edge servers. A network adapter card or network interface in each computing/processing unit receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing unit.

Computer readable program instructions for carrying out operations of the present invention may be assembly language instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, or the like, as well as traditional procedural programming languages such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, over the Internet using an Internet service provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowcharts and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It is noted that each block of the flowcharts and/or block diagrams, as well as combinations of blocks in the flowcharts and/or block diagrams, may be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a means for implementing the functions/steps defined in the block(s) of flowcharts and/or block diagrams. These computer readable program instructions may also be stored on a computer readable storage medium capable of controlling a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium on which instructions are stored is a Product of manufacture, including instructions that implement aspects of the function/step specified in the block(s) of the flowchart and/or block diagrams or charts.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of process steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-executable process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions/steps set forth in the flowchart and/or block diagram block(s).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products in accordance with various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions comprising one or more executable instructions for performing the particular logical function(s). In some alternative implementations, the functions indicated in the block may occur in a different order than shown in the figures. For example, two blocks shown in sequence may actually execute substantially simultaneously, or the blocks may sometimes execute in reverse order depending on the corresponding functionality. It should also be noted that each block of the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, may be implemented by special purpose hardware-based systems that perform the specified functions or steps, or execute combinations of special purpose hardware and computer instructions.

Moreover, according to various embodiments, a system may include a processor and logic integrated and/or executable by the processor, the logic configured to perform one or more of the process steps set forth herein. Integrated means that logic is embedded in the processor in the form of hardware logic, for example, an application specific integrated circuit (ASIC), an FPGA, etc. Processor executable means that the logic may be hardware logic, software logic such as firmware, a portion of an operating system, a portion of an application program, etc., or a combination of hardware and software logic that is accessible to the processor and configured to cause the processor to perform functionality when executed by the processor. Software logic may be stored in local and/or remote memory of any type of memory known in the art. Any processor known in the art may be used, e.g. a software processor module and/or a hardware processor such as an ASIC, an FPGA, a central processing unit (CPU), an integrated circuit (IC), a graphics processing unit (GPU), etc.

It will be appreciated that the various features of the foregoing systems and/or methodologies may be combined in any manner, producing a variety of combinations from the descriptions set forth above.

Furthermore, it is to be understood that embodiments of the present invention may be provided in the form of a service provided on behalf of a customer to provide a service on demand.

While various embodiments have been described above, it is to be understood that they have been presented by way of example only and not limitation. Accordingly, the breadth and scope of a preferred embodiment should not be limited by any of the exemplary embodiments described above, but should be defined only in accordance with the following claims and their equivalents.

Claims (23)

A multiplexed neural core circuit comprising: T sets of electronic neurons, where T is an integer multiplexing factor and is equal to four; T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons; and a synaptic connection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, wherein the interconnection network connects each of the T sets of electronic axons to its corresponding set of electronic neurons; and a set of axon buffers each divided into T partitions, each of the T partitions associated with one of T sub-time steps of a time step, and each of the T sub-time steps comprising: a common set of neuron parameters, the neuron parameters comprising a spike threshold, a leak rate, and axon type weights; a common set of neuron target locations indicative of a target axon for each of the electronic neurons, and a different set of neuron membrane potentials than the other sub-time steps, each set of neuron membrane potentials having a membrane potential V that increases when receiving inputs from source excitatory neurons and that decreases when receiving inputs from source inhibitory neurons, wherein the multiplexed core neural circuit is time multiplexed for the T sub-time steps of the time step, with synaptic weights and the neuron parameters being shared across the T sub-time steps, and wherein each of the T sub-time steps is associated with a different set of neuron target locations and a different set of neuron membrane potentials than the other sub-time steps, such that the multiplexed core neural circuit operates as four cores during a time step, each of the four cores having its own unique neuron target locations and neuron membrane potentials. Multiplexed neural core circuit according to Claim 1 , where the synaptic connection network is shared by the T sets of electronic neurons and a plurality of neuron target sites are shared by the T sets of electronic neurons. Multiplexed neural core circuit according to Claim 1 , where the neuron membrane potentials each have a single or multi-bit state, and each of the T sub-time steps indicates when a firing event encapsulated in a spike event packet is generated. Multiplexed neural core circuit according to Claim 1 , where a neuron state is shared by the T sets of electronic neurons, the synaptic connection network is shared by the T sets of electronic neurons, the set of neuron parameters has weights of the axon types Syn0 , Syn1 and Syn2 , and a plurality of neuron target locations are shared by the T sets of electronic neurons. Multiplexed neural core circuit according to Claim 1 , wherein operation of the multiplexed core neural circuit is described in terms of a plurality of discrete time steps, and in a single discrete time step, each set of the T sets of electronic axons is connected to its corresponding set of electronic neurons via the synaptic connection network. Multiplexed neural core circuit according to Claim 5 further comprising: dividing each of the plurality of discrete time steps into T sub-time steps, assigning one of the T sub-time steps to each set of the T sets of electronic axons and its corresponding set of electronic neurons, and connecting each set of the T sets of electronic axons via the synaptic connection network to its corresponding set of electronic neurons in its assigned one of the T sub-time steps. Multiplexed neural core circuit according to Claim 1 , further comprising two different memory banks, the two different memory banks comprising: a first memory bank comprising the synaptic connection network, the common set of neuron parameters, the common set of neuron target locations, and a neuron state for all electronic neurons in the T sets of electronic neurons, and a second memory bank comprising the set of axon buffers. Multiplexed neural core circuit according to Claim 1 , where the set of axon buffers is divided into T rows × max(Δ) columns, where max(Δ) is a number of time delays. Multiplexed neural core circuit according to Claim 8 , further comprising a first memory bank comprising the synaptic connection network, the common set of neuron parameters, the common set of neuron target locations and the neuron state for all electronic neurons in the T sets of electronic neurons, and a second memory bank comprising the set of axon buffers; wherein the first memory bank is stored using a first memory section comprising the synaptic connection network and a second memory section comprising the common set of neuron parameters, the common set of neuron target locations, and the neuron status for all electronic neurons within the T sets of electronic neurons, wherein the first memory section is different from or equal to the second memory section. A computer-implemented method for multiplexing a core neural circuit, comprising: configuring, using a hardware processor, T sets of electronic neurons, where T is an integer multiplexing factor T having a value of four; configuring, using a hardware processor, T sets of electronic neurons, wherein each of the sets of electronic axons corresponds to one of the T sets of electronic neurons; configuring, using the hardware processor, a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each set of the T sets of electronic axons to its corresponding set of electronic neurons; and configuring, using the hardware processor, a set of axon buffers each divided into T partitions, each of the T partitions associated with one of T sub-time steps of a time step, and each of the T sub-time steps having: a common set of neuron parameters, the neuron parameters comprising a spike threshold, a leak rate, and axon type weights; a common set of neuron target locations specifying a target axon for each of the electronic neurons; and a different set of neuron membrane potentials than the other sub-time steps, each set of neuron membrane potentials having a membrane potential V that increases when receiving inputs from source excitatory neurons and that decreases when receiving inputs from source inhibitory neurons; wherein the multiplexed core neural circuit is time-multiplexed for the T sub-time steps of the time step, with synaptic weights and the neuron parameters being shared across the T sub-time steps; and wherein each of the T sub-time steps is associated with a different set of neuron target locations and a different set of neuron membrane potentials than the other sub-time steps, such that the multiplexed core neural circuit operates as four cores during a time step, each of the four cores having its own unique neuron target locations and neuron membrane potentials. A computer-implemented method according to Claim 10 , where the synaptic connection network is shared by the T sets of electronic neurons. A computer-implemented method according to Claim 10 , where a plurality of neuron parameters are shared among the T sets of electronic neurons. A computer-implemented method according to Claim 10 , where a plurality of neuron target locations are shared among the T sets of electronic neurons. A computer-implemented method according to Claim 10 , where a neuron state is shared by the T sets of electronic neurons. A computer-implemented method according to Claim 10 , wherein operation of the multiplexed core neural circuit is described in terms of a plurality of discrete time steps, and in a single discrete time step, each set of the T sets of electronic axons is connected to its corresponding set of electronic neurons via the synaptic connection network. A computer-implemented method according to Claim 15 further comprising: dividing each of the plurality of discrete time steps into T sub-time steps, assigning each set of the T sets of electronic axons and its corresponding set of electronic neurons to one of the T sub-time steps, and connecting each set of the T sets of electronic axons via the synaptic connection network to its corresponding set of electronic neurons in its assigned one of the T sub-time steps. A computer-implemented method according to Claim 10 , further comprising storing two different memory banks, the two different memory banks comprising: a first memory bank comprising the synaptic connection network, the common set of neuron parameters, the common set of neuron target locations and a neuron state for all electronic neurons in the T sets of electronic neurons, and a second memory bank containing the set of axon buffers. A neurosynaptic system comprising: a neurosynaptic chip, a single-core neurosynaptic component-on-chip module, or a multi-core neurosynaptic component-on-chip module comprising a plurality of multiplexed core neural circuits interconnected via an on-chip network, each of the plurality of multiplexed core neural circuits comprising: T sets of electronic neurons, where T is an integer multiplexing factor greater than four; T sets of electronic axons, each set of the T sets of electronic axons corresponding to one of the T sets of electronic neurons; and a synaptic interconnection network comprising a plurality of electronic synapses each connecting a single electronic axon to a single electronic neuron, the interconnection network connecting each of the T sets of electronic axons to its corresponding set of electronic neurons; and a set of axon buffers each divided into T partitions, each of the T partitions associated with one of T sub-time steps of a time step, and each of the T sub-time steps comprising: a common set of neuron parameters, the neuron parameters comprising a spike threshold, a leak rate, and axon type weights; a common set of neuron target locations indicative of a target axon for each of the electronic neurons; and a different set of neuron membrane potentials than the other sub-time steps, each set of neuron membrane potentials having a membrane potential V that increases when receiving inputs from source excitatory neurons and that decreases when receiving inputs from source inhibitory neurons, wherein the multiplexed core neural circuit is time multiplexed for the T sub-time steps of the time step, with synaptic weights and the neuron parameters being shared across the T sub-time steps, and wherein each of the T sub-time steps is associated with a different set of neuron target locations and a different set of neuron membrane potentials than the other sub-time steps, such that the multiplexed core neural circuit operates as four cores during a time step, each of the four cores having its own unique neuron target locations and neuron membrane potentials. Neurosynaptic system according to Claim 18 , wherein the neurosynaptic chip, the neurosynaptic single-core module or the neurosynaptic multi-core module are interconnected via a network located outside the chip. Neurosynaptic system according to Claim 18 , where the on-chip network is event-driven. Neurosynaptic system according to Claim 19 , where the off-chip network is event-driven. Neurosynaptic system according to Claim 18 wherein one or more of the plurality of multiplexed core neural circuits have an integer multiplexing factor that is different from the other multiplexed core neural circuits of the plurality of multiplexed core neural circuits. Neurosynaptic system according to Claim 22 , wherein messages transmitted between the nuclei comprise spike packets encoding a relative address of a target nucleus, a time delay in electronic axons, an address of a set of electronic axons, an axon address, and data encoding a mapping between the integer multiplexing factor Ts of source nuclei and the integer multiplexing factor Td of target nuclei.

Images