DE10322541A1 - Memory chip with integral address scrambling unit whereby the address can be scrambled in different ways according to the address control bits - Google Patents

Abstract

The memory chip has an integral address scrambling unit (22,23) which has address inputs for entering an address. The address scrambling unit is arranged and adapted such that the addresses can be scrambled differently dependent on the control bits. A memory cell field is provided and is connected to the output of the address scrambling unit. The scrambling unit may have several predefined scramblers for scrambling the addresses in different ways. Independent claims also cover a method of scrambling addresses.

Description

The The invention relates to a memory chip with an integrated address scrambler unit and a method for scrambling an address in an integrated Storage.

Want a physically defective memory cell of a memory cell array do you want to analyze or want to test certain patterns, which also be referred to as a scramble pattern in the memory cell array write, one must note that the actual arrangement of the memory cells in the memory chip does not match the idea of an ideal matrix. This explains firstly, that the memory chip is usually is not square. On the other hand, one tries to do as little space as possible to accommodate many memory cells and if possible slight delays to be able to address. This means in other words; that the logistics that are necessary to data write to or read from certain memory cells, a preferably clever allocation of addressing required.

Around nevertheless the physical position of an addressed memory cell to obtain it is necessary to use a special program or scrambling the address based on the address decoding. scrambling means that an address is converted in such a way that a defined memory cell is addressed. But that means that actually a different address on the address lines of the Memory module must be switched when you want to address logically.

Around the functionality to check a memory chip and ensure it is necessary to find critical terms the for the relevant memory modules are relevant. Take these conditions into account physical effects that may affect the function of the memory restrict or impair can. Such effects can z. B. unwanted electrical couplings between adjacent bit or word lines or between the memory cells, i.e. the capacitor unit cells, of a dynamic semiconductor memory or the stray magnetic fields on the trained as an exchange-coupled magnetic unit cells Memory cells of a ferromagnetic random access memory (MRAM) etc. his.

A important prerequisite for targeting such effects, is a suitable addressing of the corresponding areas, e.g. B. a memory cell in the memory cell array. The real one Location, for example the location of a memory cell in the memory cell array, So the physical address (x0, y0) and the x and y coordinate the row and column decoder in memory, i.e. the logical address (x, y) are usually not congruent. To be clear Establish mapping between logical and physical address to be able a function must be defined which is called a Scrambler is taken over. The address scrambling can often be done by a rather complex mathematical Operation can be represented in an external, i.e. outside of the test system located in the memory must be programmed. Because of the different design, the different ratio of chip area memory size etc. the memory chips differ in their scrambling.

So far, as in 1 is shown, the address scrambling outside the memory chip 20 with the help of a test system 10 with a virtual memory cell array 11 programmed. When the test is run, whereby the test system specifies the clock clk, the data d, the addresses adr and the control commands ctr, is in the memory cell field 21 of the memory chip 20 traveled a trajectory, e.g. B. in the form of a complete translation in the x direction and then in the y direction, or in the form of a diagonal, etc. At each step in the test process, the address scrambler 10 queried and output the corresponding physical coordinates.

The The problem here is that the programming of address scramblers is complex and often incorrect implementation of the correct one Address topology in a test. Mostly next to it the addresses also scrambled the data using a data scrambler Need to become, can the complex scrambler additionally some Limitations of the test system and the flexibility with the Limit programming.

Become different test systems are used, so the scrambler must be on can be programmed in different ways.

A The object of the invention is a memory chip with integrated Address scrambler unit and a method for scrambling an address specify in an integrated memory, where the complex Programming an external scrambler can be omitted and also a high degree of flexibility guaranteed in the way of scrambling the address or the data becomes.

The task is through a storage building Stone with integrated address scrambler unit with the features according to claim 1 and solved by a method for scrambling an address in an integrated memory with the features according to claim 10.

The memory chip according to the invention with integrated address scrambler unit has the following features on. The address scrambler unit has address inputs for creating an address and is designed and operable in such a way that by means of the address scrambler unit dependent the address of control bits can be scrambled in various ways. In addition, a memory cell array is provided that the address scrambler unit is connected downstream.

The inventive method for scrambling an address in an integrated memory following steps. With a control command one is in memory intended address scrambler unit caused from several possible Scramble patterns select a scramble pattern and scramble it to use. The address to be scrambled becomes the address scrambler unit supplied and according to the selected one Scramble pattern scrambled. Finally the scrambled Address supplied to a memory cell array provided in the memory.

advantageous Training and further developments of the invention result from the in the dependent claims Features.

In one embodiment of the memory chip according to the invention with an integrated address scrambler unit, this has several predefined scramblers which are designed and operable in such a way that they are dependent on the address can be scrambled differently for the control bits.

In a further embodiment of the memory chip according to the invention assigns one of the predefined scramblers a conversion element Convert a bit of the address and a multiplexer on which either the bit converted by the conversion element or not scrambled bit forwards.

In a further embodiment of the memory chip according to the invention another of the predefined scramblers has a further conversion element for converting an address bit of the address and a multiplexer on either the one converted by the other conversion element Address bit or that of one of the other predefined scramblers generates generated address bits. With the help of such a link several predefined scrambler, the number of possible scramble patterns can be increased, without the complexity the address scrambler unit integrated in the memory module considerably increases.

advantageously, the address scrambler unit can also have a programmable scrambler, this being designed and operable in such a way that it depends on the address of the control bits can be scrambled in different ways. With the help of such a programmable scrambler the flexibility increase while scrambling.

moreover it is advantageous if the programmable scrambler of the memory module according to the invention has several multiplexers, the input side with several of the Address inputs connected are. The programmable scrambler also has a conversion unit on which of certain bits of the address and those of the multiplexers delivered bits scrambled address bits generated, the control bits serve to control the multiplexers.

Furthermore the conversion element of the memory chip according to the invention can be an XOR gate have, which on the input side with a first and a second Address line is connected.

Prefers It is also proposed that the control bits in the memory module have a control connection can be specified externally. This means that the outside can at any time desired scramble pattern can be set.

The memory chip according to the invention can According to a further feature of the invention, be designed such that the address scrambler unit can be activated by means of an external signal is.

at one possible Further development of the method according to the invention for scrambling an address in an integrated memory the memory before scrambling the address into a test mode brought.

in the The following is the invention with several embodiments based on the following figures closer explained.

1 shows the circuitry of an external address scrambler with an integrated memory chip according to the prior art.

2 shows the basic structure of an integrated semiconductor memory device with an integrated address scrambler unit according to the invention in the form of a block diagram.

3 shows in the form of a block diagram a possible embodiment of an address scrambler unit integrated in the memory module.

4 shows a 2: 1 multiplexer, which is used for example in the 3 shown address scrambler unit can be used.

5 shows an embodiment of an address scrambler unit with two predefined scramblers, which correspond to the in 3 shown embodiment are connected.

6 shows a further possible embodiment of the address scrambler unit integrated in the memory module.

7 shows an example of the structure of a 4: 1 multiplexer.

Towards the detailed explanation 1 is omitted here and reference is made to the introduction to the description instead.

In 2 A memory module according to the invention is shown in the form of a block diagram. The memory chip 20 has a number of address inputs 20.2 to create an address adr, where the address inputs 20.2 internally with inputs 23.2 a scrambler decoder 23 are connected. The scrambler decoder 23 via a 4-bit wide line from a programmable scrambler or several predefined scramblers 22 controlled. For controlling the pre-programmable scrambler or the predefined scrambler 22 again the memory chip points 20 a control input 20.1 on which a control signal ctr can be applied. The control input 20.1 of the memory chip 20 No additional connection pin is required to control the programmable scrambler or the predetermined scrambler 22 , but can be an existing connection pin, via which, among other functions, the control of the address scrambler unit 22 . 23 can be done. The desired scramble pattern is selected from a series of several different possible scramble patterns via the control signal ctr and with the aid of the scrambler decoder 23 the address is scrambled accordingly. At the output of the scrambler decoder 23.1 the scrambled address is then available, which is then via an address decoder 24 on a conventional memory cell array 21 of the memory chip 20 to be led. If the address scrambler unit via the control signal ctr 22 . 23 is not activated, it means that the memory chip 20 is operated conventionally. This means that the address adr is unscrambled on the address decoder 24 performed, which then decodes and onto the memory cell array 21 leads.

In 3 is a possible embodiment of an address scrambler unit with N predefined scramblers 1 represented to N. An address A <m: 0>, which consists of a total of m + 1 bits, is fed to the address scrambler unit. Two bits of it, namely bit A <1> and bit A <0> are transferred to a first conversion unit SCRAM 1 performed, which calculates a scrambled bit SC1 <0> and on a first input of a multiplexer MUX 1 leads. To the second input of the MUX multiplexer 1 , which is designed as a 2: 1 multiplexer, bit A <0> is set. With the aid of a first control bit S1, it can now be selected whether the original address bit A <0> or the scrambled address bit SC1 <0> to the output of the multiplexer MUX 1 as the address output bit A <0 '>. With the help of the first predefined scrambler 1 the original address A <m: 0> is scrambled into the scrambled address A <m: 1,0 '> if the control bit S1 has been set. Otherwise the original address A <m: 0> is retained.

Depending on the application and need, several pre-defined scramblers can be integrated in the integrated memory chip 20 be provided. This is in 3 indicated by a further, N-th predefined scrambler N. In contrast to the first predefined scrambler 1 the further predefined scrambler N, as in 3 is shown by way of example using the conversion unit SCRAM N to scramble several bits of the address A <m: 0>, for example the bits A <4: 0>. Scrambled address bits SCN <3: 0> are then present at the output of the conversion unit SCRAM N and are passed to the multiplexer MUX N. With the help of the Nth control bit SN it can be determined whether the multiplexer MUX N either the scrambled address bits SCN <3: 0> or the address bits A <3: 1.0 '> as address output bits A <3'':0''> leads.

In 4 A possible embodiment of a 2: 1 multiplexer at the transistor level is shown. The MUX multiplexer 1 out 3 can be carried out in this way, for example. Port P corresponds to the control input of the MUX multiplexer 1 which is controlled with control bit S1.

In 5 is a more detailed illustration of a possible embodiment of the address scrambler unit from 3 shown. As the SCRAM conversion unit 1 For example, an XOR gate can be used, the two inputs of which are connected to the address lines A <0> and A <1>. At the output of the XOR gate SCRAM 1 the scrambled address bit SC1 <0> can then be attacked to the first input of the MUX multiplexer 1 to be led. The second input of the MUX multiplexer 1 however, is connected to the original address line A <0>. The output A <0 '> of the multiplexer MUX 1 is routed to the input of a 2: 1 multiplexer N.5, which is part of the multiplexer MUX N. The address lines A <0>, A <1>, A <2>, A <3> and A <4> are as in 5 is shown, led to four XOR gates N.1 to N.4, which together form the conversion unit SCRAM N. Their outputs SCN <0> to SCN <3> are routed to the inputs of the 2: 1 multiplexers N.5 - N.8. Address lines A <1>, A <2> and A <3> are also routed to the inputs of multiplexers N.6, N.7 and N.8. How out 5 can also be seen, depending on the control bits S1 and SN, the address bits A <0>, A <1>, A <2> and A <3> are scrambled, whereas the address bits A <4>, A <5> and A <6> in any case remain unscrambled.

In 6 Another embodiment of the address scrambler unit is shown. Here comes a freely programmable scrambler 3 for use. With the help of a conversion unit 3.6 the address bits A <m: 0> with those of the two multiplexers 3.1 and 3.2 as well as the downstream AND gates 3.3 and 3.4 and the OR gate 3.5 linked and as scrambled output bits A <m ': 0'> the in 2 shown address decoder 24 fed. The freely programmable scrambler can be operated via the two control bits S0 and S1 3 be programmed. This enables different scramble patterns to be generated, which can then be used to scramble the address adr in different ways.

The conversion unit 3.6 can for example be designed as an XOR gate. If in this case the bit at the output of the OR gate 3.5 on the logical state 1 is set in the conversion unit 3.6 all address bits A <m: 0> inverted.

Of course, the freely programmable scrambler 3 not on the in 6 limited embodiment shown as an example, but may well have other multiplexers and corresponding downstream logic elements. This allows the number of scramble patterns to be increased or adapted to the needs.

In 7 A possible embodiment of a 4: 1 multiplexer is shown. The control of the four m: 2 multiplexers 4.1 to 4.4 takes place via four control bits S0 to S4.

With in addition to the solution according to the invention Addresses also scrambled data with different scramble patterns become.

The previous description of the embodiments according to the present Invention serves only for illustrative purposes and not for the purpose the restriction the invention. Various changes are within the scope of the invention and modifications possible, without departing from the scope of the invention and its equivalents.

1

first predefined scrambler

N

Nth predefined scrambler

3

programmable scrambler

N.1 - N.4

conversion units

3.1

multiplexer

3.2

multiplexer

3.3

AND gate

3.4

AND gate

3.5

OR gate

3.6

conversion unit

4.1 - 4.4

m: 2 multiplexer

10

test system

11

virtual Memory cell array

20

memory chip

20.1

control connection

20.2

address inputs

21

physical Memory cell array

22

scrambler

23

Scramblerdecoder

24

address decoder

clk

clock

d

Data

adr

address

ctr

control signal

x, y

logical address

x0, y0

physical address

S0, S1, SN

control bits

A <m: 0> m + 1

 address lines or address bits

SCRAM1

conversion unit

MUX

multiplexer

A <0> - A <6>

address lines or address bits 1 to 6

SC <0>

Scramblerausgang

SCN <0>

output of the Nth scrambler

A0 ', A0' '

address bit at the exit of the scrambler

Claims (11)

Memory module with integrated address scrambler unit, in which the address scrambler unit ( 22 . 23 ) Has address inputs for creating an address (A <m: 0>) and can be designed and operated in such a way that the address scrambler unit ( 22 . 23 ) depending on control bits (S1 - SN) the address (A <m: 0>) can be scrambled in different ways, and in which a memory cell array ( 21 ) is provided that the address scrambler unit ( 22 . 23 ) is connected downstream. Memory chip according to Claim 1, in which the address scrambler unit ( 22 . 23 ) has several predefined scramblers (1 - N), which are designed and operable in such a way that the address (A <m: 0>) can be scrambled differently depending on the control bits (S1-SN). Memory chip according to Claim 2, in which one of the predefined scramblers ( 1 ) a conversion element (SCRAM 1 ) for converting a bit (A <0>) of the address (A <m: 0>) and a multiplexer (MUX 1 ), which depending on one of the control bits (S1 – SN) either that of the conversion element (SCRAM 1 ) the converted bit (SCl <0>) or the unscrambled bit (A <0>). Memory block according to Claim 3, in which a further one of the predefined scramblers (N), a further conversion element (N.1) for converting an address bit (A <0>) of the address (A <m: 0>) and a multiplexer (N.5 ) which, depending on one of the control bits (S1 – SN), either the address bit (SCN <0>) converted by the further conversion element (N.1) or that of one of the other predefined scramblers ( 1 ) generated address bit (A <0 '>). Memory chip according to one of Claims 1 to 4, in which the address scrambler unit ( 22 . 23 ) a programmable scrambler ( 3 ), the programmable scrambler ( 3 ) is designed and can be operated in such a way that the address (A <m: 0>) can be scrambled in various ways depending on the control bits (S0, S1). Memory chip according to Claim 5, in which the programmable scrambler ( 3 ) multiple multiplexers ( 3.1 . 3.2 ) that are connected on the input side to several of the address inputs (A <m: 0>) in which the programmable scrambler ( 3 ) a conversion unit ( 3.3 - 3.6 ), which consists of certain bits of the address (A <m: 0>) and those of the multiplexers ( 3.1 . 3.2 ) delivered bits scrambled address bits (A <m ': 0'>) generated, the control bits (S0, S1) for controlling the multiplexers ( 3.1 . 3.2 ) serve. Memory chip according to one of Claims 3 to 6, in which the conversion element (SCRAM 1 ; N.1; 3.3 - 3.6 ) has an XOR gate, which is connected on the input side to a first and a second address line (A <0>, A <1>). Memory chip according to one of Claims 1 to 7, in which the control bits (S1 - SN) are connected via a control connection ( 20.1 ) can be specified externally. Memory chip according to one of Claims 1 to 8, in which the address scrambler unit ( 22 . 23 ) can be activated by means of an external signal (ctr). Method for scrambling an address in an integrated memory, in which a control command (ctr) is used to 20 ) intended address scrambler unit (1 - N; 3) is prompted to select a scramble pattern from several possible scramble patterns and to use this for scrambling, in which the address (A <m: 0>) of the address scrambler unit (1 - N; 3) is supplied, in which the address (A <m: 0>) is scrambled using the address scrambler unit (1 - N; 3), and in which the scrambled address (A <m ': 0'>) is one In the storage room ( 20 ) provided memory cell array ( 21 ) is supplied. The method of claim 10, wherein the memory ( 20 ) is put into a test mode before scrambling the address (A <m: 0>).