EP3823022A2

EP3823022A2 - Semiconductor memory device including capacitor

Info

Publication number: EP3823022A2
Application number: EP20202906.2A
Authority: EP
Inventors: Kyung Hwa Yun; Chan Ho Kim; Dong Ku Kang; Bong Soon Lim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-11-12
Filing date: 2020-10-20
Publication date: 2021-05-19
Also published as: KR20210057351A; EP3823022A3; US20210143162A1; JP2021077893A; US11563016B2; CN112864165A

Abstract

A semiconductor memory device and operating method are provided. The three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a substrate and including a plurality of peripheral circuits, horizontal semiconductor layers disposed on the peripheral logic structure, a plurality of stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, a plurality of electrode isolation regions extending in the first direction and a second direction and separating the plurality of stack structures, the electrode isolation regions being connected to the horizontal semiconductor layers and a plurality of through structures disposed in the peripheral logic structure to penetrate the stack structures in the first direction, each of the through structures having one side connected to through channel contacts, wherein the electrode pads form capacitances respectively with at least one of the electrode isolation regions or with at least one of the through structures.

Description

BACKGROUND

1. Field

The present disclosure relates to a semiconductor memory device, and more particularly, to a three-dimensional (3D) semiconductor memory device including a capacitor and having an improved reliability and integration density.

2. Description of the Related Art

There is a demand for improving the integration density of semiconductor memory devices in order to meet consumer requirements of high performance and low price. Since integration density is an important factor that determines the price of a semiconductor memory device, an improvement in integration density is highly required. The integration density of a two-dimensional (2D) (or planar) semiconductor memory device is determined by the area occupied by each unit memory cell and may thus be highly affected by the level of fine pattern forming technology.
However, since expensive equipment is needed to fabricate fine patterns, there is a clear limit in increasing the integration density of a 2D semiconductor memory device. Thus, a memory device in which memory cells are arranged three-dimensionally has been suggested.

SUMMARY

The present invention provides a three-dimensional semiconductor device according to the appended claims. Embodiments of the present disclosure provide a semiconductor memory device including a vertical channel structure with an improved reliability and integration density.
However, embodiments of the present disclosure are not restricted to those set forth herein. The above and other embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.
According to an embodiment of the present disclosure, the three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a substrate and including a plurality of peripheral circuits, horizontal semiconductor layers disposed on the peripheral logic structure, a plurality of stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, a plurality of electrode isolation regions extending in the first direction and a second direction and separating the plurality of stack structures, the electrode isolation regions being connected to the horizontal semiconductor layers and a plurality of through structures disposed in the peripheral logic structure to penetrate the stack structures in the first direction, each of the through structures having one side connected to through channel contacts, wherein the electrode pads form capacitances respectively with at least one of the electrode isolation regions or with at least one of the through structures.
The through structures may have second sides connected to the horizontal semiconductor layers or to wiring lines below the horizontal semiconductor layers respectively.
The plurality of stack structures may include a memory cell array region and a peripheral region. At least two the electrode isolation regions may be located in the peripheral region. A plurality of through structures may be disposed in the peripheral region, between at least two adjacent electrode isolation regions, to penetrate the stack structures in the first direction, the through structures having first sides connected to through channel contacts. In the peripheral region, the stack structures are stacked to have the same width in the second and third directions.
According to another embodiment of the present disclosure, the three-dimensional (3D) semiconductor memory device includes a plurality of stack structures in which mold layers and electrode pads are alternately stacked in a first direction on horizontal semiconductor layers, the plurality of stack structures including a memory cell array region and a peripheral region, a plurality of electrode isolation regions extending in a second direction, the electrode isolation regions being spaced apart from one another in a third direction to separate the stack structures and a plurality of through structures disposed in a peripheral region, between at least two adjacent electrode isolation regions, to penetrate the stack structures in the first direction, the through structures having one sides connected to through channel contacts, wherein in the peripheral region, the stack structures are stacked in the second and third directions to have the same width.
According to the other embodiment of the present disclosure, a three-dimensional (3D) semiconductor memory device includes at least one peripheral region in which mold layers and electrode pads are alternately arranged on horizontal semiconductor layers, a plurality of electrode isolation regions extending in the peripheral region in a wordline direction and a bitline direction to be spaced apart from one another, a mold region disposed between two adjacent electrode isolation regions among the plurality of the electrode isolation regions and a plurality of through structures vertically penetrating the mold region respectively, wherein the electrode pads form capacitances with at least one of the through structures or with one of the electrode isolation regions.
Other features and embodiments may be apparent from the following detailed description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other embodiments and features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a block diagram of a semiconductor memory device according to some embodiments of the present disclosure.
FIG. 2 is a perspective view of a semiconductor memory device according to some embodiments of the present disclosure.
FIG. 3 is a circuit diagram illustrating one of a plurality of memory cell blocks included in a semiconductor memory device according to some embodiments of the present disclosure.
FIG. 4 is a layout view of a semiconductor memory device according to some embodiments of the present disclosure.
FIGS. 5A and 5B are plan views illustrating some of a plurality of stack structures illustrated in FIG. 4.
FIG. 6 is a plan view illustrating one of the stack structures illustrated in FIG. 4.
FIG. 7 is a cross-sectional view taken along line A-A' of FIG. 6.
FIG. 8A illustrates the part Y of the peripheral region FR of the semiconductor memory device of FIG. 6.
FIG. 8B is a cross-sectional view taken along line B1-B1' of FIG. 8A
FIG. 9A illustrates a peripheral region of a semiconductor memory device according to some embodiments of the present disclosure.
FIG. 9B is a cross-sectional view taken along line B2-B2' of FIG. 9A.
FIG. 10A illustrates a peripheral region of a semiconductor memory device according to some embodiments of the present disclosure.
FIGS. 10B and 10C are cross-sectional views taken along line B3-B3' of FIG. 10A.
FIG. 11 is a block diagram of an exemplary peripheral circuit of FIG. 1.
FIG. 12 is a block diagram of a storage device including a 3D semiconductor memory device, according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a semiconductor memory device according to some embodiments of the present disclosure.
Referring to FIG. 1, a semiconductor memory device 10 may include a memory cell array 20 and a peripheral circuit 30.
The semiconductor memory device 10 may include, for example, a NAND flash memory, a vertical NAND (VNAND) flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a magneto-resistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque-random access memory (STT-RAM), or the like, but the present disclosure is not limited thereto.
The semiconductor memory device 1 will hereinafter be described as being, for example, a VNAND flash memory, but the present disclosure is not limited thereto. That is, the present disclosure is also applicable to other nonvolatile memories.
The memory cell array 20 may include a plurality of memory cell blocks BLK1 through BLKn. Each of the memory cell blocks BLK1 through BLKn may include a plurality of memory cells. The memory cell blocks BLK1 through BLKn may be connected to the peripheral circuit 30 via bitlines BL, wordlines WL, one or more string selection lines SSL, and one or more ground selection lines GSL.
Specifically, the memory cell blocks BLK1 through BLKn may be connected to a row decoder 33 via the wordlines WL, the string selection lines SSL, and the ground selection lines GSL. Also, the memory cell blocks BLK1 through BLKn may be connected to a page buffer 35 via the bitlines BL.
The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10 and may exchange data DATA with an external device (not illustrated) on the outside of the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, the row decoder 33, and the page buffer 35.
Although not specifically illustrated, the peripheral circuit 30 may further include various sub-circuits such as an input/output (I/O) circuit, a voltage generation circuit for generating various voltages necessary for operating the semiconductor memory device 10, and an error correction circuit for correcting error in the data DATA read from the memory cell array 20.
The control logic 37 may be connected to the row decoder 33, the voltage generation circuit, and the I/O circuit. The control logic 37 may control a general operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals for use in the semiconductor memory device 10 in response to the control signal CTRL.
For example, the control logic 37 may control the levels of voltages provided to the wordlines WL and the bitlines BL during a memory operation such as a program operation or an erase operation.
The row decoder 33 may select at least one of the memory cell blocks BLK1 through BLKn in response to the address ADDR and may select at least one of the wordlines WL, at least one of the string selection lines SSL, and at least one of the ground selection lines GSL of the selected memory cell block. The row decoder 33 may transmit a voltage for performing a memory operation on the wordlines WL of the selected memory cell block.
The page buffer 35 may be connected to the memory cell array 20 via the bitlines BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, during a program operation, the page buffer 35 may operate as a write driver and may apply, to the bitlines BL, a voltage corresponding to the data DATA to be stored in the memory cell array 20. During a read operation, the page buffer 35 may operate as a sense amplifier and may sense the data DATA stored in the memory cell array 20.
FIG. 2 is a perspective view of a semiconductor memory device according to some embodiments of the present disclosure.
Referring to FIG. 2, the semiconductor memory device may include a peripheral logic structure PS and a cell array structure CS.
The cell array structure CS may be stacked on the peripheral logic structure PS. That is, in a plan view, the peripheral logic structure PS and the cell array structure CS may overlap with each other. The semiconductor memory device may have a Cell-Over-Peri (COP) structure.
For example, the cell array structure CS may include the memory cell array 20 of FIG. 1. The peripheral logic structure PS may include the peripheral circuit 30 of FIG. 1.
The cell array structure CS may include a plurality of memory cell blocks BLK1 through BLKn, which are disposed on the peripheral logic structure PS.
FIG. 3 is a circuit diagram illustrating one of a plurality of memory cell blocks included in a semiconductor memory device according to some embodiments of the present disclosure.
Referring to FIG. 3, a memory cell block according to some embodiments of the present disclosure may include a common source line CSL, a plurality of bitlines BL0 through BL2, and a plurality of cell strings CSTR, which are disposed between the common source line CSL and the bitlines BL.
The cell strings CSTR may be connected in parallel to each of the bitlines BL0 through BL2. The cell strings CSTR may be connected in common to the common source line CSL. That is, the cell strings CSTR may be disposed between the common source line CSL and the bitlines BL0 through BL2. A plurality of common source lines CSL may be arranged two-dimensionally. The same voltage may be applied to the plurality of common source lines CSL, or the plurality of common source lines CSL may be separately controlled electrically.
For example, each of the cell strings CSTR may include string selection transistors (SST1 and SST2), which are connected in series, memory cells MCT, which are connected in series, and a ground selection transistor GST. Each of the memory cells MST includes a data storage element.
For example, each of the cell strings CSTR may include first and second string selection transistors SST1 and SST2, which are connected in series, the second string selection transistor SST2 may be connected to one of the bitlines BL0 through BL2, and the ground selection transistor GST may be connected to the common source line CSL. Memory cells MCT may be connected in series between the first string selection transistor SST1 and the ground selection transistor GST.
Each of the cell strings CSTR may further include a dummy cell DMC, which is connected between the first string selection transistor SST1 and the memory cells MCT. Although not specifically illustrated, the dummy cell DMC may also be connected between the ground selection transistor GST and the memory cells MCT. The ground selection transistor GST may include a plurality of metal oxide semiconductor (MOS) transistors, which are connected in series. In another example, each of the cell strings CSTR may include only one string selection transistor.
In some embodiments, the first string selection transistor SST1 may be controlled by a first string selection line SSL1, and the second string selection transistor SST2 may be controlled by a second string selection line SSL2. The memory cells MCT may be controlled by a plurality of wordlines WL0 through WLn, and the dummy cell DMC may be controlled by a dummy wordline DWL. The ground selection transistor GST may be controlled by ground selection lines GSL. The common source line CSL may be connected in common to the sources of the ground selection transistors GST of the cell strings CSTR.
Each of the cell strings CSTR may consist of a plurality of memory cells MCT, which have different distances from the common source line CSL. A plurality of wordlines (WLO through WLn and DWL) may be disposed between the common source line CSL and the bitlines BL0 through BL2.
The gate electrodes of memory cells MCT at substantially the same distance from the common source line CSL may be connected in common to one of the wordlines (WLO through WLn and DWL) and may thus be in an equipotential state. Even if the gate electrodes of memory cells MCT are disposed on substantially the same level from the common source line CSL, they can be controlled independently if they are arranged in different rows or different columns.
The ground selection lines GSL0 through GSL2 and the string selection lines SSL1 and SSL2 may extend in the same direction as the wordlines (WLO through WLn and DWL). The ground selection lines GSL0 through GSL2 and the string selection lines SSL1 and SSL2 are disposed on substantially the same level and be electrically isolated.
FIG. 4 is a layout view of a semiconductor memory device according to some embodiments of the present disclosure, and FIGS. 5A and 5B are plan views illustrating some of a plurality of stack structures illustrated in FIG. 4. FIG. 6 is a plan view illustrating one of the stack structures illustrated in FIG. 4, and FIG. 7 is a cross-sectional view taken along line A-A' of FIG. 6.
A semiconductor memory device 10 may include a peripheral logic structure PS and a cell array structure CS.
The peripheral logic structure PS may include one or more peripheral circuits TR and a plurality of lower connecting wiring bodies 116. The peripheral circuits TR may be formed on a substrate 100. The peripheral circuits TR may be included in the page buffer 35 of FIG. 1 or in the row decoder 33 of FIG. 1. The peripheral circuits TR will be described later in detail with reference to FIG. 11.
The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be a silicon substrate or may include another material such as, for example, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, a lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.
A peripheral logic insulating film 110 may be formed on the substrate 100. The peripheral logic insulating film 110 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.
A lower connecting wiring body 116 may be formed in the peripheral logic insulating film 110. The lower connecting wiring body 116 may include a plurality of wiring lines. The lower connecting wiring body 116 may include a plurality of layers, and in each of the layers, at least one wiring line may be disposed. The lower connecting wiring body 116 may be connected to a peripheral circuit TR.
The cell array structure CS may include a plurality of horizontal semiconductor layers 150, which are disposed on the peripheral logic structure PS, and a plurality of first through fourth stack structures ST0 through ST3, which are disposed on each of the horizontal semiconductor layers 150.
The horizontal semiconductor layers 150 may be disposed on the peripheral logic structure PS. The horizontal semiconductor layers 150 may extend along the top surface of the peripheral logic structure PS.
Each of the horizontal semiconductor layers 150 may include a lower support semiconductor layer LSB and a common source plate CSP, which is disposed on the lower support semiconductor layer LSB. The horizontal semiconductor layers 150 may include at least one of, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and a mixture thereof. The horizontal semiconductor layers 150 may have at least one of a monocrystalline structure, an amorphous crystalline structure, and a polycrystalline structure.
The common source plate CSP may serve as the common source line CSL of FIG. 3.
Alternatively, each of the horizontal semiconductor layers 150 may include only the common source plate CSP.
Common source lines that extend in a direction D2, instead of two-dimensional (2D) planar common source plates, may be formed in the horizontal semiconductor layers 150.
Filler insulating films (not illustrated) may be formed on the peripheral logic structure PS. The filler insulating films may fill the gaps between the horizontal semiconductor layers 150. The filler insulating films may include, for example, silicon oxide, but the present disclosure is not limited thereto.
A plurality of first through fourth stack structures ST0 through ST3 may be disposed on each of the horizontal semiconductor layers 150. The first through fourth stack structures ST0 through ST3 may be arranged to be spaced apart from one another in a direction D1.
FIG. 4 illustrates that there are four stack structures disposed on each of the horizontal semiconductor layers 150, but the present disclosure is not limited thereto. In some embodiments, two or more stack structures may be disposed on each of the horizontal semiconductor layers 150.
Each of the first through fourth stack structures ST0 through ST3 may include a memory cell array region MCR and a peripheral region FR. The memory cell array region MCR may correspond to the memory cell array 20 of FIG. 1, and the peripheral region FR may correspond to a capacitance region in which a capacitor used in the peripheral circuit 30 is formed.
For example, as illustrated in FIG. 5A, the stack structure ST0 may include a memory cell array region MCR0 and at least one peripheral region FR0.
Referring to FIG. 5A, a peripheral region FR0 may extend in the direction D2 (or a wordline direction) and may be disposed to be a distance D apart from a memory cell array region MCR0 in the direction D1 (or a bitline direction).
Referring to FIG. 5A, the peripheral region FR0 may form a capacitor with a predefined capacitance and may thus be electrically connected to a peripheral circuit for the memory cell array region MCR0.
In another example, as illustrated in FIG. 5B, the stack structure ST0 may include at least two memory cell array regions MCR0 and MCR1 and at least one peripheral region FR0.
Referring to FIG. 5B, the peripheral region FR0 may extend in the direction D2 (or a wordline direction) and may be disposed to be a predetermined distance apart from the memory cell array regions MCR0 and MCR1 in the direction D1 (or a bitline direction).
Referring to FIG. 5B, the peripheral region FR0 may form a capacitor with a predetermined capacitance and may thus be electrically connected to peripheral circuits for the memory cell array regions MCR0 and MCR1. That is, the memory cell array regions MCR0 and MCR1 are connected to the capacitor in the peripheral region FR0 and can thus be used exclusively.
Referring to FIG. 5B, a peripheral region FR0 may form a capacitor with a predetermined capacitance and may thus be electrically connected to peripheral circuits for the memory cell array region MCR1 and a memory cell array region MCR2. That is, the memory cell array regions MCR1 and MCR2 are connected to the capacitor in the peripheral region FR0 and can thus be used exclusively.
Although not specifically illustrated, a plurality of peripheral regions FR may be provided for a single memory cell region MCR. For example, two peripheral regions, i.e., a first peripheral region "FR A" with a first capacitance and a second peripheral region "FR B" with a second capacitance, may be provided near a single memory cell region MCR to be spaced apart from each other, in which case, the peripheral circuit 30 below the memory cell region MCR may be connected to one of the first and second peripheral regions "FR A" or "FR B", or connected in series or in parallel to both the first and second peripheral regions "FR A" and "FR B", depending on the capacitance required.
A three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure will hereinafter be described with reference to FIGS. 6 and 7, taking a stack structure ST1 as an example. The description of the stack structure ST1 that follows may be directly applicable to stack structures ST2, ST3, and ST0.
Referring to FIGS. 6 and 7, the stack structure ST1 includes a memory cell array region MCR and a peripheral region FR. The stack structure ST1 may include a plurality of electrode pads (EP1 through EP7), which are stacked in a direction D3. The stack structure ST1 may further include interlayer insulating films, which are disposed between the electrode pads (EP1 through EP7). The stack structure ST1 is illustrated as including seven electrode pads, but the present disclosure is not limited thereto.
The electrode pads (EP1 through EP7) may include gate electrodes that are included in the string selection transistors (SST1 and SST2) and the ground selection transistor GST. The electrode pads (EP1 through EP7) may further include wordlines of memory cells MCT.
For example, the stack structure ST1 may include fourth and fifth electrode pads EP4 and EP5, which are adjacent to each other in the direction D3. The fifth electrode pad EP5 may be disposed on the fourth electrode pad EP4.
The fourth electrode pad EP4 may protrude in a direction D1 beyond the fifth electrode pad EP5. That is, first sidewalls of the fourth and fifth electrode pads EP4 and EP5 that face a stack structure ST2 may be a predetermined width apart from each other in the direction D1.
The fourth electrode pad EP4 may protrude in a direction D2 beyond the fifth electrode pad EP5. That is, second sidewalls of the fourth and fifth electrode pads EP4 and EP5 may be a predetermined width apart from each other in the direction D2.
In some embodiments, the protruded width, in the direction D1, between the first sidewalls of the fourth and fifth electrode pads EP4 and EP5 may be the same as, or different from, the protruded width, in the direction D2, between the second sidewalls of the fourth and fifth electrode pads EP4 and EP5.
The stack structure ST1 may include a cell region CR and first cell extension regions CER1, which extend in the direction D1, from the cell region CR. The stack structure ST1 may further include second cell extension regions CER2, which extend in the direction D2 from the cell region CR.
A plurality of electrode isolation regions WLC may be disposed in the stack structure ST1. The electrode isolation regions WLC may extend in the direction D2.
The stack structure ST1 may include a plurality of electrode isolation trenches. The electrode isolation regions WLC may fill the electrode isolation trenches.
For example, the electrode isolation regions WLC may include an insulating material for filling the electrode isolation trenches. The electrode isolation regions WLC may include, for example, silicon oxide.
In another example, the electrode isolation regions WLC may include liners, which are formed along sidewalls of the electrode isolation trenches , and filling films, which are disposed on the liners. The liners may include an insulating material, and the filling film may include a conductive material. Alternatively, the liners may include a conductive material, and the filling films may include an insulating material.
In yet another example, the electrode isolation regions WLC may not include an insulating material for filling the electrode isolation trenches. The electrode isolation regions WLC may fill the electrode isolation trenches with a conductive material.
The electrode isolation regions WLC may not be disposed in the first cell extension regions CER1. The electrode isolation trenches, in which the electrode isolation regions WLC are formed, are used in a replacement process for forming the wordlines WL0 through WLn of FIG. 3. That is, parts of a mold film are removed using the electrode isolation trenches, and the wordlines WL0 through WLn of FIG. 3 are formed where the mold film is removed.
The mold film may not be entirely removed from the first cell extension regions CER1 of the memory cell region MCR. As a result, the mold film may remain in the first cell extension regions CER1. The first cell extension regions CER1 may include first mold regions EP_M1, which extend in the direction D2. That is, the stack structure ST1 may include the first mold regions EP_M1, which are disposed on both sides, in the direction D1, of the cell region CR. The mold regions EP_M1 include the stacked mold film and after the replacement processing and the mold film may include silicon nitride, the present invention is not limited thereto. The mold film may be a mold layer or a sacrificial layer(or film).
In the memory cell array region MCR, each of the electrode pads (EP1 through EP7) may include an electrode region EP_E and first mold regions EP_M1. The electrode region EP_E may include, for example, tungsten (W), but the present disclosure is not limited thereto.
The mold region EP_M1 is placed on both side of cell region CR in a bitline direction D1. For example, each of the electrode pads (EP1 through EP7) may include an electrode region EP_E and first mold regions EP_M1, which are disposed on both sides, in the direction D1, of the electrode region EP_E. The electrode region EP_E may be separated by a plurality of electrode isolation regions WLC, which extend in the direction D2. The first mold regions EP_M1 may extend in the direction D1 from the electrode region EP_E.
The plurality of electrode isolation regions WLC may include first and second electrode isolation regions, which are spaced apart from each other in the direction D1. The electrode region EP_E may be disposed between the first and second electrode isolation regions. Part of the electrode region EP_E may be disposed in an area other than that between the first and second electrode isolation regions.
In the memory cell array region MCR, the width, in the direction D1, of the first mold regions EP_M1 of each of the electrode pads (EP1 through EP7) may decrease away from the peripheral logic structure PS in the direction D3. For example, the width, in the direction D1, of the first mold regions EP_M1 of the fourth electrode pad EP4 may be greater than the width, in the direction D1, of the first mold regions EP_M1 of the fifth electrode pad EP5.
For example, in the memory cell array region MCR, first mold regions EP_M1 of the fourth electrode pad EP4 may protrude in the direction D1 beyond first mold regions EP_M1 of the fifth electrode pad EP5 by as much as a predetermined width.
In the memory cell array region MCR, sidewalls of first mold regions EP_M1 of the fourth and fifth electrode pads EP4 and EP5 that face the stack structure ST2 may be a predetermined distance apart from each other in the direction D1.
In the memory cell array region MCR, the sidewall profile of the stack structure ST1 may have a stepwise structure and may be defined by the first mold regions EP_M1 included in each of the electrode pads (EP1 through EP7).
The second cell extension regions CER2 of the memory cell array region MCR may include second mold regions EP_M2. For example, second mold regions EP_M2 of the fourth electrode pad EP4 may protrude in the direction D2 beyond second mold regions EP_M2 of the fifth electrode pad EP5 by as much as a predetermined width.
In the memory cell array region MCR, sidewalls of the second mold regions EP_M2 of the fourth electrode pad EP4 may be a predetermined distance apart from sidewalls of the second mold regions EP_M2 of the fifth electrode pad EP5 in the direction D2.
The first mold regions EP_M1 and the second mold regions EP_M2 may include, for example, silicon nitride, but the present disclosure is not limited thereto.
In the memory cell array region MCR, a plurality of vertical structures VS that penetrate the stack structure ST1 may be disposed between each pair of adjacent electrode isolation regions WLC. The vertical structures VS may be connected to the horizontal semiconductor layers 150.
For example, vertical structures VS that are used as the channel regions of memory cells may be electrically connected to the common source plates CSP of the horizontal semiconductor layers 150.
The vertical structures VS may include a semiconductor material such as, for example, Si, Ge, or a mixture thereof. Alternatively, the vertical structures may include a semiconductor material such as a metal oxide. Each of the vertical structures VS may include a blocking insulating film, a charge storage film, and a tunnel insulating film. The blocking insulating film, the charge storage film, and the tunnel insulating film may be separated from one another at lower parts of the respective vertical structures VS, and a contact supporting film CSB may be disposed between the blocking insulating film, the charge storage film, and the tunnel insulating film. The contact supporting film CSB may electrically connect the common source plates CSP of the horizontal semiconductor layers 150 and the vertical structures VS. The contact supporting film CSB may include a semiconductor material such as, for example, Si, Ge, or a mixture thereof.
In the peripheral region FR, each of the electrode pads (EP1 through EP7) may include an electrode region EP_E and third mold regions. The electrode region EP_E may include, for example, tungsten, W, but the present disclosure is not limited thereto.
The peripheral region FR may be a distance D apart from the memory cell array region MCR in the direction D1 (or the bitline direction).
In the peripheral region FR, unlike in the memory cell array region MCR, the first cell extension regions CER1 and the second cell extension regions CER2 may not be formed. As illustrated in FIG. 7, in the peripheral region FR, the sidewall profile of the electrode pads (EP1 through EP7) may not have a stepwise structure in the direction D3. For example, the fourth and fifth electrode pads EP4 and EP5 may have the same length in the direction D2. Thus, the length, in the direction D2, of the peripheral region FR, i.e., a width W1 of the peripheral region FR, may be smaller than the length, in the direction D2, of the memory cell array region MCR, i.e., CER2+CR+CER2, and the length, in the direction D1, of the peripheral region FR, i.e., a width W2 of the peripheral region FR, may be smaller than the length, in the direction D1, of the memory cell array region MCR, i.e., CER1+CR+CER1. In other words, the length, in the wordline direction, of the peripheral region FR may be smaller than the length, in the wordline direction, of the memory cell region MCR.
The peripheral region FR may include at least two electrode isolation regions WLC. The distance between the electrode isolation regions WLC in the peripheral region FR may be greater than the distance between electrode isolation regions WLC where there are no through structures. For example, the distance between the electrode isolation regions WLC in the peripheral region FR may be three times greater than the distance between electrode isolation regions WLC where there are no through structures THV. The distance between electrode isolation regions WLC where there are no through structures THV may be the same as the distance between electrode isolation regions WLC where there are, for example, vertical structures VS, i.e., S1.
The peripheral region FR may include a plurality of through structures THV between a pair of adjacent electrode isolation regions WLC. The plurality of through structures THV may be spaced apart from one another in the direction D2 and may be arranged in at least one row. Alternatively, the plurality of through structures THV may be spaced apart from one another in the direction D1 and may be arranged in at least one column. Alternatively, the plurality of through structures THV may be spaced apart from one another in both the directions D1 and D2 and may be arranged in at least two rows and at least two columns.
There are two schemes to form the through structures THV, i.e., a first scheme in which the through structures THV are formed before a replacement process and a second scheme in which the through structures THV are formed after a replacement process. In the first scheme, through trenches are formed between the pair of adjacent electrode isolation regions WLC, the through structures THV are formed by depositing an oxide into the through trenches and injecting a conductive material into the through trenches, and a replacement process is performed. In the second scheme, a replacement process is performed on the pair of adjacent electrode isolation regions WLC, the through trenches are formed, and the through structures THV are formed by injecting a conductive material into the through trenches.
The distance between the pair of adjacent electrode isolation regions WLC may be greater in the second scheme than in the first scheme. Since the distance between the pair of adjacent electrode isolation regions WLC is relatively large, there may exist a mold region not filled with a conductive material, in the middle of the pair of adjacent electrode isolation regions WLC.
In the peripheral region FR, the through structures THV may be formed by the second scheme. That is, the electrode isolation regions WLC may be used in a replacement process, and the through structures THV may be formed after a replacement process using the electrode isolation regions WLC. Electrodes EP in the mold structure are replaced from the mold layer to the conductive materials. The through structures THV may be disposed to penetrate a mold layer between the pair of adjacent electrode isolation regions WLC. The mold layer may be disposed to extend in the direction D2, between the pair of adjacent electrode isolation regions WLC.
A first interlayer insulating film 151 may be formed on the horizontal semiconductor layers 150. The first interlayer insulating film 151 may cover the stack structures ST1 and ST2 in the memory cell array region MCR and in the peripheral region FR. The first interlayer insulating film 151 may include, for example, silicon oxide, but the present disclosure is not limited thereto.
Second and third interlayer insulating films 152 and 153 may be sequentially formed on the first interlayer insulating film 1 51. Parts of the electrode isolation regions WLC may extend even to the second interlayer insulating film 152.
Bitlines B1 and through channel contact lines TH_L may be disposed on the stack structure ST1. The bitlines BL may extend in the direction D1. The bitlines BL may be electrically connected to at least one of the vertical structures VS in the direction D1.
The through channel contact lines TH_L may extend in the direction D1. At least one of a plurality of through channel contact lines TH_L included in the stack structure ST0 may be electrically connected to at least one of a plurality of through channel contact lines TH_L included in the stack structure ST1.
The bitlines BL and the through channel contact lines TH_L may be formed on the third interlayer insulating film 153. The bitlines BL may be electrically connected to the vertical structures VS via bitline pads and bitline plugs.
Although not specifically illustrated, a plurality of through vias may be disposed between the stack structures ST0 and ST1. The through vias may be spaced apart from one another in the direction D1.
The through vias may be electrically connected to the peripheral circuit TR of the peripheral logic structure PS. The through vias may be connected to the bitlines BL via through via connecting wires.
The through vias may not penetrate the stack structures ST0 and ST1. The through vias may penetrate the space between the stack structures ST0 and ST1 and may thus be electrically connected to the peripheral circuit TR.
FIGS. 8A through 10C are enlarged views illustrating part Y of the peripheral region FR of the semiconductor memory device of FIG. 6.
Specifically, FIG. 8A illustrates the part Y of the peripheral region FR of the semiconductor memory device of FIG. 6, and FIG. 8B is a cross-sectional view taken along line B1-B1' of FIG. 8A. It will be appreciated that the number of through structures is greater in FIG. 8A than in FIG. 6 but this is not a limitation of the present disclosure. For convenience, FIGS. 8A and 8B illustrate through structures THV that are arranged in a row, between a pair of adjacent electrode isolation regions WLC, to be spaced at regular intervals in the direction D1, but the present disclosure is not limited thereto. The present disclosure may also be applicable to through structures THV that are arranged in multiple rows between the pair of adjacent electrode isolation regions WLC.
Referring to FIGS. 8A and 8B, the semiconductor memory device of FIG. 6 may include, in the peripheral region FR, at least two electrode isolation regions WLC, which are adjacent to each other, and a plurality of through structures THV, which are disposed between the electrode isolation regions WLC to be spaced apart from one another in the direction D2.
The peripheral region FR may include the electrode isolation regions WLC and the through structures THV. In each of the electrode isolation regions WLC, a conductive pattern and spacers WLCI, which surround sidewalls of the conductive pattern, may be formed. The electrode isolation regions WLC may extend in the directions D2 and D3 and may be spaced apart from each other in the direction D1 by as much as a width W3. First sides (e.g. the top surfaces) of the conductive patterns of the electrode isolation regions WLC may be connected to electrode isolation region contact lines WLCL via electrode isolation region plugs WLC_PG and electrode isolation pads WLC_PAD, and second sides (e.g. the bottom surfaces) of the conductive patterns of the electrode isolation regions WLC may be connected to the common electrode plates CSP of the horizontal semiconductor layers 150.
The through structures THV may be arranged in at least one row, between the electrode isolation regions WLC, to be spaced at regular intervals in the direction D2. The through structures THV may be disposed to be a width W4 apart in the direction D1 from the electrode isolation regions WLC. First sides (e.g. the top surfaces) of the through structures THV may be connected to the through channel contact lines TH_L, and second sides (e.g. the bottom surfaces) of the through structures THV may be connected to wiring lines 116 in the peripheral logic structure PS.
If a first voltage is applied via the through channel contact lines TH_L, the electrode pads (EP1 through EP7) may be bonded to the through structures THV with no through insulating film THI. For example, the first voltage may be an input power supply voltage VDD or a ground voltage GND.
Since the electrode isolation regions WLC are electrically disconnected from the electrode pads (EP1 through EP7) due to the spacers WLCI, a second voltage may be applied via the electrode isolation region contact lines WLCL. For example, the second voltage may be the ground voltage GND or the input power supply voltage VDD.
In response to the first and second voltages, which are different, being applied, capacitances may be generated between the conductive patterns of the electrode isolation regions WLC and the electrode pads (EP1 through EP7). The capacitances may increase as the number of electrode pads that are stacked. The capacitances may be connected to the peripheral circuit TR via the wiring lines 116.
FIG. 9A illustrates a peripheral region of a semiconductor memory device according to some embodiments of the present disclosure, and FIG. 9B is a cross-sectional view taken along line B2-B2' of FIG. 9A.
Referring to FIGS. 9A and 9B, the semiconductor memory device may include, in a peripheral region FR, at least two electrode isolation regions WLC, which are adjacent to each other, and a plurality of through structures THV, which are disposed between the electrode isolation regions WLC to be spaced apart from one another in a direction D2.
The peripheral region FR may include the electrode isolation regions WLC and the through structures THV. Conductive patterns may be formed in the electrode isolation regions WLC. The electrode isolation regions WLC may extend in the direction D2 and a direction D3 and may be spaced apart from each other in a direction D1 by as much as a width W3. First sides (e.g. the top surfaces) of the conductive patterns of the electrode isolation regions WLC may be connected to electrode isolation region contact lines WLCL via electrode isolation region contact plugs WLC_PG, T_PG and electrode isolation pads WLC_PAD, and second sides (e.g. the bottom surfaces) of the conductive patterns of the electrode isolation regions WLC may be connected to common electrode plates CSP of horizontal semiconductor layers 150.
Through structures THV may be arranged in at least one row, between the electrode isolation regions WLC, to be spaced at regular intervals in the direction D2. The through structures THV may be disposed to be a width W4 apart in the direction D1 from the electrode isolation regions WLC. First sides (e.g. the top surfaces) of the through structures THV may be connected to through channel contact lines TH_L, and second sides (e.g. the bottom surfaces) of the through structures THV may be connected to wiring lines LM2 in a peripheral logic structure PS. The through structures THV of FIGS. 9A and 9B, unlike the through structures THV of FIGS. 8A and 8B, include conductive regions THV and through insulating films THI, which surround the conductive regions THV, for example, on the sidewalls thereof.
In response to a first voltage being applied to the through channel contact lines TH_L and a second voltage, which is different from the first voltage, being applied to the electrode isolation region contact lines WLCL, capacitances are generated between the conductive patterns of the electrode isolation regions WLC. The capacitances may increase as the number of electrode pads that are stacked. The capacitances may be connected to a peripheral circuit TR via wiring lines 116.
FIG. 10A illustrates a peripheral region of a semiconductor memory device according to some embodiments of the present disclosure, and FIGS. 10B and 10C are cross-sectional views taken along line B3-B3' of FIG. 10A.
Referring to FIGS. 10A and 10B, the semiconductor memory device may include, in a peripheral region FR, at least two electrode isolation regions WLC, which are adjacent to each other, and a plurality of through structures THV, which are disposed between the electrode isolation regions WLC to be spaced apart from one another in directions D1 and D2.
The through structures THV may include first through structures THV1 and second through structures THV1. The first through structures THV1 may include conductive regions and through insulating films THI, which surround the conductive regions, and the second through structures THV2 may include only conductive regions. The first through structures THV1 and the second through structures THV2 may be alternately arranged.
In some embodiments, first and third rows of first through structures THV1 and second and fourth rows of second through structures THV2 may be provided to be spaced apart from one another in the direction D1.
Although not specifically illustrated, in some embodiments, rows of first through structures THV1 and rows of second through structures THV2 may be alternately arranged. For example, two rows of first through structures THV1 and two rows of second through structures THV2 may be alternately arranged.
Although not specifically illustrated, in some embodiments, at least one column of first through structures THV1 and at least one column of second through structures THV2 may be alternately arranged.
The distance between the electrode isolation regions WLC may be greater than the width W3 of FIG. 8A or 9A.
First sides (e.g. the top surfaces) of the conductive patterns of the electrode isolation regions WLC may be connected to electrode isolation region contact lines WLCL via electrode isolation region contact plugs WLC_PG and electrode isolation pads WLC_PAD, and second sides (e.g. the bottom surfaces) of the conductive patterns of the electrode isolation regions WLC may be connected to common electrode plates CSP of horizontal semiconductor layers 150.
Referring to FIG. 10B, in some embodiments, the through structures THV may be arranged in at least one row and at least one column, between the electrode isolation regions WLC, to be spaced at regular intervals in the direction D2. The through structures THV may also be spaced at regular intervals in the direction D1, between the electrode isolation regions WLC. First sides (e.g. the top surfaces) of the first through structures THV1 and first sides (e.g. the top surfaces) of the second through structures THV2 may be connected first through channel contact lines TH_L1 and second through channel contact lines TH_L2, respectively, and second sides (e.g. the bottom surfaces) of the first through structures THV1 and second sides (e.g. the bottom surfaces) of the second through structures THV2 may be connected to wiring lines 116 in a peripheral logic structure PS.
In response to a first voltage being applied to the first through channel contact lines TH_L1 and a second voltage, which is different from the first voltage, being applied to the second through channel contact lines TH_L2, the second voltage is applied to electrode pads (EP1 through EP7) that are stacked, via the second through channel contact lines THL_2. That is, capacitances may be generated between the first through structures THV1 and the electrode pads (EP1 through EP7). The capacitances may be connected to a peripheral circuit TR via the wiring lines 116.
Referring to FIG. 10C, in some embodiments, through structures THV may be arranged in at least one row and at least one column, between the electrode isolation regions WLC, to be spaced at regular intervals in the direction D2. The through structures THV may also be spaced at regular intervals in the direction D1, between the electrode isolation regions WLC. First sides (e.g. the top surfaces) of the first through structures THV1 and first sides (e.g. the top surfaces) of the second through structures THV2 may be connected first through channel contact lines TH_L1 and second through channel contact lines TH_L2, respectively, and second sides (e.g. the bottom surfaces) of the first through structures THV1 and second sides (e.g. the bottom surfaces) of the second through structures THV2 may be connected to common electrode plates CSP of horizontal semiconductor layers 150.
In response to a first voltage being applied to the first through channel contact lines TH_L1 and a second voltage, which is different from the first voltage, being applied to the second through channel contact lines TH_L2, the second voltage is applied to electrode pads (EP1 through EP7) that are stacked, via the second through channel contact lines THL_2. That is, capacitances may be generated between the first through structures THV1 and the electrode pads (EP1 through EP7). Also, capacitances may be additionally generated between the common source plates CSP and lowermost interlayer insulating films ILD. The capacitances generated between the first through structures THV1 and the electrode pads (EP1 through EP7) may be connected to a peripheral circuit TR via the common source plates CSP.
Although not specifically illustrated, the semiconductor memory device may include, in the peripheral region FR, a plurality of electrode isolation regions WLC, and the electrode isolation regions WLC may include first electrode isolation regions WLC1, which include conductive patterns and spacers that surround the conductive patterns, and second electrode isolation regions WLC2, which include conductive patterns. The first electrode isolation regions WLC1 and the second electrode isolation regions WLC2 may be alternately arranged in the direction D1.
In some embodiments, first sides (e.g. the top surfaces) of the first electrode isolation regions WLC1 may be connected to first electrode isolation region contact lines second sides (e.g. the bottom surfaces) of the first electrode isolation regions WLC1 may be connected to the common source plates CSP, first sides (e.g. the top surfaces) of the second electrode isolation regions WLC2 may be connected to second electrode isolation region contact lines, and second sides (e.g. the bottom surfaces) of the second electrode isolation regions WLC2 may be connected to the wiring lines 116. In response to the first and second voltages, which are different from each other, being applied to the first electrode isolation region contact lines WLCL1 and the second electrode isolation region contact lines WLCL2, respectively, the second voltage is applied to the electrode pads (EP1 through EP7) via the second electrode isolation regions WLC2. As a result, capacitances may be formed between the first electrode isolation regions WCL1 and the electrode pads (EP1 through EP7). The capacitances may be used in the peripheral circuit TR as capacitors via the wiring lines 116.
In some embodiments, the first sides (e.g. the top surfaces) of the first electrode isolation regions WLC1 may be connected to the first electrode isolation region contact lines WLCL1, the second sides (e.g. the bottom surfaces) of the first electrode isolation regions WLC1 may be connected to the common source plates CSP, the first sides (e.g. the top surfaces) of the second electrode isolation regions WLC2 may be connected to the second electrode isolation region contact lines WLCL2, and the second sides (e.g. the bottom surfaces) of the second electrode isolation regions WLC2 may be connected to the common source plates CSP. In response to the first and second voltages, which are different from each other, being applied to the first electrode isolation region contact lines WLCL1 and the second electrode isolation region contact lines WLCL2, respectively, the second voltage is applied to the electrode pads (EP1 through EP7) via the second electrode isolation regions WLC2. As a result, capacitances may be formed between the first electrode isolation regions WCL1 and the electrode pads (EP1 through EP7). The capacitances may be used in the peripheral circuit TR as capacitors via the common source plates CSP.
FIG. 11 is a block diagram of an exemplary peripheral circuit of FIG. 1.
In some embodiments, capacitances generated between at least some through structures (or at least some electrode isolation regions) and the electrode patterns of stack structures may serve as capacitors in the peripheral circuit 30 included in the semiconductor memory device 10 of FIG. 1. For example, at least some through structures (or at least some electrode isolation regions) may consist of the first electrodes of capacitors, and the electrode patterns of the stack structures may consist of the second electrodes of the capacitors.
Referring to FIG. 11, an exemplary peripheral circuit 300 may include a column logic 310, an internal voltage generator 321, a high voltage generator 322, a pre-decoder 330, a temperature sensor 340, a command decoder 350, an address decoder 360, a moving zone controller 370, a scheduler 380, and a test/measurement circuit 390. The configuration of the peripheral circuit 300 of FIG. 11 is exemplary, and the peripheral circuit 300 may additionally include elements other than those illustrated in FIG. 11 or may have a different configuration from that illustrated in FIG. 11. The peripheral circuit 300 will hereinafter be described with reference to FIGS. 1 and 11.
The column logic 310 may generate a signal for driving the page buffer 35. The pre-decoder 330 may generate a signal for determining the timing of a signal for driving the row decoder 33. The internal voltage generator 321 may generate voltages for use in the semiconductor memory device 10, such as, for example, voltages applied to the wordlines WL and the bitlines BL, reference voltages, and power supply voltages. The high voltage generator 322 may include a charge pump, a regulator, and the like and may generate high voltages for programming or erasing the memory cells of the memory cell array 20. The temperature sensor 340 may detect the temperature of the semiconductor memory device 10 and may output a signal corresponding to the detected temperature.
The command decoder 350 may latch and decode a command signal CMD received from outside the semiconductor memory device 10 and may set an operating mode for the semiconductor memory device 10 based on the decoded command signal. The address decoder 360 may latch and decode an address signal ADDR received from outside the semiconductor memory device 10 and may activate a memory block selected in accordance with the decoded address signal. The moving zone controller 370 may control the application of various voltages to strings included in the memory cell array 20. The scheduler 380 may include a processor or a state machine and may generate a plurality of control signals at appropriate timings in accordance with the operating mode set by the command decoder 350. The test/measurement circuit 390 may test or measure the characteristics of the semiconductor memory device 10 to provide information regarding the characteristics of the semiconductor memory device 10 during the fabrication of the semiconductor memory device 10. The test/measurement circuit 390 may operate in accordance with the command signal CMD. A system including the semiconductor memory device 10 may use the test/measurement circuit 390 to acquire the information regarding the characteristics of the semiconductor memory device 10 at an early stage of operation.
The elements of the peripheral circuit 300 may be disposed in the peripheral logic structure PS of FIG. 2, together with the row decoder 33 and the page buffer 35 of FIG. 1.
FIG. 12 is a block diagram of a storage device including a 3D semiconductor memory device, according to some embodiments of the present disclosure.
Referring to FIG. 12, in some embodiments, the storage device may be a solid state drive (SSD) system 1000.
The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may transmit signals to, and receive signals from, the host 1100 via a signal connector and may receive power via a power connector.
The SSD 1200 may include an SSD controller 1210, an auxiliary power device 1220, and a plurality of memory devices 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 may be VNAND flash memory devices and may be implemented in accordance with the embodiments of FIGS. 1 through 11. Accordingly, the memory devices 1230, 1240, and 1250 may have a high integration density.

Claims

A three-dimensional, 3D, semiconductor memory device comprising:
a peripheral logic structure (PS) disposed on a substrate (100) and including a plurality of peripheral circuits;

horizontal semiconductor layers (150) disposed on the peripheral logic structure;

a plurality of stacks of mold layers and electrode pads (EP1-EP7) that are alternately stacked in a first direction on the horizontal semiconductor layers,

a plurality of electrode isolation regions (WLC) extending in the first direction and a second direction and separating the plurality of stacks, the electrode isolation regions being connected to the horizontal semiconductor layers; and

a plurality of through structures (THV) disposed on the peripheral logic structure to penetrate the stacks in the first direction, each of the through structures having a first side connected to through channel contact lines (TH_L)

wherein the electrode pads are arranged to form capacitors respectively with at least one of the electrode isolation regions or with at least one of the through structures.
The 3D semiconductor memory device of claim 1, wherein
each of the electrode isolation regions includes a conductive pattern and spacers (WLCI), which surround sidewalls of the conductive pattern, and
each of the through structures includes a conductive region, which is connected to each of the electrode pads.
The 3D semiconductor memory device of claim 1, wherein
each of the electrode isolation regions includes a conductive pattern, which is connected to each of the electrode pads, and
each of the through structures includes a conductive region and a through insulating film (THI), which surrounds sidewalls of the conductive region.
The 3D semiconductor memory device of claim 1, wherein
the electrode isolation regions include a first electrode isolation region, which includes a conductive pattern and spacers surrounding sides of the conductive pattern and is isolated from each of the electrode pads, and a second electrode isolation region, which includes a conductive pattern and is connected to each of the electrode pads, and
each of the through structures includes a conductive region and is connected to each of the electrode pads.
The 3D semiconductor memory device of claim 1, wherein
the through structures include a first through structure, which includes a conductive region and a through insulating film surrounding sidewalls of the conductive region and is isolated from each of the electrode pads, and a second through structure, which includes a conductive region and is connected to each of the stacks, and
the first and second through structures are alternately arranged between at least two electrode isolation regions.
The 3D semiconductor memory device of any preceding claim, wherein a second side of the through structures are each connected to the horizontal semiconductor layers respectively.
The 3D semiconductor memory device of any of claims 1 to 5, wherein
the through structures include a third through structure, which has a second side connected to one of the horizontal semiconductor layers, and a fourth through structure, which has a second side connected to one of wiring lines in the peripheral logic structure, and
the third and fourth through structures are alternately arranged.
The 3D semiconductor memory device of any preceding claim, further comprising two adjacent electrode isolation regions between which there are no through structures, wherein a distance between two adjacent electrode isolation regions between which there are through structures is greater than a distance between the two adjacent electrode isolation regions when there are no through structures.
The 3D semiconductor memory device of claim 8, wherein the distance between the electrode isolation regions when there are through structures is three or more times greater than the distance between the two adjacent electrode isolation regions when there are no through structures.
A three-dimensional, 3D, semiconductor memory device comprising:
a plurality of stacks in which interlayer isolation films and electrode pads (EP1-EP7) are alternately stacked in a first direction on horizontal semiconductor layers, the plurality of stacks including a memory cell array region (MCR) and a peripheral region (FR);

a plurality of electrode isolation regions (WLC) extending in a second direction, the electrode isolation regions being spaced apart from one another in a third direction to separate the stacks; and

a plurality of through structures (THV) disposed in the peripheral region, between at least two adjacent electrode isolation regions, to penetrate the stacks in the first direction, the through structures having first sides connected to through channel contacts,

wherein in the peripheral region, the stacks are stacked to have the same width in the second and third directions.
The 3D semiconductor memory device of claim 10, wherein the through structures have second sides connected to the horizontal semiconductor layers or to wiring lines below the horizontal semiconductor layers respectively.
The 3D semiconductor memory device of either of claims 10 or 11, wherein
each of the electrode isolation regions includes a conductive pattern, which penetrates the stacks in the first direction, and spacers (WLCI), which surround sidewalls of the conductive pattern, and
each of the through structures includes a conductive region, which is connected to each of the electrode pads.
The 3D semiconductor memory device of either of claims 10 or 11, wherein
each of the electrode isolation regions includes a conductive pattern, which penetrates the stacks and is connected to each of the electrode pads, and
each of the through structures includes a conductive region and a through insulating film, which surrounds sides of the conductive region, and is thus isolated from each of the electrode pads.
A three-dimensional (3D) semiconductor memory device comprising:
at least one peripheral region (FR) in which mold layers and electrode pads (EP1-EP7) are alternately arranged on horizontal semiconductor layers (150);

a plurality of electrode isolation regions extending in the peripheral region in a wordline direction and a bitline direction and spaced apart from one another;

a mold region disposed between two adjacent electrode isolation regions among the plurality of the electrode isolation regions; and

a plurality of through structures vertically penetrating the mold region respectively,

wherein the electrode pads form a capacitor with at least one of the through structures or with one of the electrode isolation regions.
The 3D semiconductor memory device of claim 14, wherein in the peripheral region, the electrode pads and the mold layers are stacked to have the same length in the wordline direction and the bitline direction on the horizontal semiconductor layers.