KR20230081555A - Nonvolatile memory device - Google Patents

Abstract

A nonvolatile memory device, according to an embodiment of the present invention, may comprise: a first semiconductor structure which comprises a memory cell area, containing a first semiconductor substrate and a plurality of memory cells placed on a top surface of the first semiconductor substrate, and a first metal pad placed on an upper part of the memory cell area; a second semiconductor structure which comprises a second semiconductor substrate, a page buffer placed on a top surface of the second semiconductor substrate, and a second metal pad bonded with the first metal pad; and a third semiconductor structure which comprises a third semiconductor substrate, a buffer memory and peripheral circuits formed on a top surface of the third semiconductor substrate, and a third metal pad connected to the peripheral circuits through a connection via penetrating the third semiconductor substrate, and is connected to the second semiconductor structure by a connection structure penetrating the second semiconductor substrate. The page buffer may comprise a plurality of vertical transistors defined by a source area, a channel area, and a drain area which are sequentially stacked in the vertical direction. Accordingly, the page buffer is placed by utilizing a space as much as possible in the nonvolatile memory device, according to one embodiment of the present invention, such that an issue of increasing the size of the page buffer caused by the increase in a storage capacity can be solved.

Description

Non-volatile memory device {NONVOLATILE MEMORY DEVICE}

The present invention relates to a non-volatile memory device.

Recent non-volatile memory devices require a high degree of integration and high speed in order to process more data in a shorter time. In order to improve integration and increase storage capacity of the nonvolatile memory device, the number of channel structures included in each of a plurality of memory blocks included in the nonvolatile memory device may be increased. However, as the number of channel structures including memory cells increases, the number of page buffers that sense values stored in memory cells may also increase. When the number of page buffers increases, a size of a peripheral circuit area of the nonvolatile memory device may increase more than necessary.

One of the problems to be achieved by the technical idea of the present invention is to increase the number of memory cells capable of simultaneously reading and writing data in parallel in a page buffer by reducing the number of memory cell strings connected to each page buffer, and furthermore, It is an object of the present invention to provide a non-volatile memory device capable of reducing read and write operation times of memory cells.

A nonvolatile memory device according to an embodiment of the present invention includes a first semiconductor substrate, a memory cell region including a plurality of memory cells disposed on the first semiconductor substrate, and a first memory cell region disposed above the memory cell region. A first semiconductor structure including a first metal pad, wherein the plurality of memory cells are defined by stacked gate electrodes spaced apart from each other and channel structures penetrating the gate electrodes and connected to the first semiconductor substrate; A second semiconductor structure including a semiconductor substrate, a page buffer disposed on the second semiconductor substrate, and a second metal pad bonded to the first metal pad, and a third semiconductor substrate formed on the third semiconductor substrate A third semiconductor structure including a buffer memory and peripheral circuits, and a third metal pad connected to the peripheral circuits through a connection via penetrating the third semiconductor substrate, wherein the second semiconductor structure and the The third semiconductor structures are connected to each other by a connection structure penetrating the second semiconductor substrate, and the page buffer is configured in a first direction in which the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are connected. It includes a plurality of vertical transistors defined by sequentially stacked source regions, channel regions, and drain regions.

A nonvolatile memory device according to an embodiment of the present invention includes a first semiconductor substrate, a memory cell region including a plurality of memory cells disposed on the first semiconductor substrate, and a first memory cell region disposed above the memory cell region. A first semiconductor structure including a first metal pad, wherein the plurality of memory cells are defined by stacked gate electrodes spaced apart from each other and channel structures penetrating the gate electrodes and connected to the first semiconductor substrate; A second semiconductor structure including a semiconductor substrate, a page buffer disposed on the second semiconductor substrate, and a second metal pad bonded to the first metal pad, and a third semiconductor substrate formed on the third semiconductor substrate a buffer memory, peripheral circuits disposed above the buffer memory, and a third metal pad connected to the peripheral circuits through a connection via penetrating the third semiconductor substrate; A third semiconductor structure connected to the second semiconductor structure by a connection structure therethrough, wherein the peripheral circuits include a row decoder connected to the page buffer and other peripheral circuits for controlling the plurality of memory cells; , The third semiconductor structure is a plurality defined by a source region, a channel region, and a drain region sequentially stacked in a first direction to which the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are connected. of vertical transistors.

A nonvolatile memory device according to an embodiment of the present invention includes a first semiconductor substrate, a memory cell region including a plurality of memory cells disposed on the first semiconductor substrate, and a first memory cell region disposed above the memory cell region. A first semiconductor structure including a first metal pad, wherein the plurality of memory cells are defined by stacked gate electrodes spaced apart from each other and channel structures penetrating the gate electrodes and connected to the first semiconductor substrate; A second semiconductor structure including a semiconductor substrate, a page buffer disposed on the second semiconductor substrate, and a second metal pad bonded to the first metal pad, and a third semiconductor substrate formed on the third semiconductor substrate a third semiconductor structure including a buffer memory, a row decoder, and other peripheral circuits, and a third metal pad connected to the peripheral circuits through a connection via penetrating the third semiconductor substrate; A decoder is disposed in the center of the second semiconductor substrate to be surrounded by the page buffer, and the plurality of memory cells are sequentially connected to the page buffer, the row decoder, and the other peripheral circuits.

A nonvolatile memory device according to an embodiment of the present invention includes a stack of a first semiconductor structure including a memory cell region, a second semiconductor structure including a page buffer, and a third semiconductor structure including a buffer memory and peripheral circuits. By being implemented as a structure, it is possible to secure the space necessary for arranging the page buffer.

A nonvolatile memory device according to an exemplary embodiment of the present invention can maximize space by implementing a page buffer using vertical transistors.

A nonvolatile memory device according to an exemplary embodiment of the present invention may maximize space utilization by implementing a buffer memory and/or peripheral circuits using vertical transistors.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a perspective view simply showing the structure of a non-volatile memory device.
2 and 3 are schematic diagrams illustrating a non-volatile memory device according to an exemplary embodiment of the present invention.
4A and 4B are diagrams for explaining a vertical transistor included in a nonvolatile memory device according to an exemplary embodiment of the present invention.
4C is a diagram for explaining vertical transistors included in a page buffer in a nonvolatile memory device according to an exemplary embodiment of the present invention.
5 is a block diagram illustrating a memory system including a nonvolatile memory device according to an exemplary embodiment of the present invention.
6 is a block diagram simply illustrating a non-volatile memory device according to an exemplary embodiment of the present invention.
7 is an equivalent circuit diagram of a memory block included in a nonvolatile memory device according to an embodiment of the present invention.
8 is a diagram for explaining a wafer bonding method in a nonvolatile memory device according to an embodiment of the present invention.
9 to 12 are views simply illustrating a non-volatile memory device according to an exemplary embodiment of the present invention.
13 and 14 are diagrams simply illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.
15 and 16 are diagrams simply illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.
17 and 18 are schematic diagrams illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.
19A to 19E are diagrams for explaining a process of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a perspective view simply showing the structure of a non-volatile memory device.

Referring to FIG. 1 , a nonvolatile memory device may have a cell on periphery (COP) structure. For example, a nonvolatile memory device having a COP structure includes a memory cell area (CELL) including a plurality of memory cells formed in a 3D structure and a peripheral circuit area (PERI) including peripheral circuits implemented with planar transistors. ) may be included.

The peripheral circuit area PERI may include a page buffer PB, a row decoder XDEC, and other peripheral circuits OC. The row decoder (XDEC) may be disposed below a stepped structure in which a step is formed to select a word line, and a page buffer (PB) and other peripheral circuits (OC) may be disposed between the row decoder (XDEC). there is.

Recently, as the number of memory cells included in the nonvolatile memory device increases and the number of bits stored per memory cell increases, the storage capacity of the nonvolatile memory device is increasing. Accordingly, when using the existing page buffer (PB), the time required for read/write operations may increase, and it is necessary to increase the size of the page buffer (PB) to ensure the operational performance of the non-volatile memory device. there may be

In addition, the size of a storage device including a non-volatile memory device tends to decrease due to integration. Therefore, it may be necessary to secure a sufficient space in the peripheral circuit area PERI.

A non-volatile memory device according to an embodiment of the present invention has a 3-stack structure in which a page buffer (PB) is formed in a separate semiconductor structure and three semiconductor structures including the page buffer PB are stacked. can secure enough. In addition, since the latch structure included in the page buffer PB is implemented using vertical transistors, the space of the peripheral circuit area PERI can be maximally utilized and the existing space shortage problem can be solved.

2 and 3 are schematic diagrams illustrating a non-volatile memory device according to an exemplary embodiment of the present invention.

Referring to FIGS. 2 and 3 , a nonvolatile memory device according to an embodiment of the present invention includes a first semiconductor structure 110 having a stacked structure in a first direction (eg, Z direction), and a second semiconductor structure ( 120), and a third semiconductor structure 130.

The first semiconductor structure 110 may include a first semiconductor substrate 111 and an upper region of the first semiconductor substrate. The upper region of the first semiconductor substrate may include a memory cell region 112 in which a plurality of memory cells are disposed and a first metal pad 119 disposed above the memory cell region 112 .

The first semiconductor substrate 111 may have a top surface extending in a second direction (eg, an X direction) and a third direction (eg, a Y direction). The first semiconductor substrate 111 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the first semiconductor substrate 111 may include silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or another suitable material. Alternatively, the first semiconductor substrate 111 may be provided with a polycrystalline semiconductor layer such as a polycrystalline silicon layer or an epitaxial layer. The semiconductor substrates 111 , 121 , and 131 included in the semiconductor structures 110 , 120 , and 130 included in the nonvolatile memory device 100 may include the same material. However, this is merely an example and may not be limited.

The plurality of memory cells included in the memory cell region 112 include gate electrodes spaced apart from each other and stacked on the first semiconductor substrate 111 , and channel structures passing through the gate electrodes and connected to the first semiconductor substrate 111 . (CH). That is, the plurality of memory cells may be memory cells constituting a vertical NAND flash memory (VNAND).

The gate electrodes may include electrodes sequentially forming a ground select transistor, a plurality of memory cells, and a string select transistor from the first semiconductor substrate 111 . The number of gate electrodes constituting a plurality of memory cells may be determined according to the capacity of the nonvolatile memory device 100 . In this case, the gate electrodes may extend to different lengths to form a stepped structure, and the gate electrodes may be connected to the gate contacts through exposed ends. Gate electrodes and gate contacts in the memory cell region 112 may be covered by an insulating layer made of an insulating material.

The gate electrodes may include a metal material, such as tungsten (W). Depending on the embodiment, the gate electrodes may include polycrystalline silicon or a metal silicide material. For example, the gate electrodes may further include an anti-diffusion layer, and for example, the anti-diffusion layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. Meanwhile, interlayer insulating layers disposed between the gate electrodes may include an insulating material such as silicon oxide or silicon nitride.

Each of the channel structures CH constitutes one memory cell string and may be spaced apart from each other while forming rows and columns. The channel structures CH may be arranged to form a lattice pattern in an X-Y plane or may be arranged in a zigzag shape in one direction. The channel structures CH may have a pillar shape and may have inclined side surfaces that become narrower closer to the first semiconductor substrate 111 according to an aspect ratio.

Meanwhile, the non-volatile memory device 100 according to an embodiment of the present invention includes a charge storage layer composed of a conductive floating gate as well as a charge storage layer composed of an insulating film (Charge Trap Flash; CTF). ) can also be applied.

The second semiconductor structure 120 may include the second semiconductor substrate 121 and an upper region of the second semiconductor substrate. The upper region of the second semiconductor substrate may include the page buffer 122 , the row decoder 123 , and the second metal pad 129 of the nonvolatile memory device 100 .

In the nonvolatile memory device 100 according to an embodiment of the present invention, the page buffer 122 is separately disposed in the second semiconductor structure 120 to increase the storage capacity of the nonvolatile memory device 100. ), it is possible to minimize the spatial constraints when increasing the size of . Accordingly, the nonvolatile memory device 100 may shorten read operations and write operations of a plurality of memory cells.

Referring to FIG. 2 , a row decoder 123 may be disposed in the center of the second semiconductor substrate 121 to be surrounded by the page buffer 122 to load the page buffer 122 disposed on both sides. However, this is merely an example and may not be limited.

The second metal pad 129 may be bonded to the first metal pad 119 in the first direction. The first metal pad 119 and the second metal pad 129 may connect the first semiconductor structure 110 and the second semiconductor structure 120 by a wafer bonding method.

The wafer bonding method may form a direct connection path having a short connection length between the first semiconductor structure 110 and the second semiconductor structure 120 . Accordingly, the wafer bonding method can improve the input/output speed of data and control signals while removing the delay caused by the chip interface and reducing power consumption.

Meanwhile, the first metal pad 119 and the second metal pad 129 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or the like. Each of the first metal pad 119 and the second metal pad 129 may be electrically separated by adjacent layers in a second direction (eg, X direction) and/or a third direction (eg, Y direction). As an example, the layer may include silicon oxide, silicon nitride, low-k dielectric, and the like.

Referring to FIG. 3 , the nonvolatile memory device 100 according to an exemplary embodiment may further include a pad out layer disposed on a lower surface of the second semiconductor substrate 121 . As an example, the pad out layer may include a dielectric material such as silicon oxide, silicon nitride, or a low-k dielectric.

The pad-out layer may include one or more contact pads 128 to electrically connect the memory cell region 112 and/or the page buffer 122 to an external circuit. Since the first semiconductor structure 110 and the second semiconductor structure 120 are electrically connected to each other by wafer bonding, the electrical signal of the external circuit applied to the contact pad 128 is included in the first semiconductor structure 110. may be transferred to the memory cell region 112. That is, the contact pad 128 may transmit an electrical signal between the nonvolatile memory device 100 and an external circuit for pad-out.

However, this is merely an example and may not be limited. For example, the pad-out layer may be disposed on the lower surface of the first semiconductor substrate 111 . At this time, the electrical signal of the external circuit applied to the contact pad 128 included in the pad-out layer passes through the first metal pad 119 and the second metal pad 129 connected by a wafer bonding method to the second semiconductor structure ( 120) can be passed on.

The third semiconductor structure 130 may include the third semiconductor substrate 131 and an upper region of the third semiconductor substrate. An upper region of the third semiconductor substrate may include a buffer memory 132 and other peripheral circuits 134 , and the third semiconductor structure 130 may include connection vias 138 penetrating the third semiconductor substrate 131 . It may include a third metal pad 139 connected to peripheral circuits through.

Meanwhile, the second semiconductor substrate 121 and the third semiconductor substrate 131 may be electrically connected by a connection structure 140 penetrating the second semiconductor substrate 121 . Referring to FIG. 3 , the connection structure 140 completely penetrates the second semiconductor substrate 121 and the pad-out layer, and connects a contact extending from the wiring layer of the second semiconductor structure 120 to the third semiconductor structure 130 . It can be connected between wiring layers.

Similar to the wafer bonding method, the connection structure 140 may form a direct connection path having a short connection length between the second semiconductor structure 120 and the third semiconductor structure 130 . Accordingly, the connection structure 140 can improve the input/output speed of data and control signals while removing delay caused by the chip interface and reducing power consumption.

As an example, referring to FIG. 2 , other peripheral circuits 134 may refer to peripheral circuits other than circuits such as the sense amplifier 133 and the multiplexer 135, such as a write driver and a charge pump. , but is not limited thereto, and as shown in FIG. 3 , other peripheral circuits 134 may mean peripheral circuits including circuits such as sense amplifiers and multiplexers. Other peripheral circuits 134 may be implemented by arbitrary elements (eg, diodes, resistors, or capacitors) including a plurality of transistors disposed on the third semiconductor substrate 131 and wirings.

The buffer memory 132 may include a plurality of memory cells included in the memory cell area 112 and other memory cells. The buffer memory 132 temporarily stores data stored in or read from the memory cell area 112 to adjust signal and data transmission speeds between the non-volatile memory device and the external device 10 . there is.

Referring to FIG. 3 , in the nonvolatile memory device 100 according to an embodiment of the present invention, the buffer memory 132 may include dynamic random access memory (DRAM). Accordingly, each of the memory cells included in the buffer memory 132 may be implemented by a selection transistor and a capacitor.

However, this is only one embodiment and is not limited, and the buffer memory 132 may include static random access memory (SRAM), magnetoresistive random access memory (MRAM), and phase-change RAM in addition to DRAM. It may include a memory device operating on a different principle, such as change random access memory (PRAM). Accordingly, elements included in the buffer memory 132 and their structures may vary.

The nonvolatile memory device 100 according to an embodiment of the present invention may exchange command (CMD), address (ADDR), and control (CTRL) signals with the external device 10 through the third metal pad 139. In addition, the signals may be exchanged between the plurality of memory cells and peripheral circuits through the connection structure 140 . The external device 10 may control overall operations of the nonvolatile memory device 100 based on signals exchanged with the nonvolatile memory device 100 .

In the nonvolatile memory device 100 according to an embodiment of the present invention, a plurality of memory cells may be sequentially connected to a page buffer 122 , a row decoder 123 , and other peripheral circuits 134 . At this time, the page buffer 122 may be disposed on both sides of the row decoder 123. However, this is merely an example and may not be limited.

Meanwhile, at least some of the circuits included in the nonvolatile memory device 100 include a plurality of vertical transistors defined by sequentially stacked source regions, channel regions, and drain regions in a first direction (eg, Z direction). (Vertical Transistor) may be included.

For example, the page buffer 122 and/or the row decoder 123 included in the nonvolatile memory device 100 according to an embodiment of the present invention may be implemented with a plurality of vertical transistors. Through this, the nonvolatile memory device 100 according to an embodiment of the present invention can maximize the space where the page buffer 122 is implemented.

4A and 4B are diagrams for explaining a vertical transistor included in a nonvolatile memory device according to an exemplary embodiment of the present invention. 4C is a diagram for explaining vertical transistors included in a page buffer in a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2 together, at least some of the circuits included in the second semiconductor structure 120 of the nonvolatile memory device 100 according to an exemplary embodiment of the present invention may be implemented by vertical transistors. For example, the page buffer 122 may include a plurality of page buffers corresponding to a plurality of memory cells, and each of the plurality of page buffers may include a latch structure implemented with four vertical transistors. For example, a plurality of page buffers may correspond 1:1 to a plurality of memory cells. However, this is merely an example and may not be limited.

Referring to FIGS. 4A and 4B , among the vertical transistors, an NMOS transistor may be implemented as shown in FIG. 4A and a PMOS transistor may be implemented as shown in FIG. 4B.

The vertical transistor may be implemented by a first source/drain region SD1, a first gate electrode G1, a second gate electrode G2, and a third source/drain region SD3 stacked in the vertical direction. . Meanwhile, referring to FIG. 4B , the vertical transistor may be implemented to have a structure in which a metal structure is connected to the second source/drain region SD2 . In the vertical transistor, a channel region surrounded by the first gate electrode G1 and/or the second gate electrode G2 may be formed of a nanowire.

Referring to FIG. 4C , the second semiconductor structure 120 included in the nonvolatile memory device 100 according to an embodiment of the present invention includes wiring structures M0, M1, M2, M3, M4) may be included. Circuits included in the semiconductor structures 120 and 130 may be formed by connecting the wiring structures M0 , M1 , M2 , M3 , and M4 and other devices.

For example, a latch structure included in the page buffer 122 included in the second semiconductor structure 120 may be implemented with four vertical transistors. The vertical transistors may be disposed two by two in the vertical direction. For example, the first transistor TR1 and the second transistor TR2 may be NMOS transistors shown in FIG. 4A, and the third transistor TR3 and TR4 may be PMOS transistors shown in FIG. 4B. can However, this is merely an example and may not be limited.

Meanwhile, since structures such as an inverter and a buffer can be implemented using vertical transistors, other peripheral circuits included in the row decoder 123 and the third semiconductor structure 130 in addition to the page buffer 122 are also vertical transistors. can be formed

5 is a block diagram illustrating a memory system including a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , the memory system 1 may include a memory device MEM and a memory controller CTRL. The memory system 1 may support a plurality of channels CH1 to CHm, and the memory device MEM and the memory controller CTRL may be connected through the plurality of channels CH1 to CHm. For example, the memory system 1 may be implemented as a storage device such as a solid state drive (SSD).

The memory device MEM may include a plurality of nonvolatile memory devices NVM11 to NVMmn. Each of the nonvolatile memory devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a corresponding way. For example, the nonvolatile memory devices NVM11 to NVM1n are connected to the first channel CH1 through ways W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n are connected to ways W21 to W1n. W2n) may be connected to the second channel CH2. In an exemplary embodiment, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as an arbitrary memory unit capable of operating according to individual commands from the memory controller CTRL. For example, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as a chip or die, but the present invention is not limited thereto.

The memory controller CTRL may transmit and receive signals to and from the memory device MEM through a plurality of channels CH1 to CHm. For example, the memory controller CTRL transmits commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device MEM through channels CH1 to CHm. Data DATAa to DATAm may be transmitted to the device MEM or may be received from the memory device MEM.

The memory controller CTRL may select one of the nonvolatile memory devices NVM11 to NVMmn connected to the corresponding channel through each channel and transmit/receive signals to and from the selected nonvolatile memory device. For example, the memory controller CTRL may select the nonvolatile memory device NVM11 among the nonvolatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller CTRL transmits the command CMDa, address ADDRa, and data DATAa to the selected nonvolatile memory device NVM11 through the first channel CH1, or transmits the selected nonvolatile memory device NVM11. Data DATAa may be received from

The memory controller CTRL may transmit and receive signals to and from the memory device MEM in parallel through different channels. For example, while the memory controller CTRL transmits the command CMDa to the memory device MEM through the first channel CH1, the command CMDb is sent to the memory device MEM through the second channel CH2. can transmit. For example, the memory controller CTRL receives data DATAb from the memory device 10 through a second channel CH2 while receiving data DATAa from the memory device 10 through a first channel CH1. can receive

The memory controller CTRL may control overall operations of the memory device MEM. The memory controller CTRL may control each of the nonvolatile memory devices NVM11 to NVMmn connected to the channels CH1 to CHm by transmitting a signal to the channels CH1 to CHm. For example, the memory controller CTRL may control a selected one of the nonvolatile memory devices NVM11 to NVM1n by transmitting the command CMDa and the address ADDRa through the first channel CH1.

Each of the nonvolatile memory devices NVM11 to NVMmn may operate under the control of the memory controller CTRL. For example, the nonvolatile memory device NVM11 may program the data DATAa according to the command CMDa and the address ADDRa provided through the first channel CH1. For example, the nonvolatile memory device NVM21 reads data DATAb according to the command CMDb and address ADDRb provided through the second channel CH2, and transfers the read data DATAb to a memory controller ( CTRL).

5 shows that the memory device MEM communicates with the memory controller CTRL through m channels and includes n nonvolatile memory devices corresponding to each channel; The number and number of nonvolatile memory devices connected to one channel may be variously changed.

6 is a block diagram simply illustrating a non-volatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , a nonvolatile memory device 100 according to an embodiment of the present invention includes a memory cell area including a memory cell array 112 and a peripheral circuit area including peripheral circuits 150. can do.

The peripheral circuits 150 disposed in the peripheral circuit area of the nonvolatile memory device 100 include a row decoder 123, a page buffer 122, an input/output buffer 151, a voltage generator 152, and a control logic circuit ( 153) may be included. Although not shown in FIG. 6 , the nonvolatile memory device 100 may further include a column logic, a pre-decoder, and a temperature sensor.

The control logic circuit 153 may overall control various operations within the non-volatile memory device. The control logic circuit 153 may output various control signals in response to the command CMD and/or the address ADDR input from the memory controller. For example, the control logic circuit 153 may output a voltage control signal CTRL_VOL, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array 112 may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. The memory cell array 112 may be connected to the page buffer 122 through bit lines BL, and may be connected to the page buffer 122 through word lines WL, string select lines SSL, and ground select lines GSL. It can be connected to the row decoder 123.

In the nonvolatile memory device 100 according to an embodiment of the present invention, the memory cell array 112 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. . Each NAND string may include a plurality of memory cells respectively connected to word lines WL vertically stacked on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference. are combined For example, the memory cell array 112 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings disposed along row and column directions.

The page buffer 122 may include a plurality of page buffers, and the plurality of page buffers may be respectively connected to a plurality of memory cells through a plurality of bit lines BL. The page buffer 122 may select at least one bit line from among the bit lines BL in response to the column address Y-ADDR. The page buffer 122 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a write operation, the page buffer 122 may apply a bit line voltage corresponding to data to be written to a selected bit line. During a read operation, the page buffer 122 may sense data stored in a plurality of memory cells by sensing a current or voltage of a selected bit line.

The voltage generator 152 may generate various types of voltages for performing write, read, write verify, and erase operations based on the voltage control signal CTRL_VOL. For example, the voltage generator 152 may generate a write voltage, a read voltage, a write verify voltage, an erase voltage, and the like as the word line voltage VWL.

The row decoder 123 may select one of the plurality of word lines WL and select one of the plurality of string select lines SSL in response to the row address X-ADDR. For example, during a write operation, the row decoder 123 may apply a write voltage and a write verify voltage to the selected word line, and during a read operation, may apply a read voltage to the selected word line.

7 is an equivalent circuit diagram of a memory block included in a nonvolatile memory device according to an embodiment of the present invention.

The memory block BLKi shown in FIG. 7 represents a 3D memory block formed in a 3D structure on a semiconductor substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the semiconductor substrate.

Referring to FIG. 7 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. 4 illustrates that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., MC8, but is not necessarily limited thereto.

The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding gate lines GTL1 , GTL2 , ... , and GTL8 , respectively. The gate lines GTL1 , GTL2 , ..., GTL8 may correspond to word lines, and some of the gate lines GTL1 , GTL2 , ... , GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other. 7 shows that the memory block BLK is connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2, BL3, but is not necessarily limited thereto. no.

8 is a diagram for explaining a wafer bonding method in a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 8 , the nonvolatile memory device 1000 may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a cell region (CELL) is fabricated on a first wafer, a lower chip including a peripheral circuit area (PERI) is fabricated on a second wafer different from the first wafer, and then the upper chip is fabricated. This may mean connecting a chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

Referring to FIGS. 2 and 3 together, the cell region CELL included on the first semiconductor substrate 1810 of the nonvolatile memory device 1000 may correspond to the memory cell region 112 and the first semiconductor structure (110) may be included. Meanwhile, the peripheral circuit region PERI included on the second semiconductor substrate 1710 may correspond to peripheral circuits and may correspond to the second semiconductor structure 120 and the third semiconductor structure 130 . Also, the bonding metal may correspond to the first metal pad 119 and the second metal pad 129 .

Each of the peripheral circuit area PERI and the cell area CELL of the nonvolatile memory device 1000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. there is.

The peripheral circuit region PERI includes a second semiconductor substrate 1710, an interlayer insulating layer 1715, a plurality of circuit elements 1720a, 1720b, and 1720c formed on the second semiconductor substrate 1710, and a plurality of circuit elements. (1720a, 1720b, 1720c) the first metal layers 1730a, 1730b, 1730c connected to each other, and the second metal layers 1740a, 1740b, 1740c formed on the first metal layers 1730a, 1730b, 1730c can include In one embodiment, the first metal layers 1730a, 1730b, and 1730c may be formed of tungsten having a relatively high electrical resistivity, and the second metal layers 1740a, 1740b, and 1740c may be made of copper having a relatively low electrical resistivity. can be formed

In this specification, only the first metal layers 1730a, 1730b, and 1730c and the second metal layers 1740a, 1740b, and 1740c are shown and described, but are not limited thereto, and the second metal layers 1740a, 1740b, and 1740c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 1740a, 1740b, and 1740c are made of aluminum having a lower electrical resistivity than copper forming the second metal layers 1740a, 1740b, and 1740c. can be formed

The interlayer insulating layer 1715 covers the plurality of circuit elements 1720a, 1720b, and 1720c, the first metal layers 1730a, 1730b, and 1730c, and the second metal layers 1740a, 1740b, and 1740c to cover the second semiconductor. It is disposed on the substrate 1710 and may include an insulating material such as silicon oxide or silicon nitride.

Lower bonding metals 1771b and 1772b may be formed on the second metal layer 1740b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1771b and 1772b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 1871b and 1872b of the cell area CELL by a bonding method. , The lower bonding metals 1771b and 1772b and the upper bonding metals 1871b and 1872b may be formed of aluminum, copper, or tungsten.

The cell area CELL may provide at least one memory block. The cell region CELL may include a first semiconductor substrate 1810 and a common source line 1820 . A plurality of word lines 1831 to 1838 (1830) may be stacked on the first semiconductor substrate 1810 along a direction perpendicular to the upper surface of the first semiconductor substrate 1810 (Z-axis direction). String select lines and a ground select line may be disposed on upper and lower portions of the word lines 1830 , and a plurality of word lines 1830 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH extends in a direction (Z-axis direction) perpendicular to the top surface of the first semiconductor substrate 1810 to form word lines 1830, string select lines, and ground. Can pass through selection lines. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 1850c and the second metal layer 1860c. For example, the first metal layer 1850c may be a bit line contact, and the second metal layer 1860c may be a bit line. In one embodiment, the bit line 1860c may extend along a third direction (eg, Y direction) parallel to the top surface of the first semiconductor substrate 1810 .

In the embodiment shown in FIG. 8 , an area where the channel structure CH and the bit line 1860c are disposed may be defined as a bit line bonding area BLBA. The bit line 1860c may be electrically connected to the circuit elements 1720c providing the page buffer 1893 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 1860c is connected to upper bonding metals 1871c and 1872c in the peripheral circuit area PERI, and the upper bonding metals 1871c and 1872c are connected to circuit elements 1720c of the page buffer 1893. It may be connected to the connected lower bonding metals 1771c and 1772c.

In the word line bonding area WLBA, the word lines 1830 may extend along a second direction (eg, an X direction) parallel to the upper surface of the first semiconductor substrate 1810 while being perpendicular to the third direction. It may be connected to the plurality of cell contact plugs 1841 to 1847 (1840). The word lines 1830 and the cell contact plugs 1840 may be connected to each other through pads provided by extending different lengths from at least some of the word lines 1830 along the second direction. A first metal layer 1850b and a second metal layer 1860b may be sequentially connected to upper portions of the cell contact plugs 1840 connected to the word lines 1830 . The cell contact plugs 1840 are connected to peripheral circuits in the word line bonding area WLBA through the upper bonding metals 1871b and 1872b of the cell area CELL and the lower bonding metals 1771b and 1772b of the peripheral circuit area PERI. It may be connected to the area PERI.

The cell contact plugs 1840 may be electrically connected to circuit elements 1720b forming the row decoder 1894 in the peripheral circuit area PERI. In one embodiment, the operating voltage of the circuit elements 1720b forming the row decoder 1894 may be different from the operating voltage of the circuit elements 1720c forming the page buffer 1893. For example, the operating voltage of the circuit elements 1720c forming the page buffer 1893 may be higher than the operating voltage of the circuit elements 1720b forming the row decoder 1894 .

A common source line contact plug 1880 may be disposed in the external pad bonding area PA. The common source line contact plug 1880 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 1820 . A first metal layer 1850a and a second metal layer 1860a may be sequentially stacked on the common source line contact plug 1880 . For example, an area where the common source line contact plug 1880, the first metal layer 1850a, and the second metal layer 1860a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 1705 and 1805 may be disposed in the external pad bonding area PA. Referring to FIG. 8 , a lower insulating film 1701 covering a lower surface of the second semiconductor substrate 1710 may be formed under the second semiconductor substrate 1710, and second input/output pads ( 1705) may be formed. The second input/output pad 1705 is connected to at least one of the plurality of circuit elements 1720a, 1720b, and 1720c arranged in the peripheral circuit area PERI through the second input/output contact plug 1703, and the lower insulating layer 1701 ) may be separated from the second semiconductor substrate 1710. In addition, a side insulating layer may be disposed between the second input/output contact plug 1703 and the second semiconductor substrate 1710 to electrically separate the second input/output contact plug 1703 from the second semiconductor substrate 1710 .

Referring to FIG. 8 , an upper insulating layer 1801 covering the upper surface of the first semiconductor substrate 1810 may be formed on an upper portion of the first semiconductor substrate 1810, and a first input/output pad ( 1805) may be placed. The first input/output pad 1805 may be connected to at least one of the plurality of circuit elements 1720a, 1720b, and 1720c arranged in the peripheral circuit area PERI through the first input/output contact plug 1803. In one embodiment, the first input/output pad 1805 may be electrically connected to the circuit element 1720a.

According to example embodiments, the first semiconductor substrate 1810 and the common source line 1820 may not be disposed in an area where the first input/output contact plug 1803 is disposed. Also, the first input/output pad 1805 may not overlap the word lines 1880 in the first direction (eg, Z direction). Referring to FIG. 5 , the first input/output contact plug 1803 is separated from the first semiconductor substrate 1810 in a direction parallel to the upper surface of the first semiconductor substrate 1810, and the interlayer insulating layer of the cell region CELL ( 1815 and connected to the first input/output pad 1805.

According to embodiments, the second input/output pad 1705 and the first input/output pad 1805 may be selectively formed. For example, the non-volatile memory device 1000 includes only the second input/output pad 1705 disposed on the lower insulating film 1701, or the first input/output pad 1805 disposed on the upper insulating film 1801. may contain only Alternatively, the nonvolatile memory device 1000 may include both the second input/output pad 1705 and the first input/output pad 1805 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists in a dummy pattern, or The top metal layer may be empty.

In the nonvolatile memory device 1000 , in the external pad bonding area PA, the cell area is formed on the uppermost metal layer of the peripheral circuit area PERI corresponding to the upper metal pattern 1872a formed on the uppermost metal layer of the cell area CELL. A lower metal pattern 1773a having the same shape as the upper metal pattern 1872a of the cell may be formed. The lower metal pattern 1773a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the upper metal layer of the cell area CELL corresponds to the lower metal pattern 1773a formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 1872a having the same shape as the lower metal pattern 1773a may be formed.

Lower bonding metals 1771b and 1772b may be formed on the second metal layer 1740b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1771b and 1772b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 1871b and 1872b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the uppermost metal layer of the cell area CELL corresponds to the lower metal pattern 1752 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 1892 having the same shape as the metal pattern 1752 may be formed. A contact may not be formed on the upper metal pattern 1892 formed on the uppermost metal layer of the cell region CELL.

However, the nonvolatile memory device 1000 shown in FIG. 8 is only an example for explaining the wafer bonding method, and the structure of the nonvolatile memory device 1000 according to the wafer bonding method may not be limited to that shown in FIG. 8 . there is.

9 to 12 are views simply illustrating a non-volatile memory device according to an exemplary embodiment of the present invention.

Each of the nonvolatile memory devices 200, 300, 400, 500, 600, 700, and 800 according to embodiments of the present invention shown in FIGS. 9 to 12 is the nonvolatile memory device 100 shown in FIG. ) can respond.

In each embodiment, the page buffer may include a plurality of vertical transistors defined by a source region, a channel region, and a drain region sequentially stacked in a first direction (eg, Z direction). Accordingly, by arranging the page buffer to be connected 1:1 to the memory cell string, even if the speed of outputting data from the page buffer is slower than the speed of applying data to the page buffer, data can be continuously stored in the empty page buffer. there is. However, this is only one embodiment and is not limited, and the structure and arrangement of the page buffer and/or peripheral circuits may vary depending on the embodiment.

Referring to FIG. 9 , the nonvolatile memory device 200 includes a first semiconductor structure 210 including a first semiconductor substrate 211 and a memory cell region 212 , a second semiconductor substrate 221 and a page buffer ( 222), and a third semiconductor substrate 231, a buffer memory 232, and peripheral circuits such as a row decoder 223, a sense amplifier 233, and a multiplexer 235 , and a third semiconductor structure 230 including other peripheral circuits 234 .

Meanwhile, the page buffer 222 may first be connected to a connection portion of the memory cell CELL in order to sense the value of the memory cell. That is, a connection distance between the page buffer 222 and the plurality of memory cells may be shorter than a connection distance between other peripheral circuits and the plurality of memory cells.

In the non-volatile memory device 200 according to an embodiment of the present invention, the page buffer 222 includes a sensing page buffer 222a directly connected to a plurality of memory cells and a serially connected sensing page buffer 222a. At least one general page buffer 222b may be included.

The sensing page buffer 222a and at least one normal page buffer 222b corresponding to each of the plurality of memory cells may be disposed side by side in a first direction (eg, a Z direction). In this case, among the at least one normal page buffer 222b, the normal page buffer 222b most distantly connected to the sensing page buffer 222a may be connected to the bit line BL.

Data input from the external device 10 through the input/output interface may be stored in the buffer memory 232 and then programmed into a plurality of memory cells via the page buffer 222 . However, the multiplexer 235 may determine whether or not to pass through the buffer memory 232 based on characteristics of input data.

For example, when data is stored in all memory cells included in the buffer memory 232, the multiplexer 235 does not pass through the buffer memory 232, but inputs data from the external device 10 to a plurality of memory cells. It can operate to store. However, this is only one embodiment and is not limited, and the operation of the multiplexer 235 may vary depending on characteristics such as data capacity and access period. Also, the multiplexer 235 may include a demultiplexer that sets a data processing path in a similar manner in a read operation.

10 and 11 , nonvolatile memory devices 300 and 400 include first semiconductor structures 310 and 410 including first semiconductor substrates 311 and 411 and memory cell regions 312 and 412; Second semiconductor structures 320 and 420 including second semiconductor substrates 321 and 421 and page buffers 322 and 422, and third semiconductor substrates 331 and 431, buffer memories 332 and 432, and Third semiconductor structures 330, 430 including peripheral circuits, such as row decoders 323, 423, sense amplifiers 333, 433, multiplexers 335, 435, and other peripheral circuits 334, 434 can include

In the nonvolatile memory devices 300 and 400 according to an exemplary embodiment, the page buffers 322 and 422 include a sensing page buffer 322a connected between a plurality of memory cells CELL and a bit line BL; 422a). Meanwhile, the page buffers 322 and 422 may further include normal page buffers 322b and 422b connected to the sensing page buffers 322a and 422a.

Referring to FIG. 10 , the general page buffer 322b of the nonvolatile memory sensor 300 may be included in the second semiconductor structure 320 . In this case, an input/output interface between the plurality of memory cells and the buffer memory 332 may be shared.

Referring to FIG. 11 , the general page buffer 422b of the nonvolatile memory sensor 400 may be included in the third semiconductor structure 430 . In this case, the plurality of memory cells and the input/output interface of the buffer memory 432 may be individually arranged.

Referring to FIG. 12 , the nonvolatile memory device 500 includes a first semiconductor structure 510 including a first semiconductor substrate 511 and a memory cell region 512 , a second semiconductor substrate 521 and a page buffer ( 522), and a third semiconductor substrate 531, a buffer memory 532, and peripheral circuits such as a row decoder 523, a sense amplifier 533, and a multiplexer 535 , and a third semiconductor structure 530 including other peripheral circuits 534 .

In the non-volatile memory device 500 according to an embodiment of the present invention, the page buffer 522 includes a sensing page buffer 522a directly connected to a plurality of memory cells, and a sensing page buffer 522a in a first direction ( For example, at least one general page buffer 522b serially connected in the Z direction) may be included.

Meanwhile, the page buffer 522 of the nonvolatile memory device 500 may be connected to a memory cell of the buffer memory 532 to exchange data. Data transmission may be controlled by peripheral circuits of the second semiconductor substrate 521 on which the page buffer 522 is formed. Accordingly, the normal page buffer 522b furthest from the sensing page buffer 522a among the at least one normal page buffer 522b may be connected to the control line CL for controlling data transmission. In this case, a buffer memory 532 may be connected between the control line CL and the bit line BL.

For example, a logic circuit including a buffer memory 532, a row decoder 523, and other peripheral circuits includes a plurality of vertical transistors defined by a source region, a channel region, and a drain region sequentially stacked in a first direction. can include However, this is merely an example and may not be limited.

13 and 14 are diagrams simply illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention. 15 and 16 are diagrams simply illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention. 17 and 18 are schematic diagrams illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIGS. 13 to 18 , each of the nonvolatile memory devices 600 , 700 , and 800 according to example embodiments may correspond to the nonvolatile memory device 200 shown in FIG. 9 .

Meanwhile, the structure of the first semiconductor structure 610 , 710 , 810 including the first semiconductor substrate 611 , 711 , 811 and the memory cell region 612 , 712 , 812 , and the first semiconductor structure 610 , 710 , 810), the connection relationship between the second semiconductor structures 620, 720, and 820, and the third semiconductor structures 630, 730, and 830 may correspond to the nonvolatile memory device 100 shown in FIG.

The nonvolatile memory device 600 shown in FIGS. 13 and 14, the nonvolatile memory device 700 shown in FIGS. 15 and 16, and the nonvolatile memory device 800 shown in FIGS. 17 and 18, respectively. The included third semiconductor structures 630, 730, and 830 may include a plurality of vertical transistors defined by sequentially stacked source regions, channel regions, and drain regions in a first direction (eg, Z direction). .

13 and 14 , in the nonvolatile memory device 600 according to an exemplary embodiment of the present invention, a row decoder 623 and a row decoder 623 are disposed under a second semiconductor substrate 621 where a page buffer 622 is disposed Other peripheral circuits 634 may be disposed. In this case, the row decoder 623 and other peripheral circuits 634 may include vertical transistors defined by sequentially stacked source regions, channel regions, and drain regions in the first direction, like the page buffer 622. can Other peripheral circuits 634 may exchange data with an external host while receiving command (CMD), address (ADDR), and control (CTRL) signals.

Since the size of the page buffer 622 is most affected by the increase in the storage capacity of the nonvolatile memory device 600, it may be arranged in the widest area. Accordingly, in the nonvolatile memory device 600 according to an embodiment of the present invention, the page buffer 622 is formed in a wide area of the second semiconductor substrate 621, and rows are formed under the second semiconductor substrate 621. Space utilization of the page buffer 622 may be maximized by arranging the decoder 623 and other peripheral circuits 634 .

Meanwhile, by forming the row decoder 623 and the other peripheral circuits 634 on the same layer, an increase in the length of the nonvolatile memory device 600 in the first direction can be minimized.

15 and 16, in a nonvolatile memory device 700 according to an embodiment of the present invention, a row decoder 723 and a row decoder 723 are disposed under a second semiconductor substrate 721 on which a page buffer 722 is disposed. Other peripheral circuits 734 may be disposed, and additional circuits 736 may be disposed below them. That is, the third semiconductor structure 730 may further include additional circuits 736 disposed between the peripheral circuits and the buffer memory 732 .

At this time, the row decoder 723, other peripheral circuits 734, and additional circuits 736 are sequentially stacked in the first direction, like the page buffer 722, in the source region, channel region, and drain region. It may include vertical transistors defined by

In one example, additional circuits 736 may include artificial intelligence (AI) function circuits that perform multiply and accelerate (MAC) operations on values stored in page buffer 722 and/or values stored in page buffer 722. An error correcting code (ECC) functional circuit that performs an error correction code (ECC) operation may be included. However, this is only one embodiment and is not limited, and the additional circuits 736 may be designed to perform various functions.

In the non-volatile memory device 700 according to an embodiment of the present invention, new functions can be freely added without being limited in area by arranging additional circuits 736 including vertical transistors on a separate layer from other circuits. can In particular, when the function performed by the memory controller is performed by the nonvolatile memory device 700, the performance of the nonvolatile memory device 700 itself can be improved.

As an example, if additional circuitry 736 is an error correcting code (ECC) functional circuit, additional circuitry 736 is placed closer to the input/output interface than page buffer 722 to perform error detection and correction functions for read data. It can be. More specifically, the additional circuit 736 may generate parity bits for write data to be written in the nonvolatile memory device 700, and the generated parity bits may be stored together with the write data. there is. During a data read operation in the nonvolatile memory device 700, the additional circuit 736 may correct an error in the read data using parity bits read together with the read data, and output the read data with the error corrected. .

For example, when the additional circuit 736 is an artificial intelligence (AI) function circuit, the additional circuit 736 may be disposed close to the page buffer 722 because it immediately calculates a value output from the page buffer 722 . However, this is merely an example and may not be limited.

17 and 18, in a nonvolatile memory device 800 according to an exemplary embodiment of the present invention, a row decoder 823 is provided under a second semiconductor substrate 821 on which a page buffer 822 is disposed. may be disposed, and other peripheral circuits 834 may be disposed below it. That is, the row decoder 823 may be disposed on a separate layer above the other peripheral circuits 834 .

19A to 19E are diagrams for explaining a process of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

19A to 19E may be views simply illustrating a manufacturing process of the nonvolatile memory device 100 shown in FIGS. 2 and 3 . The fabrication process of FIGS. 19A to 19E may be similarly applied to the nonvolatile memory devices 200, 300, 400, 500, 600, 700, and 800 according to other embodiments. However, this is merely an example and may not be limited. For example, the first semiconductor structure 110 , the second semiconductor structure 120 , and the third semiconductor structure 130 included in the nonvolatile memory device 100 may be independently manufactured regardless of order.

Referring to FIG. 19A , in the first semiconductor structure 110 , a memory cell region 112 including gate electrodes and channel structures CH may be formed on the first semiconductor substrate 111 . In this case, a first metal pad 119 for bonding the first semiconductor structure 110 to another structure may be formed on the top of the memory cell region 112 .

Referring to FIG. 19B , in the second semiconductor structure 120 , a peripheral circuit region including a page buffer 122 and a row decoder 123 may be formed on the second semiconductor substrate 121 . In this case, a second metal pad 129 for bonding the second semiconductor structure 120 to the first semiconductor structure 110 may be formed above the peripheral circuit region. For example, the position of the second metal pad 129 may correspond to the position of the first metal pad 119 .

As described above, contact pads 128 may be disposed below the second semiconductor substrate 121 to electrically connect the page buffer 122 and/or the row decoder 123 to an external circuit. However, this is only an example and is not limited, and the contact pad 128 may be disposed on the lower surface of the first semiconductor substrate 111 .

Referring to FIG. 19C , a connection structure 140a passing through the second semiconductor substrate 121 may be formed in the second semiconductor structure 120 . For example, the connection structure 140a may be electrically connected to the row decoder 123 of the second semiconductor structure 120 . However, this is only an example and is not limited thereto, and the connection structure 140a may be connected to the page buffer 122 of the second semiconductor structure 120 .

Referring to FIG. 19D, in the third semiconductor structure 130, on the third semiconductor substrate 131, a third metal pad 139 is connected through a connection via 138 penetrating the third semiconductor substrate 131. Other peripheral circuits 134 may be formed. At this time, the buffer memory 132 may be disposed on one side of the other peripheral circuits 134 . A connection structure 140b for bonding the third semiconductor structure 130 to the second semiconductor structure 120 may be formed above the third semiconductor structure 130 . For example, a position of the connection structure 140b included in the third semiconductor structure 130 may correspond to a position of the connection structure 140a included in the second semiconductor structure 120 .

Referring to FIG. 19E, the first semiconductor structure 110, the second semiconductor structure 120, and the third semiconductor structure 130 fabricated through FIGS. 19A to 19D are in a first direction (eg, Z direction). It can be bonded so that it is stacked. For example, the first semiconductor structure 110 may be bonded to the second semiconductor structure 120 through bonding of the first metal pad 119 and the second metal pad 129 . Also, the second semiconductor structure 120 may be bonded to the third semiconductor structure 130 through bonding of the connection structures 140a and 140b.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

100, 200, 300, 400, 500, 600, 700, 800: non-volatile memory device
110: first semiconductor structure 111: first semiconductor substrate
112: memory cell area 119: first metal pad
120: second semiconductor structure 121: second semiconductor substrate
122: page buffer 222a: sensing page buffer
222b: general page buffer 123: raw decoder
128: contact pad 129: second metal pad
130: third semiconductor structure 131: third semiconductor substrate
132 buffer memory 133 sense amplifier
134: other peripheral circuits 135: multiplexer
736 additional circuits 138 connecting vias
139: third metal pad 140: connection structure
150: peripheral circuit area 151: input/output buffer
152 voltage generator 153 control logic circuit
10: external device

Claims (10)

a first semiconductor substrate, a memory cell region including a plurality of memory cells disposed on the first semiconductor substrate, and a first metal pad disposed on the memory cell region, wherein the plurality of memory cells are connected to each other a first semiconductor structure defined by spaced apart stacked gate electrodes and channel structures penetrating the gate electrodes and connected to the first semiconductor substrate;
a second semiconductor structure including a second semiconductor substrate, a page buffer disposed on the second semiconductor substrate, and a second metal pad bonded to the first metal pad; and
a third semiconductor substrate, a buffer memory and peripheral circuits formed on the third semiconductor substrate, and a third metal pad connected to the peripheral circuits through connection vias penetrating the third semiconductor substrate; semiconductor structures; including,
The second semiconductor structure and the third semiconductor structure are connected to each other by a connection structure penetrating the second semiconductor substrate, and the page buffer includes the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure. A nonvolatile memory device including a plurality of vertical transistors defined by a source region, a channel region, and a drain region sequentially stacked in a first direction connected thereto.
According to claim 1,
The second semiconductor structure further comprises a row decoder on both sides of which the page buffer is disposed.
According to claim 1,
The page buffer includes a sensing page buffer directly connected to the plurality of memory cells and at least one general page buffer connected in series with the sensing page buffer;
The sensing page buffer and the at least one normal page buffer corresponding to each of the plurality of memory cells are arranged side by side in the first direction.
According to claim 3,
A general page buffer furthest from the sensing page buffer among the at least one general page buffer is connected to a bit line.
According to claim 3,
Among the at least one general page buffer, a normal page buffer that is furthest away from the sensing page buffer is connected to a control line for controlling data transfer, and the buffer memory included in the third semiconductor structure includes the control line and the bit line. A non-volatile memory device connected between
According to claim 1,
The page buffer includes a sensing page buffer connected between the plurality of memory cells and a bit line.
According to claim 6,
The third semiconductor structure further comprises at least one general page buffer connected to the sensing page buffer.
a first semiconductor substrate, a memory cell region including a plurality of memory cells disposed on the first semiconductor substrate, and a first metal pad disposed on the memory cell region, wherein the plurality of memory cells are connected to each other a first semiconductor structure defined by spaced apart stacked gate electrodes and channel structures penetrating the gate electrodes and connected to the first semiconductor substrate;
a second semiconductor structure including a second semiconductor substrate, a page buffer disposed on the second semiconductor substrate, and a second metal pad bonded to the first metal pad; and
A third semiconductor substrate, a buffer memory formed on the third semiconductor substrate, peripheral circuits disposed on the buffer memory, and a third connected to the peripheral circuits through connection vias penetrating the third semiconductor substrate. a third semiconductor structure including three metal pads and connected to the second semiconductor structure by a connection structure penetrating the second semiconductor substrate; including,
The peripheral circuits include a row decoder connected to the page buffer and other peripheral circuits for controlling the plurality of memory cells, and the third semiconductor structure includes the first semiconductor structure, the second semiconductor structure, and the first semiconductor structure. A non-volatile memory device including a plurality of vertical transistors defined by a source region, a channel region, and a drain region sequentially stacked in a first direction in which three semiconductor structures are connected.
According to claim 8,
The third semiconductor structure includes additional circuits disposed between the peripheral circuits and the buffer memory,
The additional circuits are selected from among a circuit that performs an Error Correction Code (ECC) operation on the values stored in the page buffer and a multiply and accumulate (MAC) operation on the values stored in the page buffer. A non-volatile memory device comprising at least one.
According to claim 8,
The row decoder is disposed above the peripheral circuits.

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